diff options
Diffstat (limited to 'abc80.sdc')
| -rw-r--r-- | abc80.sdc | 18 |
1 files changed, 18 insertions, 0 deletions
@@ -17,6 +17,24 @@ set_clock_groups -asynchronous \ -group {clock_24[*] pll2|*} \ -group {clock_27[*]} +set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[2]}] 7 +set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[1]}] 3 +set_multicycle_path -from [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] -to [get_keepers {mmuram:mmu|*portb*}] 2 +set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[2]}] 6 +set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[1]}] 2 +set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[2]}] 6 +set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[1]}] 2 +set_multicycle_path -from [get_clocks {pll1|*|clk[2]}] -to [get_keepers {sram_*_q*}] 2 +set_multicycle_path -start -from [get_keepers {sram_do*}] -to [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] 2 + +# I/O pin constraints +set_input_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_dq[*]}] +set_input_delay -clock {pll1|*|clk[0]} -max 3ns [get_ports {sram_dq[*]}] +# These numbers are a bit tricky, they appear to be relative to the *next* +# edge of the clock, so -max -1ns refer to a 6ns clock-to-pad delay. +set_output_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_*}] +set_output_delay -clock {pll1|*|clk[0]} -max -1ns [get_ports {sram_*}] + # Automatically calculate clock uncertainty to jitter and other effects. # Not supported for family Cyclone II #derive_clock_uncertainty |