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-rw-r--r--abc80.qsf14
1 files changed, 11 insertions, 3 deletions
diff --git a/abc80.qsf b/abc80.qsf
index 69a2a3d..11aaae5 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -365,7 +365,7 @@ set_global_assignment -name MAX_SCC_SIZE 50
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
@@ -557,7 +557,6 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sw
@@ -609,4 +608,13 @@ set_global_assignment -name VERILOG_FILE abc80.v
set_global_assignment -name SDC_FILE abc80.sdc
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SOURCE_FILE db/abc80.cmp.rdb
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation \ No newline at end of file