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authorH. Peter Anvin <hpa@zytor.com>2003-09-17 06:50:36 +0000
committerH. Peter Anvin <hpa@zytor.com>2003-09-17 06:50:36 +0000
commit97c4db3573ebb1bd87cf81b2da8e3d38ce6a651f (patch)
tree60b396212f35b8d839e30d4202f3fb90d36bcbab /t80pio
parent2951df3d335d63f60fe40c1b3bf0656f8c37d932 (diff)
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IEO is an output pin
Diffstat (limited to 't80pio')
-rw-r--r--t80pio/t80pio.v30
1 files changed, 14 insertions, 16 deletions
diff --git a/t80pio/t80pio.v b/t80pio/t80pio.v
index 900f50e..25626c3 100644
--- a/t80pio/t80pio.v
+++ b/t80pio/t80pio.v
@@ -33,7 +33,7 @@ module T80PIO (
input RD_n;
input RETI_n;
input IEI;
- input IEO;
+ output IEO;
input INT_n;
input [7:0] Ai;
output [7:0] Ao;
@@ -43,7 +43,7 @@ module T80PIO (
output BRDY;
reg [7:1] V; // Interrupt vector
- reg [1:0] M; // Operating mode
+ reg [1:0] M; // Operating mode (1's hot)
reg [7:0] IO; // Mode 3 direction mask
reg [3:0] ICW; // Interrupt control word
reg [7:0] MB; // Interrupt mask
@@ -99,11 +99,9 @@ module T80PIO (
// This computes the mode 3 interrupt condition
wire [7:0] xor_mask = ICW[1] ? 8'hFF : 8'h00;
- wire irq_cond = ICW[2] ?
- // "AND" mode
- (((read_data ^ xor_mask) & MB) == 0):
- // "OR" mode
- (((read_data ^ ~xor_mask) & MB) != 0);
+ wire irq_cond_and = ((read_data ^ xor_mask) & MB) == 0;
+ wire irq_cond_or = (~(read_data ^ xor_mask) & MB) != 0;
+ wire irq_cond = ICW[2] ? irq_cond_and : irq_cond_or;
always @(posedge CLK_n or negedge RESET_n)
begin
@@ -112,7 +110,7 @@ module T80PIO (
M <= 2'b01;
IO <= 0;
ICW <= 0;
- MB <= 0;
+ MB <= 8'hFF;
D <= 0;
io_next <= 0;
mb_next <= 0;
@@ -120,11 +118,11 @@ module T80PIO (
intak <= 0;
servicing_irq <= 0;
ASTB_n_old <= ASTB_n;
- Do_q <= ~0; // Output all ones when "inactive"
+ Do_q <= 8'hFF;
end
else
begin
- Do_q <= ~0;
+ Do_q <= 8'hFF;
if ( M1_n & ~IORQ_n & ~CE_n )
begin
@@ -179,12 +177,12 @@ module T80PIO (
end // case: 2'b11
endcase // case( { RD_n, CDsel } )
end // if ( ~IORQ_n & ~CE_n )
- else
- // Latch input data every cycle unless we are
- // currently being addressed by the CPU
- if ( latch_in )
- data_in <= Ai;
+ // Latch input data every cycle unless we are
+ // currently being addressed by the CPU
+ if ( latch_in )
+ data_in <= Ai;
+
// Mode 3 interrupt control
if ( M == 2'b11 )
begin
@@ -199,7 +197,7 @@ module T80PIO (
if ( M[0] == 1'b0 ) // Output or Bidir modes
o_data_flag <= 0; // Data sent, now empty
- else if ( M == 2'b01 ) // Input mode
+ else // Input mode
i_data_flag <= 1; // Data received, now full
end