INT# is an output

1 files changed, 7 insertions, 6 deletions

diff --git a/t80pio/t80pio.v b/t80pio/t80pio.v
index 25626c3..5243fa1 100644
--- a/t80pio/t80pio.v
+++ b/t80pio/t80pio.v
@@ -34,7 +34,7 @@ module T80PIO (
    input 	RETI_n;
    input 	IEI;
    output 	IEO;
-   input 	INT_n;
+   output 	INT_n;
    input [7:0] 	Ai;
    output [7:0]	Ao;
    input 	ASTB_n;
@@ -64,8 +64,9 @@ module T80PIO (
 	      (M == 2'b01) ? data_in :
 	      (M == 2'b10) ? data_in :
 	      /* (M == 2'b11) */ (D & ~IO) | (data_in & IO);
-   
-   assign Do = Do_q;
+
+   // It seems we can't afford a one-cycle delay in responding to INTAK
+   assign Do = ( ~M1_n & ~IORQ_n & (my_irq | intak) ) ? { V, 1'b0 } : Do_q;
    
    // Output data word (note: pins which would be tristated on Z80PIO
    // we feed back the input.)
@@ -93,8 +94,9 @@ module T80PIO (
    reg 	  need_irq;		// Need to issue interrupt
    reg 	  intak;		// INTAK in process
    reg 	  servicing_irq;	// Waiting for RETI
+   wire   my_irq = need_irq & IEI;
 
-   assign INT_n = ~( need_irq & IEI );
+   assign INT_n = ~my_irq;
    assign IEO   = IEI & ~need_irq & ~intak & ~servicing_irq;
 
    // This computes the mode 3 interrupt condition
@@ -207,9 +209,8 @@ module T80PIO (
 	     // Actual interrupt-generating logic.  We have two
 	     // possible states to be in; both can be active:
 	     // need_irq (INT# -> INTAK) and servicing_irq (INTAK -> RETI).
-	     if ( ~M1_n & ~IORQ_n & ((need_irq & IEI) | intak) )
+	     if ( ~M1_n & ~IORQ_n & (my_irq | intak) )
 	       begin
-		  Do_q <= { V, 1'b0 };
 		  servicing_irq <= 1;
 		  intak <= 1;
 		  need_irq <= 0;