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authorH. Peter Anvin <hpa@zytor.com>2003-09-12 21:40:10 +0000
committerH. Peter Anvin <hpa@zytor.com>2003-09-12 21:40:10 +0000
commit63e49239d5b3852d9ce45a2816edc024361cc7d3 (patch)
tree66eaed6e947341e252db034a7a87165b0af2887f /t80pio
parent680781246fb69a8af28cf7363c8f925a5391cd52 (diff)
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Fix typos; syntax errors. It now compiles syntactically.
Diffstat (limited to 't80pio')
-rw-r--r--t80pio/t80pio.v23
1 files changed, 11 insertions, 12 deletions
diff --git a/t80pio/t80pio.v b/t80pio/t80pio.v
index cdf78ca..ba2676b 100644
--- a/t80pio/t80pio.v
+++ b/t80pio/t80pio.v
@@ -9,6 +9,7 @@ module T80PIO (
M1_n,
IORQ_n,
RD_n,
+ RETI_n,
IEI,
IEO,
INT_n,
@@ -30,6 +31,7 @@ module T80PIO (
input M1_n;
input IORQ_n;
input RD_n;
+ input RETI_n;
input IEI;
input IEO;
input INT_n;
@@ -54,16 +56,15 @@ module T80PIO (
reg o_data_flag; // Have input data
reg ASTB_n_old; // Previous ASTB_n
- wire [7:0] data; // "Current data"
reg [7:0] data_in; // Latched input data (Di)
-
+
// Data as it would be read by the CPU
- assign read_data =
- (M == 2'b00) ? D :
- (M == 2'b01) ? data_in :
- (M == 2'b10) ? data_in :
- /* (M == 2'b11) */ (D & ~IO) | (data_in & IO);
-
+ wire [7:0] read_data =
+ (M == 2'b00) ? D :
+ (M == 2'b01) ? data_in :
+ (M == 2'b10) ? data_in :
+ /* (M == 2'b11) */ (D & ~IO) | (data_in & IO);
+
assign Do = Do_q;
// Output data word (note: pins which would be tristated on Z80PIO
@@ -82,11 +83,11 @@ module T80PIO (
assign BRDY = (M == 2'b10) && ~i_data_flag;
// This signal is high if we should latch the input data
- assign latch_in =
+ wire latch_in =
((M == 2'b01 && ~ASTB_n) |
(M == 2'b10 && ~BSTB_n) |
(M == 2'b11)) &
- ~( ~cpu_iorq_n & ~cpu_ce_n );
+ ~( ~IORQ_n & ~CE_n );
// Output INT#
reg need_irq; // Need to issue interrupt
@@ -224,5 +225,3 @@ module T80PIO (
end // else: !if( !RESET_n )
end // always @ (posedge CLK_n or negedge RESET_n)
endmodule // T80PIO
-
- \ No newline at end of file