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authorH. Peter Anvin <hpa@zytor.com>2016-11-10 20:06:19 -0800
committerH. Peter Anvin <hpa@zytor.com>2016-11-10 20:06:19 -0800
commitf82772116d1024cea9a05278394a0550a75e3427 (patch)
tree8914be76cfe5db7494897b0c4281d33fe8628af8 /sync.v
parente2851010ab6a08d49d89b40c65f9c2802f104cad (diff)
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Finally: a functional version of the 200 MHz SRAM
The 200 MHz SRAM seems to finally work. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'sync.v')
-rw-r--r--sync.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/sync.v b/sync.v
index 83b12f6..a4060c1 100644
--- a/sync.v
+++ b/sync.v
@@ -51,13 +51,13 @@ module synchronizer(reset, clk, enable, d, q);
always @(posedge clk)
if (reset)
d_q <= {width{1'b0}};
- else // if (stage_enable[0])
+ else if (stage_enable[0])
d_q <= d;
always @(posedge clk)
if (reset)
stage[1] <= {width{1'b0}};
- else // if (stage_enable[1])
+ else if (stage_enable[1])
stage[1] <= d_q;
genvar i;
@@ -67,7 +67,7 @@ module synchronizer(reset, clk, enable, d, q);
always @(posedge clk)
if (reset)
stage[i] <= {width{1'b0}};
- else // if (stage_enable[i])
+ else if (stage_enable[i])
stage[i] <= stage[i-1];
end
endgenerate