WIP: adjust SRAM timing to be able to share with another device

Infrastructure for changing the SRAM timing to add another shared
device (intended to be the Neopixel driver.)  This means upping the
SRAM state machine clock to 200 MHz; move video_clk to pll2 to be able
to generate that output.  It actually gets closer to proper VGA
timing, but at the expense of needing a synchronizing FIFO for the fg
unit.

This also clears a lot of timing warnings.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/sync.v b/sync.v
new file mode 100644
index 0000000..b1f3077
--- /dev/null
+++ b/sync.v
@@ -0,0 +1,61 @@
+// -----------------------------------------------------------------------
+//
+//   Copyright 2016 H. Peter Anvin - All Rights Reserved
+//
+//   This program is free software; you can redistribute it and/or modify
+//   it under the terms of the GNU General Public License as published by
+//   the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
+//   Boston MA 02110-1301, USA; either version 2 of the License, or
+//   (at your option) any later version; incorporated herein by reference.
+//
+// -----------------------------------------------------------------------
+
+//
+// Synchronize data from different clock domains.  This is pretty trivial
+// stuff in theory; most of the complexity comes from giving hints
+// to the synthesizer.  Good reason to make this a parameterized module.
+//
+
+(* altera_attribute = "-name synchronizer_identification forced_if_asynchronous; -name auto_shift_register_recognition off; -name global_signal off" *)
+module synchronize(reset, clk, d, q);
+   parameter width  = 1;	// Minimum 1
+   parameter stages = 2;	// Minimum 2
+
+   input reset;
+   input clk;
+   input [width-1:0] d;
+   output [width-1:0] q;
+
+   // Inputs to these modules are inherently asynchronous
+   (* altera_attribute = "-name cut on -from * ; -name sdc_statement \"set_false_path -to [get_keepers {synchronize:*|d_q[*] *|synchronize:*|d_q[*]}]\"" *)
+       reg [width-1:0] d_q;
+
+   reg [width-1:0] stage[1:stages-1];
+
+   assign q = stage[stages-1];
+
+   always @(posedge reset or posedge clk)
+     if (reset)
+       d_q <= {width{1'b0}};
+     else
+       d_q <= d;
+
+   always @(posedge reset or posedge clk)
+     if (reset)
+       stage[1] <= {width{1'b0}};
+     else
+       stage[1] <= d_q;
+
+   genvar i;
+
+   generate
+      for (i = 2; i < stages; i = i + 1)
+	begin: gen_stages
+	   always @(posedge reset or posedge clk)
+	     if (reset)
+	       stage[i] <= {width{1'b0}};
+	     else
+	       stage[i] <= stage[i-1];
+	end
+   endgenerate
+endmodule