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authorH. Peter Anvin <hpa@zytor.com>2006-02-20 07:37:16 +0000
committerH. Peter Anvin <hpa@zytor.com>2006-02-20 07:37:16 +0000
commitd00b0bde372be8a3fd84ef5cac3d3256dfc2cc0e (patch)
tree80c9093c81e6ff58e83c47a074adfa38aee5aa2f /sound.v
parent6010d2d8ed8e8d923f5561c8c7bf930f9b07ea31 (diff)
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Verilog 2001 syntax fixes
Diffstat (limited to 'sound.v')
-rw-r--r--sound.v7
1 files changed, 2 insertions, 5 deletions
diff --git a/sound.v b/sound.v
index af98d12..59aa34c 100644
--- a/sound.v
+++ b/sound.v
@@ -141,14 +141,12 @@ module oneshot(
input clk, // 25 MHz
input clk_en, // One pulse every 16 us (62.5 kHz)
input inhibit,
- output oneshot
+ output reg oneshot
);
reg out = 0;
reg inhibit1 = 0;
reg [10:0] ctr = 0;
- reg oneshot;
-
wire ctr_or = |ctr;
always @(posedge clk)
@@ -192,9 +190,8 @@ module envelope_shape(
input clk, // 25 MHz
input clk_en, // One pulse every 16 us (62.5 kHz)
input envelope,
- output [13:0] env_mag
+ output reg [13:0] env_mag
);
- reg [13:0] env_mag = 0;
always @(posedge clk)
if ( clk_en )