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authorH. Peter Anvin <hpa@zytor.com>2007-06-10 00:12:08 -0700
committerH. Peter Anvin <hpa@zytor.com>2007-06-10 00:12:08 -0700
commit3bf05ad6c6cc4b95097bc1b7104914090f3c5f77 (patch)
treebc8c89f132b10f650884d52488f2aee065ab8843
parent93bf8766459e27a558aa14cd0f77bd5d893e59e2 (diff)
parent28b0de5001e4f7d085c856e89933eab660b16025 (diff)
downloadabc80-3bf05ad6c6cc4b95097bc1b7104914090f3c5f77.tar.gz
abc80-3bf05ad6c6cc4b95097bc1b7104914090f3c5f77.tar.xz
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Merge branch 'trunk'
-rw-r--r--CHANGES3
-rw-r--r--README4
2 files changed, 4 insertions, 3 deletions
diff --git a/CHANGES b/CHANGES
index 4b6890b..e8eccea 100644
--- a/CHANGES
+++ b/CHANGES
@@ -13,9 +13,6 @@ Changes in release 18:
* Update the Z80 assembler, and include it in the release.
-* Change the CPU core from T80 to TV80, so the design is now all
- Verilog.
-
* This file changed from ISO-8859-1 encoding to UTF-8 encoding.
diff --git a/README b/README
index 9241bc4..6b49aed 100644
--- a/README
+++ b/README
@@ -6,6 +6,10 @@ This version uses an "Altera Nios Development Kit, Cyclone Edition"
combined with a "AleaRep Lancelot" daughtercard (for
VGA/Keyboard/Mouse/Sound -- see http://www.fpga.nl/).
+To build, run "make" in the top directory on a Unix/Linux machine,
+or under Cygwin on a Windows machine, then build the Quartus II
+project "abc80.qsf".
+
As provided, the design runs at 25 MHz (the real ABC80 ran at 3 MHz.)
SW3 is set up as a "turbo button", selecting 25, 12, 6, or 3 MHz
operation. Turbo can also be selected via "out (144),n" where n=0 for