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authorH. Peter Anvin <hpa@zytor.com>2011-11-01 21:01:45 -0700
committerH. Peter Anvin <hpa@zytor.com>2011-11-01 21:01:45 -0700
commitefaa21c2db63985a3a84288d823ba9c3ba8b89b7 (patch)
tree79d908196b9914da62640957c33c2a837d3d9924
parent63aed87d116e843be2e17aa0e4a199f99f23d24c (diff)
downloadabc80-efaa21c2db63985a3a84288d823ba9c3ba8b89b7.tar.gz
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Add support for Olimex MOD-ENC28J60 Ethernet controller on GPIO1
One can attach an Olimex MOD-ENC28J60 Ethernet controller to the GPIO1 port via an easy to make cable. This allows the MOD-ENC28J60 to be addressed from ABC80.
-rw-r--r--CHANGES28
-rw-r--r--abc80.qsf887
-rw-r--r--abc80.v63
-rw-r--r--enc28j60.v216
4 files changed, 746 insertions, 448 deletions
diff --git a/CHANGES b/CHANGES
index 9f7f8a6..91c7fb1 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,3 +1,31 @@
+Changes in release DE1-19:
+--------------------------
+* Support an Olimex MOD-ENC28J60 Ethernet module attached to GPIO1
+ pins 29-38. LEDG2 is now the selected LED for the Ethernet card.
+
+ The Ethernet card is ABC-bus select 9 (OUT 1,9) and uses the
+ following commands:
+
+ OUT# (OUT 0) Send a byte to the Ethernet controller, leave CS# low
+ C1# (OUT 2) Send a byte to the Ethernet controller, pull CS# high
+ C2# (OUT 2) Send FF byte to the Ethernet controller, leave CS# low
+ C3# (OUT 4) Local reset
+
+ INP# (IN 0) Read a byte from the Ethernet controller, leave CS# low
+ STATUS# (IN 1) Read a byte from the Ethernet controller, pull CS# high
+
+ Note that reads are "delayed" by one cycle, so it is necessary to
+ write a dummy byte before doing the first read.
+
+ LEDG0 - disk (SD) activity (for real!)
+ LEDG1 - disk selected (like the old LED 0)
+ LEDG2 - Ethernet selected
+ LEDG3 - CAS: relay (OUT 58,32)
+ LEDG4 - CAS: data out (OUT 58,64)
+ LEDG5 - turbo 3 (25 MHz)
+ LEDG6 - turbo 2 (12, 25 MHz)
+ LEDG7 - turbo 1 (6, 12, 25 MHz)
+
Changes in release DE1-18:
--------------------------
* Use a 6x10 character matrix as the original ABC80/800 did, instead
diff --git a/abc80.qsf b/abc80.qsf
index 89f0423..3eb15c6 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -31,413 +31,413 @@
# Project-Wide Assignments
# ========================
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.0
# Pin & Location Assignments
# ==========================
-set_location_assignment PIN_A13 -to gpio_0[0]
-set_location_assignment PIN_B13 -to gpio_0[1]
-set_location_assignment PIN_A14 -to gpio_0[2]
-set_location_assignment PIN_B14 -to gpio_0[3]
-set_location_assignment PIN_A15 -to gpio_0[4]
-set_location_assignment PIN_B15 -to gpio_0[5]
-set_location_assignment PIN_A16 -to gpio_0[6]
-set_location_assignment PIN_B16 -to gpio_0[7]
-set_location_assignment PIN_A17 -to gpio_0[8]
-set_location_assignment PIN_B17 -to gpio_0[9]
-set_location_assignment PIN_A18 -to gpio_0[10]
-set_location_assignment PIN_B18 -to gpio_0[11]
-set_location_assignment PIN_A19 -to gpio_0[12]
-set_location_assignment PIN_B19 -to gpio_0[13]
-set_location_assignment PIN_A20 -to gpio_0[14]
-set_location_assignment PIN_B20 -to gpio_0[15]
-set_location_assignment PIN_C21 -to gpio_0[16]
-set_location_assignment PIN_C22 -to gpio_0[17]
-set_location_assignment PIN_D21 -to gpio_0[18]
-set_location_assignment PIN_D22 -to gpio_0[19]
-set_location_assignment PIN_E21 -to gpio_0[20]
-set_location_assignment PIN_E22 -to gpio_0[21]
-set_location_assignment PIN_F21 -to gpio_0[22]
-set_location_assignment PIN_F22 -to gpio_0[23]
-set_location_assignment PIN_G21 -to gpio_0[24]
-set_location_assignment PIN_G22 -to gpio_0[25]
-set_location_assignment PIN_J21 -to gpio_0[26]
-set_location_assignment PIN_J22 -to gpio_0[27]
-set_location_assignment PIN_K21 -to gpio_0[28]
-set_location_assignment PIN_K22 -to gpio_0[29]
-set_location_assignment PIN_J19 -to gpio_0[30]
-set_location_assignment PIN_J20 -to gpio_0[31]
-set_location_assignment PIN_J18 -to gpio_0[32]
-set_location_assignment PIN_K20 -to gpio_0[33]
-set_location_assignment PIN_L19 -to gpio_0[34]
-set_location_assignment PIN_L18 -to gpio_0[35]
-set_location_assignment PIN_H12 -to gpio_1[0]
-set_location_assignment PIN_H13 -to gpio_1[1]
-set_location_assignment PIN_H14 -to gpio_1[2]
-set_location_assignment PIN_G15 -to gpio_1[3]
-set_location_assignment PIN_E14 -to gpio_1[4]
-set_location_assignment PIN_E15 -to gpio_1[5]
-set_location_assignment PIN_F15 -to gpio_1[6]
-set_location_assignment PIN_G16 -to gpio_1[7]
-set_location_assignment PIN_F12 -to gpio_1[8]
-set_location_assignment PIN_F13 -to gpio_1[9]
-set_location_assignment PIN_C14 -to gpio_1[10]
-set_location_assignment PIN_D14 -to gpio_1[11]
-set_location_assignment PIN_D15 -to gpio_1[12]
-set_location_assignment PIN_D16 -to gpio_1[13]
-set_location_assignment PIN_C17 -to gpio_1[14]
-set_location_assignment PIN_C18 -to gpio_1[15]
-set_location_assignment PIN_C19 -to gpio_1[16]
-set_location_assignment PIN_C20 -to gpio_1[17]
-set_location_assignment PIN_D19 -to gpio_1[18]
-set_location_assignment PIN_D20 -to gpio_1[19]
-set_location_assignment PIN_E20 -to gpio_1[20]
-set_location_assignment PIN_F20 -to gpio_1[21]
-set_location_assignment PIN_E19 -to gpio_1[22]
-set_location_assignment PIN_E18 -to gpio_1[23]
-set_location_assignment PIN_G20 -to gpio_1[24]
-set_location_assignment PIN_G18 -to gpio_1[25]
-set_location_assignment PIN_G17 -to gpio_1[26]
-set_location_assignment PIN_H17 -to gpio_1[27]
-set_location_assignment PIN_J15 -to gpio_1[28]
-set_location_assignment PIN_H18 -to gpio_1[29]
-set_location_assignment PIN_N22 -to gpio_1[30]
-set_location_assignment PIN_N21 -to gpio_1[31]
-set_location_assignment PIN_P15 -to gpio_1[32]
-set_location_assignment PIN_N15 -to gpio_1[33]
-set_location_assignment PIN_P17 -to gpio_1[34]
-set_location_assignment PIN_P18 -to gpio_1[35]
-set_location_assignment PIN_L22 -to sw[0]
-set_location_assignment PIN_L21 -to sw[1]
-set_location_assignment PIN_M22 -to sw[2]
-set_location_assignment PIN_V12 -to sw[3]
-set_location_assignment PIN_W12 -to sw[4]
-set_location_assignment PIN_U12 -to sw[5]
-set_location_assignment PIN_U11 -to sw[6]
-set_location_assignment PIN_M2 -to sw[7]
-set_location_assignment PIN_M1 -to sw[8]
-set_location_assignment PIN_L2 -to sw[9]
-set_location_assignment PIN_J2 -to s7_0[0]
-set_location_assignment PIN_J1 -to s7_0[1]
-set_location_assignment PIN_H2 -to s7_0[2]
-set_location_assignment PIN_H1 -to s7_0[3]
-set_location_assignment PIN_F2 -to s7_0[4]
-set_location_assignment PIN_F1 -to s7_0[5]
-set_location_assignment PIN_E2 -to s7_0[6]
-set_location_assignment PIN_E1 -to s7_1[0]
-set_location_assignment PIN_H6 -to s7_1[1]
-set_location_assignment PIN_H5 -to s7_1[2]
-set_location_assignment PIN_H4 -to s7_1[3]
-set_location_assignment PIN_G3 -to s7_1[4]
-set_location_assignment PIN_D2 -to s7_1[5]
-set_location_assignment PIN_D1 -to s7_1[6]
-set_location_assignment PIN_G5 -to s7_2[0]
-set_location_assignment PIN_G6 -to s7_2[1]
-set_location_assignment PIN_C2 -to s7_2[2]
-set_location_assignment PIN_C1 -to s7_2[3]
-set_location_assignment PIN_E3 -to s7_2[4]
-set_location_assignment PIN_E4 -to s7_2[5]
-set_location_assignment PIN_D3 -to s7_2[6]
-set_location_assignment PIN_F4 -to s7_3[0]
-set_location_assignment PIN_D5 -to s7_3[1]
-set_location_assignment PIN_D6 -to s7_3[2]
-set_location_assignment PIN_J4 -to s7_3[3]
-set_location_assignment PIN_L8 -to s7_3[4]
-set_location_assignment PIN_F3 -to s7_3[5]
-set_location_assignment PIN_D4 -to s7_3[6]
-set_location_assignment PIN_R22 -to key_n[0]
-set_location_assignment PIN_R21 -to key_n[1]
-set_location_assignment PIN_T22 -to key_n[2]
-set_location_assignment PIN_T21 -to key_n[3]
-set_location_assignment PIN_R20 -to ledr[0]
-set_location_assignment PIN_R19 -to ledr[1]
-set_location_assignment PIN_U19 -to ledr[2]
-set_location_assignment PIN_Y19 -to ledr[3]
-set_location_assignment PIN_T18 -to ledr[4]
-set_location_assignment PIN_V19 -to ledr[5]
-set_location_assignment PIN_Y18 -to ledr[6]
-set_location_assignment PIN_U18 -to ledr[7]
-set_location_assignment PIN_R18 -to ledr[8]
-set_location_assignment PIN_R17 -to ledr[9]
-set_location_assignment PIN_U22 -to ledg[0]
-set_location_assignment PIN_U21 -to ledg[1]
-set_location_assignment PIN_V22 -to ledg[2]
-set_location_assignment PIN_V21 -to ledg[3]
-set_location_assignment PIN_W22 -to ledg[4]
-set_location_assignment PIN_W21 -to ledg[5]
-set_location_assignment PIN_Y22 -to ledg[6]
-set_location_assignment PIN_Y21 -to ledg[7]
-set_location_assignment PIN_D12 -to clock_27[0]
-set_location_assignment PIN_E12 -to clock_27[1]
-set_location_assignment PIN_B12 -to clock_24[0]
-set_location_assignment PIN_A12 -to clock_24[1]
-set_location_assignment PIN_L1 -to clock_50
-set_location_assignment PIN_M21 -to ext_clock
-set_location_assignment PIN_H15 -to ps2_clk
-set_location_assignment PIN_J14 -to ps2_dat
-set_location_assignment PIN_F14 -to uart_rxd
-set_location_assignment PIN_G12 -to uart_txd
-set_location_assignment PIN_E8 -to tdi
-set_location_assignment PIN_D8 -to tcs
-set_location_assignment PIN_C7 -to tck
-set_location_assignment PIN_D7 -to tdo
-set_location_assignment PIN_D9 -to vga_r[0]
-set_location_assignment PIN_C9 -to vga_r[1]
-set_location_assignment PIN_A7 -to vga_r[2]
-set_location_assignment PIN_B7 -to vga_r[3]
-set_location_assignment PIN_B8 -to vga_g[0]
-set_location_assignment PIN_C10 -to vga_g[1]
-set_location_assignment PIN_B9 -to vga_g[2]
-set_location_assignment PIN_A8 -to vga_g[3]
-set_location_assignment PIN_A9 -to vga_b[0]
-set_location_assignment PIN_D11 -to vga_b[1]
-set_location_assignment PIN_A10 -to vga_b[2]
-set_location_assignment PIN_B10 -to vga_b[3]
-set_location_assignment PIN_A11 -to vga_hs
-set_location_assignment PIN_B11 -to vga_vs
-set_location_assignment PIN_A3 -to i2c_scl
-set_location_assignment PIN_B3 -to i2c_sda
-set_location_assignment PIN_A6 -to aud_adclrck
-set_location_assignment PIN_B6 -to aud_adcdat
-set_location_assignment PIN_A5 -to aud_daclrck
-set_location_assignment PIN_B5 -to aud_dacdat
-set_location_assignment PIN_B4 -to aud_xck
-set_location_assignment PIN_A4 -to aud_bclk
-set_location_assignment PIN_W4 -to dram_a[0]
-set_location_assignment PIN_W5 -to dram_a[1]
-set_location_assignment PIN_Y3 -to dram_a[2]
-set_location_assignment PIN_Y4 -to dram_a[3]
-set_location_assignment PIN_R6 -to dram_a[4]
-set_location_assignment PIN_R5 -to dram_a[5]
-set_location_assignment PIN_P6 -to dram_a[6]
-set_location_assignment PIN_P5 -to dram_a[7]
-set_location_assignment PIN_P3 -to dram_a[8]
-set_location_assignment PIN_N4 -to dram_a[9]
-set_location_assignment PIN_W3 -to dram_a[10]
-set_location_assignment PIN_N6 -to dram_a[11]
-set_location_assignment PIN_U3 -to dram_ba[0]
-set_location_assignment PIN_V4 -to dram_ba[1]
-set_location_assignment PIN_T3 -to dram_cas_n
-set_location_assignment PIN_N3 -to dram_cke
-set_location_assignment PIN_U4 -to dram_clk
-set_location_assignment PIN_T6 -to dram_cs_n
-set_location_assignment PIN_U1 -to dram_dq[0]
-set_location_assignment PIN_U2 -to dram_dq[1]
-set_location_assignment PIN_V1 -to dram_dq[2]
-set_location_assignment PIN_V2 -to dram_dq[3]
-set_location_assignment PIN_W1 -to dram_dq[4]
-set_location_assignment PIN_W2 -to dram_dq[5]
-set_location_assignment PIN_Y1 -to dram_dq[6]
-set_location_assignment PIN_Y2 -to dram_dq[7]
-set_location_assignment PIN_N1 -to dram_dq[8]
-set_location_assignment PIN_N2 -to dram_dq[9]
-set_location_assignment PIN_P1 -to dram_dq[10]
-set_location_assignment PIN_P2 -to dram_dq[11]
-set_location_assignment PIN_R1 -to dram_dq[12]
-set_location_assignment PIN_R2 -to dram_dq[13]
-set_location_assignment PIN_T1 -to dram_dq[14]
-set_location_assignment PIN_T2 -to dram_dq[15]
-set_location_assignment PIN_R7 -to dram_dqm[0]
-set_location_assignment PIN_T5 -to dram_ras_n
-set_location_assignment PIN_M5 -to dram_dqm[1]
-set_location_assignment PIN_R8 -to dram_we_n
-set_location_assignment PIN_AB20 -to fl_a[0]
-set_location_assignment PIN_AA14 -to fl_a[1]
-set_location_assignment PIN_Y16 -to fl_a[2]
-set_location_assignment PIN_R15 -to fl_a[3]
-set_location_assignment PIN_T15 -to fl_a[4]
-set_location_assignment PIN_U15 -to fl_a[5]
-set_location_assignment PIN_V15 -to fl_a[6]
-set_location_assignment PIN_W15 -to fl_a[7]
-set_location_assignment PIN_R14 -to fl_a[8]
-set_location_assignment PIN_Y13 -to fl_a[9]
-set_location_assignment PIN_R12 -to fl_a[10]
-set_location_assignment PIN_T12 -to fl_a[11]
-set_location_assignment PIN_AB14 -to fl_a[12]
-set_location_assignment PIN_AA13 -to fl_a[13]
-set_location_assignment PIN_AB13 -to fl_a[14]
-set_location_assignment PIN_AA12 -to fl_a[15]
-set_location_assignment PIN_AB12 -to fl_a[16]
-set_location_assignment PIN_AA20 -to fl_a[17]
-set_location_assignment PIN_U14 -to fl_a[18]
-set_location_assignment PIN_V14 -to fl_a[19]
-set_location_assignment PIN_U13 -to fl_a[20]
-set_location_assignment PIN_R13 -to fl_a[21]
-set_location_assignment PIN_AB16 -to fl_dq[0]
-set_location_assignment PIN_AA16 -to fl_dq[1]
-set_location_assignment PIN_AB17 -to fl_dq[2]
-set_location_assignment PIN_AA17 -to fl_dq[3]
-set_location_assignment PIN_AB18 -to fl_dq[4]
-set_location_assignment PIN_AA18 -to fl_dq[5]
-set_location_assignment PIN_AB19 -to fl_dq[6]
-set_location_assignment PIN_AA19 -to fl_dq[7]
-set_location_assignment PIN_AA15 -to fl_oe_n
-set_location_assignment PIN_W14 -to fl_rst_n
-set_location_assignment PIN_Y14 -to fl_we_n
-set_location_assignment PIN_AB15 -to fl_ce_n
-set_location_assignment PIN_AA3 -to sram_a[0]
-set_location_assignment PIN_AB3 -to sram_a[1]
-set_location_assignment PIN_AA4 -to sram_a[2]
-set_location_assignment PIN_AB4 -to sram_a[3]
-set_location_assignment PIN_AA5 -to sram_a[4]
-set_location_assignment PIN_AB10 -to sram_a[5]
-set_location_assignment PIN_AA11 -to sram_a[6]
-set_location_assignment PIN_AB11 -to sram_a[7]
-set_location_assignment PIN_V11 -to sram_a[8]
-set_location_assignment PIN_W11 -to sram_a[9]
-set_location_assignment PIN_R11 -to sram_a[10]
-set_location_assignment PIN_T11 -to sram_a[11]
-set_location_assignment PIN_Y10 -to sram_a[12]
-set_location_assignment PIN_U10 -to sram_a[13]
-set_location_assignment PIN_R10 -to sram_a[14]
-set_location_assignment PIN_T7 -to sram_a[15]
-set_location_assignment PIN_Y6 -to sram_a[16]
-set_location_assignment PIN_Y5 -to sram_a[17]
-set_location_assignment PIN_AB5 -to sram_ce_n
-set_location_assignment PIN_AA6 -to sram_dq[0]
-set_location_assignment PIN_AB6 -to sram_dq[1]
-set_location_assignment PIN_AA7 -to sram_dq[2]
-set_location_assignment PIN_AB7 -to sram_dq[3]
-set_location_assignment PIN_AA8 -to sram_dq[4]
-set_location_assignment PIN_AB8 -to sram_dq[5]
-set_location_assignment PIN_AA9 -to sram_dq[6]
-set_location_assignment PIN_AB9 -to sram_dq[7]
-set_location_assignment PIN_Y9 -to sram_dq[8]
-set_location_assignment PIN_W9 -to sram_dq[9]
-set_location_assignment PIN_V9 -to sram_dq[10]
-set_location_assignment PIN_U9 -to sram_dq[11]
-set_location_assignment PIN_R9 -to sram_dq[12]
-set_location_assignment PIN_W8 -to sram_dq[13]
-set_location_assignment PIN_V8 -to sram_dq[14]
-set_location_assignment PIN_U8 -to sram_dq[15]
-set_location_assignment PIN_Y7 -to sram_be_n[0]
-set_location_assignment PIN_T8 -to sram_oe_n
-set_location_assignment PIN_W7 -to sram_be_n[1]
-set_location_assignment PIN_AA10 -to sram_we_n
-set_location_assignment PIN_V20 -to sd_clk
-set_location_assignment PIN_Y20 -to sd_cmd
-set_location_assignment PIN_W20 -to sd_dat0
-set_location_assignment PIN_U20 -to sd_dat3
+set_location_assignment PIN_A13 -to gpio_0[0]
+set_location_assignment PIN_B13 -to gpio_0[1]
+set_location_assignment PIN_A14 -to gpio_0[2]
+set_location_assignment PIN_B14 -to gpio_0[3]
+set_location_assignment PIN_A15 -to gpio_0[4]
+set_location_assignment PIN_B15 -to gpio_0[5]
+set_location_assignment PIN_A16 -to gpio_0[6]
+set_location_assignment PIN_B16 -to gpio_0[7]
+set_location_assignment PIN_A17 -to gpio_0[8]
+set_location_assignment PIN_B17 -to gpio_0[9]
+set_location_assignment PIN_A18 -to gpio_0[10]
+set_location_assignment PIN_B18 -to gpio_0[11]
+set_location_assignment PIN_A19 -to gpio_0[12]
+set_location_assignment PIN_B19 -to gpio_0[13]
+set_location_assignment PIN_A20 -to gpio_0[14]
+set_location_assignment PIN_B20 -to gpio_0[15]
+set_location_assignment PIN_C21 -to gpio_0[16]
+set_location_assignment PIN_C22 -to gpio_0[17]
+set_location_assignment PIN_D21 -to gpio_0[18]
+set_location_assignment PIN_D22 -to gpio_0[19]
+set_location_assignment PIN_E21 -to gpio_0[20]
+set_location_assignment PIN_E22 -to gpio_0[21]
+set_location_assignment PIN_F21 -to gpio_0[22]
+set_location_assignment PIN_F22 -to gpio_0[23]
+set_location_assignment PIN_G21 -to gpio_0[24]
+set_location_assignment PIN_G22 -to gpio_0[25]
+set_location_assignment PIN_J21 -to gpio_0[26]
+set_location_assignment PIN_J22 -to gpio_0[27]
+set_location_assignment PIN_K21 -to gpio_0[28]
+set_location_assignment PIN_K22 -to gpio_0[29]
+set_location_assignment PIN_J19 -to gpio_0[30]
+set_location_assignment PIN_J20 -to gpio_0[31]
+set_location_assignment PIN_J18 -to gpio_0[32]
+set_location_assignment PIN_K20 -to gpio_0[33]
+set_location_assignment PIN_L19 -to gpio_0[34]
+set_location_assignment PIN_L18 -to gpio_0[35]
+set_location_assignment PIN_H12 -to gpio_1[0]
+set_location_assignment PIN_H13 -to gpio_1[1]
+set_location_assignment PIN_H14 -to gpio_1[2]
+set_location_assignment PIN_G15 -to gpio_1[3]
+set_location_assignment PIN_E14 -to gpio_1[4]
+set_location_assignment PIN_E15 -to gpio_1[5]
+set_location_assignment PIN_F15 -to gpio_1[6]
+set_location_assignment PIN_G16 -to gpio_1[7]
+set_location_assignment PIN_F12 -to gpio_1[8]
+set_location_assignment PIN_F13 -to gpio_1[9]
+set_location_assignment PIN_C14 -to gpio_1[10]
+set_location_assignment PIN_D14 -to gpio_1[11]
+set_location_assignment PIN_D15 -to gpio_1[12]
+set_location_assignment PIN_D16 -to gpio_1[13]
+set_location_assignment PIN_C17 -to gpio_1[14]
+set_location_assignment PIN_C18 -to gpio_1[15]
+set_location_assignment PIN_C19 -to gpio_1[16]
+set_location_assignment PIN_C20 -to gpio_1[17]
+set_location_assignment PIN_D19 -to gpio_1[18]
+set_location_assignment PIN_D20 -to gpio_1[19]
+set_location_assignment PIN_E20 -to gpio_1[20]
+set_location_assignment PIN_F20 -to gpio_1[21]
+set_location_assignment PIN_E19 -to gpio_1[22]
+set_location_assignment PIN_E18 -to gpio_1[23]
+set_location_assignment PIN_G20 -to gpio_1[24]
+set_location_assignment PIN_G18 -to gpio_1[25]
+set_location_assignment PIN_G17 -to gpio_1[26]
+set_location_assignment PIN_H17 -to gpio_1[27]
+set_location_assignment PIN_J15 -to gpio_1[28]
+set_location_assignment PIN_H18 -to gpio_1[29]
+set_location_assignment PIN_N22 -to gpio_1[30]
+set_location_assignment PIN_N21 -to gpio_1[31]
+set_location_assignment PIN_P15 -to gpio_1[32]
+set_location_assignment PIN_N15 -to gpio_1[33]
+set_location_assignment PIN_P17 -to gpio_1[34]
+set_location_assignment PIN_P18 -to gpio_1[35]
+set_location_assignment PIN_L22 -to sw[0]
+set_location_assignment PIN_L21 -to sw[1]
+set_location_assignment PIN_M22 -to sw[2]
+set_location_assignment PIN_V12 -to sw[3]
+set_location_assignment PIN_W12 -to sw[4]
+set_location_assignment PIN_U12 -to sw[5]
+set_location_assignment PIN_U11 -to sw[6]
+set_location_assignment PIN_M2 -to sw[7]
+set_location_assignment PIN_M1 -to sw[8]
+set_location_assignment PIN_L2 -to sw[9]
+set_location_assignment PIN_J2 -to s7_0[0]
+set_location_assignment PIN_J1 -to s7_0[1]
+set_location_assignment PIN_H2 -to s7_0[2]
+set_location_assignment PIN_H1 -to s7_0[3]
+set_location_assignment PIN_F2 -to s7_0[4]
+set_location_assignment PIN_F1 -to s7_0[5]
+set_location_assignment PIN_E2 -to s7_0[6]
+set_location_assignment PIN_E1 -to s7_1[0]
+set_location_assignment PIN_H6 -to s7_1[1]
+set_location_assignment PIN_H5 -to s7_1[2]
+set_location_assignment PIN_H4 -to s7_1[3]
+set_location_assignment PIN_G3 -to s7_1[4]
+set_location_assignment PIN_D2 -to s7_1[5]
+set_location_assignment PIN_D1 -to s7_1[6]
+set_location_assignment PIN_G5 -to s7_2[0]
+set_location_assignment PIN_G6 -to s7_2[1]
+set_location_assignment PIN_C2 -to s7_2[2]
+set_location_assignment PIN_C1 -to s7_2[3]
+set_location_assignment PIN_E3 -to s7_2[4]
+set_location_assignment PIN_E4 -to s7_2[5]
+set_location_assignment PIN_D3 -to s7_2[6]
+set_location_assignment PIN_F4 -to s7_3[0]
+set_location_assignment PIN_D5 -to s7_3[1]
+set_location_assignment PIN_D6 -to s7_3[2]
+set_location_assignment PIN_J4 -to s7_3[3]
+set_location_assignment PIN_L8 -to s7_3[4]
+set_location_assignment PIN_F3 -to s7_3[5]
+set_location_assignment PIN_D4 -to s7_3[6]
+set_location_assignment PIN_R22 -to key_n[0]
+set_location_assignment PIN_R21 -to key_n[1]
+set_location_assignment PIN_T22 -to key_n[2]
+set_location_assignment PIN_T21 -to key_n[3]
+set_location_assignment PIN_R20 -to ledr[0]
+set_location_assignment PIN_R19 -to ledr[1]
+set_location_assignment PIN_U19 -to ledr[2]
+set_location_assignment PIN_Y19 -to ledr[3]
+set_location_assignment PIN_T18 -to ledr[4]
+set_location_assignment PIN_V19 -to ledr[5]
+set_location_assignment PIN_Y18 -to ledr[6]
+set_location_assignment PIN_U18 -to ledr[7]
+set_location_assignment PIN_R18 -to ledr[8]
+set_location_assignment PIN_R17 -to ledr[9]
+set_location_assignment PIN_U22 -to ledg[0]
+set_location_assignment PIN_U21 -to ledg[1]
+set_location_assignment PIN_V22 -to ledg[2]
+set_location_assignment PIN_V21 -to ledg[3]
+set_location_assignment PIN_W22 -to ledg[4]
+set_location_assignment PIN_W21 -to ledg[5]
+set_location_assignment PIN_Y22 -to ledg[6]
+set_location_assignment PIN_Y21 -to ledg[7]
+set_location_assignment PIN_D12 -to clock_27[0]
+set_location_assignment PIN_E12 -to clock_27[1]
+set_location_assignment PIN_B12 -to clock_24[0]
+set_location_assignment PIN_A12 -to clock_24[1]
+set_location_assignment PIN_L1 -to clock_50
+set_location_assignment PIN_M21 -to ext_clock
+set_location_assignment PIN_H15 -to ps2_clk
+set_location_assignment PIN_J14 -to ps2_dat
+set_location_assignment PIN_F14 -to uart_rxd
+set_location_assignment PIN_G12 -to uart_txd
+set_location_assignment PIN_E8 -to tdi
+set_location_assignment PIN_D8 -to tcs
+set_location_assignment PIN_C7 -to tck
+set_location_assignment PIN_D7 -to tdo
+set_location_assignment PIN_D9 -to vga_r[0]
+set_location_assignment PIN_C9 -to vga_r[1]
+set_location_assignment PIN_A7 -to vga_r[2]
+set_location_assignment PIN_B7 -to vga_r[3]
+set_location_assignment PIN_B8 -to vga_g[0]
+set_location_assignment PIN_C10 -to vga_g[1]
+set_location_assignment PIN_B9 -to vga_g[2]
+set_location_assignment PIN_A8 -to vga_g[3]
+set_location_assignment PIN_A9 -to vga_b[0]
+set_location_assignment PIN_D11 -to vga_b[1]
+set_location_assignment PIN_A10 -to vga_b[2]
+set_location_assignment PIN_B10 -to vga_b[3]
+set_location_assignment PIN_A11 -to vga_hs
+set_location_assignment PIN_B11 -to vga_vs
+set_location_assignment PIN_A3 -to i2c_scl
+set_location_assignment PIN_B3 -to i2c_sda
+set_location_assignment PIN_A6 -to aud_adclrck
+set_location_assignment PIN_B6 -to aud_adcdat
+set_location_assignment PIN_A5 -to aud_daclrck
+set_location_assignment PIN_B5 -to aud_dacdat
+set_location_assignment PIN_B4 -to aud_xck
+set_location_assignment PIN_A4 -to aud_bclk
+set_location_assignment PIN_W4 -to dram_a[0]
+set_location_assignment PIN_W5 -to dram_a[1]
+set_location_assignment PIN_Y3 -to dram_a[2]
+set_location_assignment PIN_Y4 -to dram_a[3]
+set_location_assignment PIN_R6 -to dram_a[4]
+set_location_assignment PIN_R5 -to dram_a[5]
+set_location_assignment PIN_P6 -to dram_a[6]
+set_location_assignment PIN_P5 -to dram_a[7]
+set_location_assignment PIN_P3 -to dram_a[8]
+set_location_assignment PIN_N4 -to dram_a[9]
+set_location_assignment PIN_W3 -to dram_a[10]
+set_location_assignment PIN_N6 -to dram_a[11]
+set_location_assignment PIN_U3 -to dram_ba[0]
+set_location_assignment PIN_V4 -to dram_ba[1]
+set_location_assignment PIN_T3 -to dram_cas_n
+set_location_assignment PIN_N3 -to dram_cke
+set_location_assignment PIN_U4 -to dram_clk
+set_location_assignment PIN_T6 -to dram_cs_n
+set_location_assignment PIN_U1 -to dram_dq[0]
+set_location_assignment PIN_U2 -to dram_dq[1]
+set_location_assignment PIN_V1 -to dram_dq[2]
+set_location_assignment PIN_V2 -to dram_dq[3]
+set_location_assignment PIN_W1 -to dram_dq[4]
+set_location_assignment PIN_W2 -to dram_dq[5]
+set_location_assignment PIN_Y1 -to dram_dq[6]
+set_location_assignment PIN_Y2 -to dram_dq[7]
+set_location_assignment PIN_N1 -to dram_dq[8]
+set_location_assignment PIN_N2 -to dram_dq[9]
+set_location_assignment PIN_P1 -to dram_dq[10]
+set_location_assignment PIN_P2 -to dram_dq[11]
+set_location_assignment PIN_R1 -to dram_dq[12]
+set_location_assignment PIN_R2 -to dram_dq[13]
+set_location_assignment PIN_T1 -to dram_dq[14]
+set_location_assignment PIN_T2 -to dram_dq[15]
+set_location_assignment PIN_R7 -to dram_dqm[0]
+set_location_assignment PIN_T5 -to dram_ras_n
+set_location_assignment PIN_M5 -to dram_dqm[1]
+set_location_assignment PIN_R8 -to dram_we_n
+set_location_assignment PIN_AB20 -to fl_a[0]
+set_location_assignment PIN_AA14 -to fl_a[1]
+set_location_assignment PIN_Y16 -to fl_a[2]
+set_location_assignment PIN_R15 -to fl_a[3]
+set_location_assignment PIN_T15 -to fl_a[4]
+set_location_assignment PIN_U15 -to fl_a[5]
+set_location_assignment PIN_V15 -to fl_a[6]
+set_location_assignment PIN_W15 -to fl_a[7]
+set_location_assignment PIN_R14 -to fl_a[8]
+set_location_assignment PIN_Y13 -to fl_a[9]
+set_location_assignment PIN_R12 -to fl_a[10]
+set_location_assignment PIN_T12 -to fl_a[11]
+set_location_assignment PIN_AB14 -to fl_a[12]
+set_location_assignment PIN_AA13 -to fl_a[13]
+set_location_assignment PIN_AB13 -to fl_a[14]
+set_location_assignment PIN_AA12 -to fl_a[15]
+set_location_assignment PIN_AB12 -to fl_a[16]
+set_location_assignment PIN_AA20 -to fl_a[17]
+set_location_assignment PIN_U14 -to fl_a[18]
+set_location_assignment PIN_V14 -to fl_a[19]
+set_location_assignment PIN_U13 -to fl_a[20]
+set_location_assignment PIN_R13 -to fl_a[21]
+set_location_assignment PIN_AB16 -to fl_dq[0]
+set_location_assignment PIN_AA16 -to fl_dq[1]
+set_location_assignment PIN_AB17 -to fl_dq[2]
+set_location_assignment PIN_AA17 -to fl_dq[3]
+set_location_assignment PIN_AB18 -to fl_dq[4]
+set_location_assignment PIN_AA18 -to fl_dq[5]
+set_location_assignment PIN_AB19 -to fl_dq[6]
+set_location_assignment PIN_AA19 -to fl_dq[7]
+set_location_assignment PIN_AA15 -to fl_oe_n
+set_location_assignment PIN_W14 -to fl_rst_n
+set_location_assignment PIN_Y14 -to fl_we_n
+set_location_assignment PIN_AB15 -to fl_ce_n
+set_location_assignment PIN_AA3 -to sram_a[0]
+set_location_assignment PIN_AB3 -to sram_a[1]
+set_location_assignment PIN_AA4 -to sram_a[2]
+set_location_assignment PIN_AB4 -to sram_a[3]
+set_location_assignment PIN_AA5 -to sram_a[4]
+set_location_assignment PIN_AB10 -to sram_a[5]
+set_location_assignment PIN_AA11 -to sram_a[6]
+set_location_assignment PIN_AB11 -to sram_a[7]
+set_location_assignment PIN_V11 -to sram_a[8]
+set_location_assignment PIN_W11 -to sram_a[9]
+set_location_assignment PIN_R11 -to sram_a[10]
+set_location_assignment PIN_T11 -to sram_a[11]
+set_location_assignment PIN_Y10 -to sram_a[12]
+set_location_assignment PIN_U10 -to sram_a[13]
+set_location_assignment PIN_R10 -to sram_a[14]
+set_location_assignment PIN_T7 -to sram_a[15]
+set_location_assignment PIN_Y6 -to sram_a[16]
+set_location_assignment PIN_Y5 -to sram_a[17]
+set_location_assignment PIN_AB5 -to sram_ce_n
+set_location_assignment PIN_AA6 -to sram_dq[0]
+set_location_assignment PIN_AB6 -to sram_dq[1]
+set_location_assignment PIN_AA7 -to sram_dq[2]
+set_location_assignment PIN_AB7 -to sram_dq[3]
+set_location_assignment PIN_AA8 -to sram_dq[4]
+set_location_assignment PIN_AB8 -to sram_dq[5]
+set_location_assignment PIN_AA9 -to sram_dq[6]
+set_location_assignment PIN_AB9 -to sram_dq[7]
+set_location_assignment PIN_Y9 -to sram_dq[8]
+set_location_assignment PIN_W9 -to sram_dq[9]
+set_location_assignment PIN_V9 -to sram_dq[10]
+set_location_assignment PIN_U9 -to sram_dq[11]
+set_location_assignment PIN_R9 -to sram_dq[12]
+set_location_assignment PIN_W8 -to sram_dq[13]
+set_location_assignment PIN_V8 -to sram_dq[14]
+set_location_assignment PIN_U8 -to sram_dq[15]
+set_location_assignment PIN_Y7 -to sram_be_n[0]
+set_location_assignment PIN_T8 -to sram_oe_n
+set_location_assignment PIN_W7 -to sram_be_n[1]
+set_location_assignment PIN_AA10 -to sram_we_n
+set_location_assignment PIN_V20 -to sd_clk
+set_location_assignment PIN_Y20 -to sd_cmd
+set_location_assignment PIN_W20 -to sd_dat0
+set_location_assignment PIN_U20 -to sd_dat3
# Timing Assignments
# ==================
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
# Analysis & Synthesis Assignments
# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY "Cyclone II"
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name AUTO_ROM_RECOGNITION OFF
-set_global_assignment -name AUTO_RAM_RECOGNITION OFF
-set_global_assignment -name AUTO_RESOURCE_SHARING ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name AUTO_ROM_RECOGNITION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name TOP_LEVEL_ENTITY abc80
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
# Fitter Assignments
# ==================
-set_global_assignment -name DEVICE EP2C20F484C7
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS OFF
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS OFF
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# Timing Analysis Assignments
# ===========================
-set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
-set_global_assignment -name MAX_SCC_SIZE 50
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
+set_global_assignment -name MAX_SCC_SIZE 50
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
# Assembler Assignments
# =====================
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
-set_global_assignment -name GENERATE_HEX_FILE ON
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name GENERATE_HEX_FILE ON
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
# Design Assistant Assignments
# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT ON
-set_global_assignment -name HCPY_VREF_PINS OFF
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT ON
+set_global_assignment -name HCPY_VREF_PINS OFF
# Programmer Assignments
# ======================
-set_global_assignment -name GENERATE_JAM_FILE ON
+set_global_assignment -name GENERATE_JAM_FILE ON
# SignalTap II Assignments
# ========================
-set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
# ------------------
# start CLOCK(clkin)
@@ -462,7 +462,7 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design
# end EDA_TOOL_SETTINGS(eda_board_design)
# ---------------------------------------
@@ -472,7 +472,7 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_boar
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification
# end EDA_TOOL_SETTINGS(eda_formal_verification)
# ----------------------------------------------
@@ -482,7 +482,7 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_form
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace
# end EDA_TOOL_SETTINGS(eda_palace)
# ---------------------------------
@@ -492,7 +492,7 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_pala
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
@@ -502,7 +502,7 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simu
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis
# end EDA_TOOL_SETTINGS(eda_timing_analysis)
# ------------------------------------------
@@ -519,69 +519,70 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timi
# end ENTITY(abc80)
# -----------------
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
-set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clock_50
-set_instance_assignment -name CLOCK_SETTINGS clock_50 -to clock_50
-set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id clock_27
-set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[0]
-set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[1]
-set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id clock_24
-set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
-set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1]
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name USE_SIGNALTAP_FILE stp6.stp
-set_global_assignment -name VERILOG_FILE mega/fgcolrom.v
-set_global_assignment -name MIF_FILE data/fgcol.mif
-set_global_assignment -name VERILOG_FILE mega/pll2.v
-set_global_assignment -name VERILOG_FILE mega/serrxfifo.v
-set_global_assignment -name VERILOG_FILE i2c.v
-set_global_assignment -name MIF_FILE data/sddrom.mif
-set_global_assignment -name VERILOG_FILE mega/basic80.v
-set_global_assignment -name VERILOG_FILE mega/sddrom.v
-set_global_assignment -name VERILOG_FILE mega/sddram.v
-set_global_assignment -name VERILOG_FILE mega/ddio_out.v
-set_global_assignment -name VERILOG_FILE sddisk.v
-set_global_assignment -name VERILOG_FILE sound.v
-set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE t80/T80.vhd
-set_global_assignment -name VHDL_FILE t80/T80s.vhd
-set_global_assignment -name VHDL_FILE t80/T80se.vhd
-set_global_assignment -name MIF_FILE data/basic80.mif
-set_global_assignment -name MIF_FILE data/videoram.mif
-set_global_assignment -name MIF_FILE data/chargen.mif
-set_global_assignment -name MIF_FILE data/keyboard.mif
-set_global_assignment -name MIF_FILE data/mmu.mif
-set_global_assignment -name VERILOG_FILE mega/chargen.v
-set_global_assignment -name VERILOG_FILE mega/pll1.v
-set_global_assignment -name VERILOG_FILE mega/mmuram.v
-set_global_assignment -name VERILOG_FILE mega/videoram.v
-set_global_assignment -name VERILOG_FILE mega/kbdram.v
-set_global_assignment -name VERILOG_FILE t80pio/t80pio.v
-set_global_assignment -name VERILOG_FILE debounce.v
-set_global_assignment -name VERILOG_FILE display.v
-set_global_assignment -name VERILOG_FILE printer.v
-set_global_assignment -name VERILOG_FILE keyboard.v
-set_global_assignment -name VERILOG_FILE hexled.v
-set_global_assignment -name VERILOG_FILE hexascii.v
-set_global_assignment -name VERILOG_FILE abc80.v
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name SDC_FILE abc80.sdc
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name PARALLEL_SYNTHESIS ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clock_50
+set_instance_assignment -name CLOCK_SETTINGS clock_50 -to clock_50
+set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id clock_27
+set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[0]
+set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[1]
+set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id clock_24
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name USE_SIGNALTAP_FILE stp6.stp
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name PARALLEL_SYNTHESIS ON
+set_global_assignment -name VERILOG_FILE enc28j60.v
+set_global_assignment -name VERILOG_FILE mega/fgcolrom.v
+set_global_assignment -name MIF_FILE data/fgcol.mif
+set_global_assignment -name VERILOG_FILE mega/pll2.v
+set_global_assignment -name VERILOG_FILE mega/serrxfifo.v
+set_global_assignment -name VERILOG_FILE i2c.v
+set_global_assignment -name MIF_FILE data/sddrom.mif
+set_global_assignment -name VERILOG_FILE mega/basic80.v
+set_global_assignment -name VERILOG_FILE mega/sddrom.v
+set_global_assignment -name VERILOG_FILE mega/sddram.v
+set_global_assignment -name VERILOG_FILE mega/ddio_out.v
+set_global_assignment -name VERILOG_FILE sddisk.v
+set_global_assignment -name VERILOG_FILE sound.v
+set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE t80/T80.vhd
+set_global_assignment -name VHDL_FILE t80/T80s.vhd
+set_global_assignment -name VHDL_FILE t80/T80se.vhd
+set_global_assignment -name MIF_FILE data/basic80.mif
+set_global_assignment -name MIF_FILE data/videoram.mif
+set_global_assignment -name MIF_FILE data/chargen.mif
+set_global_assignment -name MIF_FILE data/keyboard.mif
+set_global_assignment -name MIF_FILE data/mmu.mif
+set_global_assignment -name VERILOG_FILE mega/chargen.v
+set_global_assignment -name VERILOG_FILE mega/pll1.v
+set_global_assignment -name VERILOG_FILE mega/mmuram.v
+set_global_assignment -name VERILOG_FILE mega/videoram.v
+set_global_assignment -name VERILOG_FILE mega/kbdram.v
+set_global_assignment -name VERILOG_FILE t80pio/t80pio.v
+set_global_assignment -name VERILOG_FILE debounce.v
+set_global_assignment -name VERILOG_FILE display.v
+set_global_assignment -name VERILOG_FILE printer.v
+set_global_assignment -name VERILOG_FILE keyboard.v
+set_global_assignment -name VERILOG_FILE hexled.v
+set_global_assignment -name VERILOG_FILE hexascii.v
+set_global_assignment -name VERILOG_FILE abc80.v
+set_global_assignment -name SDC_FILE abc80.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/abc80.v b/abc80.v
index 9edbef5..9791e23 100644
--- a/abc80.v
+++ b/abc80.v
@@ -732,14 +732,63 @@ module abc80 (
.select ( pr_select )
);
+ // ENC28J60 SPI Ethernet interface (using GPIO1)
+ wire [7:0] abc_eth_di;
+ wire eth_rdy;
+ wire eth_select;
+ wire eth_wol_n;
+ wire eth_irq_n;
+ wire eth_rst_n = rst_n;
+ wire eth_cs_n, eth_mosi, eth_sck, eth_miso;
+
+ enc28j60 eth_enc28j60 (
+ .rst_n ( rst_n ),
+ .clk ( cpu_clk ),
+
+ .eth_cs_n ( eth_cs_n ),
+ .eth_mosi ( eth_mosi ),
+ .eth_sck ( eth_sck ),
+ .eth_miso ( eth_miso ),
+
+ .abc_do ( cpu_do ),
+ .abc_di ( abc_eth_di ),
+ .abc_out_n ( abc_out_n[0] ),
+ .abc_cs_n ( abc_out_n[1] ),
+ .abc_c1_n ( abc_out_n[2] ),
+ .abc_c2_n ( abc_out_n[3] ),
+ .abc_c3_n ( abc_out_n[4] ),
+ .abc_inp_n ( abc_in_n[0] ),
+ .abc_status_n ( abc_in_n[1] ),
+ .abc_rst_n ( abc_in_n[7] ),
+ .abc_rdy ( eth_rdy ),
+
+ .select ( eth_select )
+ );
+
+ // The ENC28J60 module is attached to GPIO1 signals 26-33, corresponding
+ // to pins 29-38 (including power). This is dictated by VCC33 and GND
+ // on pins 29-30 corresponding to the MOD-ENC28J60 pins 1-2.
+ assign gpio_1[26] = 1'bz; // Optional connection to LEDA
+ assign gpio_1[27] = 1'bz;
+ assign eth_wol_n = gpio_1[27];
+ assign gpio_1[28] = 1'bz;
+ assign eth_irq_n = gpio_1[28];
+ assign gpio_1[29] = eth_rst_n;
+ assign gpio_1[30] = 1'bz;
+ assign eth_miso = gpio_1[30];
+ assign gpio_1[31] = eth_mosi;
+ assign gpio_1[32] = eth_sck;
+ assign gpio_1[33] = eth_cs_n;
+
// The terminology gets a bit funny there. abc_do means data from
// the ABC-bus to the main CPU.
- wire [7:0] abc_do = abc_sd_di & abc_pr_di;
+ wire [7:0] abc_do = abc_sd_di & abc_pr_di & abc_eth_di;
+ wire abc_wait_n = eth_rdy;
// Closest thing we get to a disk LED
assign std_led[0] = sd_active;
assign std_led[1] = sd_select;
- assign std_led[2] = 1'b0; // Do something interesting here...
+ assign std_led[2] = eth_select;
// Video width control INP 4 = 80, INP 3 = 40.
// Also allow KEY1 to flip it.
@@ -842,6 +891,7 @@ module abc80 (
.i2c_sda ( i2c_sda )
);
+
// ------------------------------------------------------------------------
// Internal non-ABC I/O registers (MMU, turbo, LED)
// ------------------------------------------------------------------------
@@ -993,7 +1043,7 @@ module abc80 (
assign cpu_int_n = pioa_int_n & piob_int_n;
assign cpu_nmi_n = ctr_20ms;
- wire cpu_wait_n = 1; // Nothing to wait for atm
+ wire cpu_wait_n = 1'b1; // See cpu_clk_en
wire cpu_clk_en;
always @(*)
@@ -1047,8 +1097,11 @@ module abc80 (
cpu_slow_mask <= 3'b111;
endcase // case( cpu_turbo )
end // always @ (posedge cpu_clk)
-
- assign cpu_clk_en = &(cpu_slow_ctr[2:0] | cpu_slow_mask) & flsh_wait_n;
+
+ // T80 seems to not handle WAIT# quite right so do this via
+ // the clock enable instead...
+ assign cpu_clk_en = &(cpu_slow_ctr[2:0] | cpu_slow_mask)
+ & flsh_wait_n & abc_wait_n;
assign std_led[7:5] = cpu_slow_mask;
diff --git a/enc28j60.v b/enc28j60.v
new file mode 100644
index 0000000..abfe5bd
--- /dev/null
+++ b/enc28j60.v
@@ -0,0 +1,216 @@
+// -----------------------------------------------------------------------
+//
+// Copyright 2011 H. Peter Anvin - All Rights Reserved
+//
+// Permission is hereby granted, free of charge, to any person
+// obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without
+// restriction, including without limitation the rights to use,
+// copy, modify, merge, publish, distribute, sublicense, and/or
+// sell copies of the Software, and to permit persons to whom
+// the Software is furnished to do so, subject to the following
+// conditions:
+//
+// The above copyright notice and this permission notice shall
+// be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+// OTHER DEALINGS IN THE SOFTWARE.
+//
+// -----------------------------------------------------------------------
+
+//
+// enc28j60.v
+//
+// Driver for the Microchip ENC28J60 SPI Ethernet controller
+//
+
+module enc28j60 (
+ input rst_n, // Global reset
+ input clk, // CPU clk (25 MHz)
+
+ output eth_cs_n, // SPI CS#
+ output eth_mosi, // SPI MOSI (SI)
+ output eth_sck, // SPI SCLK
+ input eth_miso, // SPI MISO (SO)
+
+ input [7:0] abc_do, // ABC-bus data out (CPU->controller)
+ output [7:0] abc_di, // ABC-bus data in (controller->CPU)
+ input abc_out_n, // ABC-bus data out select (OUT 0)
+ input abc_cs_n, // ABC-bus Card Select
+ input abc_c1_n, // ABC-bus Command 1 (OUT 2)
+ input abc_c2_n, // ABC-bus Command 2 (OUT 3)
+ input abc_c3_n, // ABC-bus Command 3 (OUT 4)
+ input abc_c4_n, // ABC-bus Command 4 (OUT 5)
+ input abc_inp_n, // ABC-bus data in select (IN 0)
+ input abc_status_n, // ABC-bus status (IN 1)
+ input abc_rst_n, // ABC-bus reset (IN 7)
+ output abc_rdy, // ABC-bus RDY/WAIT#
+
+ output select // Selected LED
+ );
+
+ // ------------------------------------------------------------------------
+ //
+ // ENC28J60 supports up to 20 MHz on the SPI bus, but we run it at
+ // CPU clk / 2 (12.5 MHz). However, all fixed timings are such that
+ // running this module up to 40 MHz for a 20 MHz output should work.
+ //
+ // Write commands:
+ // OUT - send data byte, leave CS# asserted
+ // C1 - send data byte, deassert CS#
+ // C2 - send FF byte, leave CS# asserted
+ // C3 - reset
+ // Read commands:
+ // INP - read input shift register, output FF, leave CS# asserted
+ // STATUS - read input shift register, output FF, deassert CS#
+ //
+ // If CS# is already deasserted, input simply returns the shift
+ // register contents.
+ // ------------------------------------------------------------------------
+
+ parameter selectcode = 6'd9;
+ reg selected;
+ assign select = selected;
+
+ reg [7:0] spi_shr_out;
+ reg [7:0] spi_shr_in;
+ reg [3:0] spi_ctr; // Bit or cycle counter
+
+ reg spi_cs_n;
+ reg spi_clk;
+
+ reg spi_active;
+ reg spi_cmd_ok;
+ reg spi_finish;
+
+ assign eth_cs_n = spi_cs_n;
+ assign eth_sck = spi_clk;
+ assign eth_mosi = spi_shr_out[7];
+
+ wire abc_active =
+ selected & (~abc_out_n | ~abc_c1_n | ~abc_c2_n |
+ ~abc_inp_n | ~abc_status_n);
+
+ assign abc_rdy = ~(abc_active & ~spi_cmd_ok);
+
+ reg [1:0] spi_state;
+ parameter st_idle = 2'b00;
+ parameter st_data = 2'b01;
+ parameter st_cshold0 = 2'b10;
+ parameter st_cshold1 = 2'b11;
+
+ wire [7:0] cpu_to_spi_data = (~abc_out_n | ~abc_c1_n) ? abc_do : 8'hff;
+
+ always @(posedge clk)
+ if (~rst_n)
+ selected <= 1'b0;
+ else
+ begin
+ if (~abc_rst_n)
+ selected <= 1'b0;
+ else if (~abc_cs_n)
+ selected <= abc_do[5:0] == selectcode;
+ end
+
+ always @(posedge clk)
+ if (~rst_n | ~abc_rst_n | (selected & ~abc_c3_n))
+ begin
+ spi_state <= st_idle;
+ spi_cs_n <= 1'b1;
+ spi_clk <= 1'b0;
+ spi_shr_out <= 8'hff;
+ spi_shr_in <= 8'hff;
+ spi_ctr <= 4'd0;
+ spi_finish <= 1'bx;
+ spi_cmd_ok <= 1'b0;
+ end
+ else
+ begin
+ spi_cmd_ok <= spi_cmd_ok & abc_active;
+
+ case (spi_state)
+ st_idle:
+ begin
+ spi_cmd_ok <= 1'b1;
+
+ if (abc_active)
+ begin
+ spi_cs_n <= 1'b0;
+ spi_state <= st_data;
+ spi_shr_out <= cpu_to_spi_data;
+ spi_ctr <= 4'd7;
+ spi_finish <= ~abc_c1_n | ~abc_status_n;
+ end
+ end // case: spi_idle
+
+ st_data:
+ begin
+ spi_cs_n <= 1'b0;
+ spi_clk <= ~spi_clk;
+
+ if (spi_clk)
+ begin
+ spi_shr_out <= { spi_shr_out[6:0], 1'b1 };
+ spi_ctr <= spi_ctr - 1'b1;
+
+ if (~|spi_ctr)
+ begin
+ if (spi_finish)
+ begin
+ spi_ctr <= 4'd8;
+ spi_state <= st_cshold0;
+ end
+ else if (abc_active)
+ begin
+ spi_shr_out <= cpu_to_spi_data;
+ spi_ctr <= 4'd7;
+ spi_finish <= ~abc_c1_n | ~abc_status_n;
+ spi_cmd_ok <= 1'b1;
+ end
+ else
+ begin
+ spi_state <= st_idle;
+ spi_cmd_ok <= 1'b1;
+ end
+ end // if (~|spi_ctr)
+ end // if (spi_clk)
+ else
+ begin
+ spi_shr_in <= { spi_shr_in[6:0], eth_miso };
+ end // else: !if(spi_clk)
+ end // case: spi_data
+
+ st_cshold0:
+ begin
+ spi_ctr <= spi_ctr - 1'b1;
+
+ if (~|spi_ctr)
+ begin
+ spi_cs_n <= 1'b1;
+ spi_state <= st_cshold1;
+ end
+ end
+
+ st_cshold1:
+ begin
+ spi_state <= st_idle;
+ spi_cmd_ok <= 1'b1;
+ end
+
+ endcase
+ end // else: !if(~rst_n)
+
+ //
+ // Output data
+ //
+ assign abc_di = (selected & (~abc_inp_n | ~abc_status_n))
+ ? spi_shr_in : 8'hff;
+
+endmodule // enc28j60