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authorH. Peter Anvin <hpa@trantor.hos.anvin.org>2010-09-17 21:44:16 -0700
committerH. Peter Anvin <hpa@trantor.hos.anvin.org>2010-09-17 21:46:27 -0700
commit7318780bb586bc8ea3f5cc6d55c996cae84a8cc4 (patch)
treef1d1572f710492c40a1235622ec50745f6a2ec3b
parent640da33dd594681c9c12276d2e031542960a6ec6 (diff)
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abc80.v: prepare for multiplexing SRAM with graphics; fix PLLs
Prepare for multiplexing the SRAM with a graphics unit by only activating it when the CPU really need it. The CPU will never use it for two adjacent ticks of the CPU clock. Fix the reset time of the PLLs to something in legal range. Add an 18.75 MHz clock to be used as a pixel clock for 480x480 (480x240 dual scan) VGA-compatible mode.
-rw-r--r--abc80.v43
-rw-r--r--mega/pll1.v76
-rw-r--r--mega/pll2.v29
3 files changed, 97 insertions, 51 deletions
diff --git a/abc80.v b/abc80.v
index 3422a13..21c97aa 100644
--- a/abc80.v
+++ b/abc80.v
@@ -1,6 +1,6 @@
// -----------------------------------------------------------------------
//
-// Copyright 2003-2008 H. Peter Anvin - All Rights Reserved
+// Copyright 2003-2010 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -95,10 +95,11 @@ module abc80 (
// PLLs and clock distribution
// ------------------------------------------------------------------------
- wire cpu_clk; // 25 MHz
- wire video_clk; // 25 MHz = screen pixel rate
- wire fast_clk; // 100 MHz
- wire audio_clk; // 16 MHz = I2S master clock
+ wire cpu_clk; // 25 MHz
+ wire video_clk; // 25 MHz = screen pixel rate
+ wire xvideo_clk; // 18.75 MHz = compatible screen pixel rate
+ wire fast_clk; // 100 MHz
+ wire audio_clk; // 16 MHz = I2S master clock
wire pll1_locked;
wire pll2_locked;
@@ -108,6 +109,7 @@ module abc80 (
.inclk0 ( clock_50 ), // 50 MHz input clock
.c0 ( fast_clk ), // x2/1 = 100 MHz
.c1 ( cpu_clk ), // x1/2 = 25 MHz
+ .c2 ( xvideo_clk ), // x3/8 = 18.75 MHz
.locked ( pll1_locked )
);
@@ -309,6 +311,12 @@ module abc80 (
// ------------------------------------------------------------------------
// External SRAM
+ //
+ // The SRAM is very fast (10 ns) but is a asychronous part, so we
+ // generate the SRAM cycles from the fast_clk to make sure things happen
+ // in the right order. The SRAM is only active when actually addressed
+ // by the CPU; the intent is to be able to multiplex it with a graphics
+ // unit in the future.
// ------------------------------------------------------------------------
wire [7:0] sram_do; // Data out from sram
@@ -316,11 +324,13 @@ module abc80 (
wire sram_we_w;
reg sram_we_q1;
reg sram_we_q2;
+
+ // Are we actually accessed by the CPU?
+ wire sram_cpu = msel[0] & cpu_clk_en;
- assign sram_ce_n = ~msel[0];
-
- assign sram_oe_w = msel[0] & ~cpu_rd_n;
- assign sram_we_w = msel[0] & ~cpu_wr_n;
+ assign sram_ce_n = ~sram_cpu;
+ assign sram_oe_w = sram_cpu & ~cpu_rd_n;
+ assign sram_we_w = sram_cpu & ~cpu_wr_n;
always @(negedge rst_n or posedge fast_clk)
if ( ~rst_n )
@@ -336,9 +346,14 @@ module abc80 (
sram_we_q2 <= sram_we_q1;
end // else: !if( ~rst_n )
- // Driving output pins...
- assign sram_a = mmu_a[18:1];
- assign sram_be_n = mmu_a[0] ? ~2'b10 : ~2'b01;
+ // The address to drive onto the bus. This is a placeholder for
+ // multiplexing with the Fine Graphics unit.
+ wire [18:0] sram_addr = sram_cpu ? mmu_a[18:0] : 19'h7ffff;
+
+ // Driving output pins.
+
+ assign sram_a = sram_addr[18:1];
+ assign sram_be_n = sram_addr[0] ? ~2'b10 : ~2'b01;
assign sram_oe_n = ~sram_oe_w;
assign sram_we_n = ~(sram_we_w & ~sram_we_q2);
@@ -346,7 +361,7 @@ module abc80 (
assign sram_dq = sram_we_w ? { cpu_do, cpu_do } : 16'bz;
// SRAM Input side MUX
- assign sram_do = mmu_a[0] ? sram_dq[15:8] : sram_dq[7:0];
+ assign sram_do = sram_addr[0] ? sram_dq[15:8] : sram_dq[7:0];
// ------------------------------------------------------------------------
// External flash ROM
@@ -441,7 +456,7 @@ module abc80 (
always @(posedge fast_clk)
begin
- if ( ~cpu_mreq_n )
+ if ( ~cpu_mreq_n & cpu_rfsh_n )
case ( mmu_devsel )
3'h0: msel <= 8'b00000001;
3'h1: msel <= 8'b00000010;
diff --git a/mega/pll1.v b/mega/pll1.v
index 1fe945f..b21c3d0 100644
--- a/mega/pll1.v
+++ b/mega/pll1.v
@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 8.1 Build 163 10/28/2008 SJ Web Edition
+// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2008 Altera Corporation
+//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -40,28 +40,32 @@ module pll1 (
inclk0,
c0,
c1,
+ c2,
locked);
input inclk0;
output c0;
output c1;
+ output c2;
output locked;
wire [5:0] sub_wire0;
- wire sub_wire3;
- wire [0:0] sub_wire6 = 1'h0;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
- wire locked = sub_wire3;
- wire sub_wire4 = inclk0;
- wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+ wire c2 = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
- .inclk (sub_wire5),
+ .inclk (sub_wire6),
.clk (sub_wire0),
- .locked (sub_wire3),
+ .locked (sub_wire4),
.activeclock (),
.areset (1'b0),
.clkbad (),
@@ -103,8 +107,12 @@ module pll1 (
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 8,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 3,
+ altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
- altpll_component.gate_lock_counter = 16,
+ altpll_component.gate_lock_counter = 8192,
altpll_component.gate_lock_signal = "YES",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
@@ -138,7 +146,7 @@ module pll1 (
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
- altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
@@ -179,14 +187,19 @@ endmodule
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "8"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "18.750000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "16"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "8192"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
@@ -202,25 +215,33 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "18.75000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -245,13 +266,16 @@ endmodule
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
@@ -263,8 +287,12 @@ endmodule
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "8"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "16"
+// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "8192"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
@@ -298,7 +326,7 @@ endmodule
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -317,20 +345,22 @@ endmodule
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll2.v b/mega/pll2.v
index d75e43f..d4a55d7 100644
--- a/mega/pll2.v
+++ b/mega/pll2.v
@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
-// 8.1 Build 163 10/28/2008 SJ Web Edition
+// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2008 Altera Corporation
+//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -96,7 +96,7 @@ module pll2 (
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
- altpll_component.gate_lock_counter = 16,
+ altpll_component.gate_lock_counter = 4096,
altpll_component.gate_lock_signal = "YES",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone II",
@@ -172,12 +172,13 @@ endmodule
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "16"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "4096"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
@@ -240,7 +241,7 @@ endmodule
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "16"
+// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "4096"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
@@ -298,14 +299,14 @@ endmodule
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_waveforms.html TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_wave*.jpg FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON