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authorH. Peter Anvin <hpa@trantor.hos.anvin.org>2009-01-22 22:43:43 -0800
committerH. Peter Anvin <hpa@trantor.hos.anvin.org>2009-01-22 22:43:43 -0800
commit640da33dd594681c9c12276d2e031542960a6ec6 (patch)
tree7046068ae1ddda0547f761335432b125c1d5a97d
parent898d08b7cfcd7bc9a602b47ce5564b697087811e (diff)
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Remove obsolete cfdisk.v
Remove obsolete file cfdisk.v, from the NIOS II board which had a CompactFlash slot instead of SD.
-rw-r--r--cfdisk.v441
1 files changed, 0 insertions, 441 deletions
diff --git a/cfdisk.v b/cfdisk.v
deleted file mode 100644
index c8274bf..0000000
--- a/cfdisk.v
+++ /dev/null
@@ -1,441 +0,0 @@
-// $Id$
-//
-// CompactFlash controller for ABC80
-// Designed to be compatible with the standard ABC-DOS controllers
-//
-// Note: in order for this to not require internal tristate buffers in
-// the FPGA, the data bus is split, and the "input" bus will be driven
-// to all FF when the card is not selected, so all inputs can be ANDed.
-
-//
-// The I/O port range is decoded as follows:
-//
-// A7 - don't issue NMI# for this I/O
-// A6 - unused
-// A5 - CF auxilliary status
-// A4 - DMA engine
-// A3 - Addressing CF card
-// A2..A0 - register select on CompactFlash card/DMA engine
-
-module cfcontroller(
- reset_n, // Global reset
- clk, // CPU clk
-
- cf_power, // CompactFlash power enable
- cf_a, // CompactFlash address bus
- cf_d, // CompactFlash data bus
- cf_rdy, // CompactFlash RDY
- cf_wait_n, // CompactFlash WAIT#
- cf_ce1_n, // CompactFlash CE1#
- cf_ce2_n, // CompactFlash CE2#
- cf_oe_n, // CompactFlash OE#
- cf_we_n, // CompactFlash WE#
- cf_reg_n, // CompactFlash REG#
- cf_iord_n, // CompactFlash IORD#
- cf_iowr_n, // CompactFlash IOWR#
- cf_cd1_n, // CompactFlash card detect
-
- abc_do, // ABC-bus data out (CPU->controller)
- abc_di, // ABC-bus data in (controller->CPU)
- abc_out_n, // ABC-bus data out select (OUT 0)
- abc_cs_n, // ABC-bus Card Select
- abc_c1_n, // ABC-bus Command 1 (OUT 2)
- abc_c2_n, // ABC-bus Command 2 (OUT 3)
- abc_c3_n, // ABC-bus Command 3 (OUT 4)
- abc_c4_n, // ABC-bus Command 4 (OUT 5)
- abc_inp_n, // ABC-bus data in select (IN 0)
- abc_status_n, // ABC-bus status (IN 1)
- abc_rst_n, // ABC-bus reset (IN 7)
-
- select, // Selected?
- active // Active? (Mirrors cf_ce1_n but not tristate)
- );
-
- input reset_n;
- input clk;
-
- output cf_power;
- output [10:0] cf_a;
- inout [15:0] cf_d;
- input cf_rdy;
- input cf_wait_n;
- output cf_ce1_n;
- output cf_ce2_n;
- output cf_oe_n;
- output cf_we_n;
- output cf_reg_n;
- output cf_iord_n;
- output cf_iowr_n;
- input cf_cd1_n;
-
- input [7:0] abc_do;
- output [7:0] abc_di;
- input abc_out_n;
- input abc_cs_n;
- input abc_c1_n;
- input abc_c2_n;
- input abc_c3_n;
- input abc_c4_n;
- input abc_inp_n;
- input abc_status_n;
- input abc_rst_n;
-
- output select;
- output active;
-
- // Forward declaration
- wire cf_cpu_wait_n; // If we should raise WAIT# to CPU
-
- // Which select code this device uses... select code 36 decimal is used
- // for hard disk controllers
- parameter selectcode = 6'd36;
- reg selected;
-
- assign select = selected; // For external LED, might need hysteresis
-
- // ------------------------------------------------------------------------
- // Reset and select
- // Note: for glitch prevention reasons, treat RST# and C3# as synchronous
- // resets only.
- // ------------------------------------------------------------------------
- reg ireset;
-
- always @(negedge reset_n or posedge clk)
- begin
- if ( ~reset_n )
- begin
- ireset <= 1;
- selected <= 0;
- end
- else // clock
- begin
- ireset <= 0;
- if ( ~abc_rst_n )
- begin
- ireset <= 1;
- selected <= 0;
- end
- else
- begin
- if ( selected & ~abc_c3_n )
- ireset <= 1;
-
- if ( ~abc_cs_n )
- selected <= (abc_do[5:0] == selectcode);
- end
- end
- end
-
- // ------------------------------------------------------------------------
- // Controller CPU
- // ------------------------------------------------------------------------
-
- wire cpu_m1_n;
- wire cpu_iorq_n;
- wire cpu_mreq_n;
- wire cpu_rd_n;
- wire cpu_wr_n;
- wire [15:0] cpu_a;
- wire [7:0] cpu_di;
- wire [7:0] cpu_do;
- reg cpu_int_n;
- reg cpu_nmi_n;
-
- T80se cf_cpu (
- .clk_n ( clk ),
- .reset_n ( ~ireset ),
- .clken ( cf_cpu_wait_n ),
- .wait_n ( 1 ),
- .int_n ( cpu_int_n ),
- .nmi_n ( cpu_nmi_n ),
- .busrq_n ( 1 ),
- .m1_n ( cpu_m1_n ),
- .mreq_n ( cpu_mreq_n ),
- .iorq_n ( cpu_iorq_n ),
- .rd_n ( cpu_rd_n ),
- .wr_n ( cpu_wr_n ),
- .a ( cpu_a ),
- .di ( cpu_di ),
- .do ( cpu_do )
- );
-
- // Issue NMI if CD1# goes high -> card missing
- // The logic is that we only take NMI# when IORQ# is asserted;
- // this allows for "safe areas" where NMI# isn't taken, but
- // guarantees we're not stuck in a loop waiting for the CF card.
- // A7 is used for I/O accesses from within the NMI handler itself.
- wire cf_present = ~cf_cd1_n;
-
- always @(posedge ireset or posedge clk)
- begin
- if ( ireset )
- cpu_nmi_n <= 1;
- else
- cpu_nmi_n <= ( ~cf_present & ~cpu_iorq_n & ~cpu_a[7] );
- end
-
- always @(posedge ireset or posedge clk)
- begin
- if ( ireset )
- cpu_int_n <= 1;
- else
- if ( selected & ~abc_c1_n )
- cpu_int_n <= 0;
- else if ( ~cpu_m1_n & ~cpu_iorq_n ) // INTAK
- cpu_int_n <= 1;
- end // always @ (posedge ireset or posedge clk)
-
- // ------------------------------------------------------------------------
- // Memory -- second port used for "DMA" to the main CPU
- // ------------------------------------------------------------------------
-
- wire [7:0] memrd; // Read data to controller CPU
- reg write_flag; // DMA if we should write data to controller RAM
- reg read_flag; // DMA if we just read data from controller RAM
- reg [7:0] cpudata_di; // DMA data to controller memory
- wire [7:0] cpudata_do; // DMA data from controller memory
- reg [10:0] cpudata_addr; // DMA target address
-
- cfram cfram_inst (
- .clock ( ~clk ),
- .address_a ( cpu_a[10:0] ),
- .data_a ( cpu_do ),
- .wren_a ( ~cpu_mreq_n & ~cpu_wr_n ),
- .q_a ( memrd ),
- .address_b ( cpudata_addr ),
- .data_b ( cpudata_di ),
- .wren_b ( write_flag ),
- .q_b ( cpudata_do )
- );
-
- // ------------------------------------------------------------------------
- // Main CPU interface
- // ------------------------------------------------------------------------
-
- reg [8:0] cpudata_ctr; // Bytes left to DMA
- reg cpudata_dir; // 0 = out, 1 = inp
- reg [7:0] aux_status; // Auxilliary status
- reg [7:0] main_status; // Primary status
- wire [7:0] dma_status; // Controller CPU query DMA engine status
- wire dma_stat_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[4]; // IN 0x10
- wire dma_active = (cpudata_ctr != 0);
-
- reg [7:0] abc_di;
- always @(*)
- begin
- if ( selected & ~abc_inp_n )
- if ( dma_active && cpudata_dir == 1 )
- abc_di = cpudata_do;
- else
- abc_di = aux_status;
- else if ( selected & ~abc_status_n )
- abc_di = main_status;
- else
- abc_di = 8'hFF;
- end // always @ (*)
-
- always @(posedge ireset or posedge clk)
- begin
- if ( ireset )
- begin
- cpudata_addr <= ~11'b0;
- cpudata_ctr <= 0;
- cpudata_dir <= 0;
- write_flag <= 0;
- read_flag <= 0;
- main_status <= 0;
- aux_status <= 0;
- end
- else
- begin
- write_flag <= 0;
- read_flag <= 0;
-
- if ( selected & ~abc_out_n )
- begin
- if ( dma_active && cpudata_dir == 0 )
- begin
- cpudata_di <= abc_do;
- write_flag <= 1;
- end
- end // if ( selected & ~abc_out_n )
-
- if ( selected & ~abc_inp_n )
- begin
- if ( dma_active && cpudata_dir == 1 )
- begin
- // abc_di is generated above
- read_flag <= 1;
- end
- end // if ( selected & ~abc_inp_n )
-
- if ( (write_flag & ~(selected & ~abc_out_n)) |
- (read_flag & ~(selected & ~abc_inp_n)) )
- begin
- // We just completed an OUT or INP cycle
- cpudata_addr <= cpudata_addr + 1;
- cpudata_ctr <= cpudata_ctr - 1;
- // Turn off START COMMAND
- main_status[7] <= 0;
- // If this was the last byte, turn on busy
- if ( cpudata_ctr == 1 )
- main_status[0] <= 0;
- end
-
- // Set counters or status based on commands from controller CPU
- if ( ~cpu_iorq_n & cpu_m1_n & ~cpu_wr_n & cpu_a[4] )
- begin
- casex ( cpu_a[2:0] )
- 3'b0x0: // OUT 0x10
- main_status <= cpu_do;
- 3'b0x1: // OUT 0x11
- aux_status <= cpu_do;
- 3'b100: // OUT 0x14
- cpudata_addr[7:0] <= cpu_do;
- 3'b101: // OUT 0x15
- begin
- cpudata_addr[10:8] <= cpu_do[2:0];
- cpudata_dir <= cpu_do[7];
- end
- 3'b11x: // OUT 0x16-0x17
- cpudata_ctr <= { cpu_a[0], cpu_do };
- endcase // casex( cpu_a[2:0] )
- end
-
- end // else: !if( ireset )
- end // always @ (posedge ireset or posedge clk)
-
- assign dma_status = { 6'b0, cpudata_dir, dma_active };
-
- // ------------------------------------------------------------------------
- // CompactFlash interface
- // NOTE: The CF interface is glitch-sensitive; be careful to avoid
- // both positive and negative glitches; hence 1's-hot state machine
- // and avoidance of logical combinations of states.
- // ------------------------------------------------------------------------
-
-`define CF_IDLE 0 // CF card is idle
-`define CF_CE 1 // CE# is asserted
-`define CF_WOE0 2 // WE#/OE# is asserted
-`define CF_WOE1 3 // WE#/OE# is asserted
-`define CF_WOE2 4 // WE#/OE# is asserted
-`define CF_HOLD 5 // CE# hold cycle
-
- reg [5:0] cf_state;
- wire [5:0] cf_adv;
- wire cf_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[3];
- wire cf_act = cf_sel & ~(cpu_rd_n & cpu_wr_n);
- wire cf_aux_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[5]; // IN 0x20 = CF auxilliary status
- reg [2:0] cf_a_q;
- reg [7:0] cf_wd_q;
- reg [7:0] cf_rd_q;
- reg cf_write_q; // True if write cycle
- reg cf_bsy_latch; // Has RDY/BSY# been 0 since the last write?
- reg cf_rdy_q; // Synchronized version of RDY/BSY#
- wire [7:0] cf_do; // Data out to CPU
- reg cf_we_q;
- reg cf_oe_q;
- reg cf_wait_q;
-
- // Leave power always enabled
- assign cf_power = 1;
-
- // Only 3 address bits provided
- assign cf_a[10:3] = cf_present ? 8'h00 : 8'bz;
- assign cf_a[2:0] = cf_present ? cf_a_q : 3'bz;
-
- assign cf_ce2_n = cf_present ? 1'b1 : 1'bz; // 8-bit access
- assign cf_reg_n = cf_present ? 1'b1 : 1'bz; // Common memory access mode
-
- assign cf_iord_n = cf_present ? 1'b1 : 1'bz; // Common memory access mode
- assign cf_iowr_n = cf_present ? 1'b1 : 1'bz; // Common memory access mode
-
- assign cf_d[7:0] = (cf_present & cf_write_q) ? cf_wd_q : 8'bz;
- assign cf_d[15:8] = 8'bz;
- assign cf_do = cf_rd_q;
-
- assign active = ~cf_state[`CF_IDLE];
- assign cf_ce1_n = cf_present ? ~active : 1'bz;
- assign cf_we_n = cf_present ? cf_we_q : 1'bz;
- assign cf_oe_n = cf_present ? cf_oe_q : 1'bz;
-
- assign cf_cpu_wait_n = ~(cf_act & ~cf_state[`CF_HOLD]);
-
- assign cf_adv[`CF_IDLE] = cf_state[`CF_IDLE] & cf_act;
- assign cf_adv[`CF_CE] = cf_state[`CF_CE];
- assign cf_adv[`CF_WOE0] = cf_state[`CF_WOE0] & cf_wait_q;
- assign cf_adv[`CF_WOE1] = cf_state[`CF_WOE1] & cf_wait_q;
- assign cf_adv[`CF_WOE2] = cf_state[`CF_WOE2] & cf_wait_q;
- assign cf_adv[`CF_HOLD] = cf_state[`CF_HOLD] & ~cf_act;
-
- always @(posedge ireset or posedge clk)
- begin
- if ( ireset )
- begin
- cf_state <= 1 << `CF_IDLE;
- cf_we_q <= 1;
- cf_oe_q <= 1;
- cf_wait_q <= 1;
- cf_write_q <= 0;
- end
- else
- begin
- cf_wait_q <= cf_wait_n;
-
- if ( |cf_adv )
- begin
- cf_state <= { cf_state[4:0], cf_state[5] }; // Rotate left
- end
-
- if ( cf_adv[`CF_IDLE] )
- begin
- cf_a_q <= cpu_a[2:0];
- cf_wd_q <= cpu_do;
- cf_write_q <= ~cpu_wr_n;
- end
-
- if ( cf_adv[`CF_CE] )
- begin
- cf_oe_q <= cf_write_q;
- cf_we_q <= ~cf_write_q;
- end
-
- if ( cf_adv[`CF_WOE2] )
- begin
- cf_rd_q <= cf_d[7:0];
- cf_oe_q <= 1'b1;
- cf_we_q <= 1'b1;
- end
-
- if ( cf_adv[`CF_HOLD] )
- cf_write_q <= 0;
- end
- end
-
- always @(negedge cf_rdy or posedge clk)
- begin
- if ( ~cf_rdy )
- cf_bsy_latch <= 1;
- else
- if ( ireset | (cf_state[`CF_WOE0] & cf_write_q) )
- cf_bsy_latch <= 0;
- end
-
- always @(posedge clk)
- cf_rdy_q <= cf_rdy;
-
- wire [7:0] cf_aux_status = { 5'b0, cf_present, cf_bsy_latch, cf_rdy_q };
-
- // ------------------------------------------------------------------------
- // Controller CPU data select
- // ------------------------------------------------------------------------
-
- assign cpu_di =
- cpu_rd_n ? 8'hFF :
- ~cpu_mreq_n ? memrd :
- cf_sel ? cf_do :
- cf_aux_sel ? cf_aux_status :
- dma_stat_sel ? dma_status :
- 8'hFF; // Default read input
-
-endmodule // cfcontroller