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authorhpa <hpa@trantor.hos.anvin.org>2008-12-20 12:18:47 -0800
committerhpa <hpa@trantor.hos.anvin.org>2008-12-20 12:18:47 -0800
commit61268167fb3b04aa18e02259d99dae8dfc7684f1 (patch)
treed473bd33da1e849dd6fb6efa4bd6f140d95c0cba
parent28b0de5001e4f7d085c856e89933eab660b16025 (diff)
downloadabc80-61268167fb3b04aa18e02259d99dae8dfc7684f1.tar.gz
abc80-61268167fb3b04aa18e02259d99dae8dfc7684f1.tar.xz
abc80-61268167fb3b04aa18e02259d99dae8dfc7684f1.zip
Initial port to DE1 card
Enough of a port to DE1 for it to pass synthesis, but it doesn't fit in the design due to the high consumption of memories. This needs to be addressed by using the external flash.
-rw-r--r--[-rwxr-xr-x]abc80.qpf58
-rw-r--r--[-rwxr-xr-x]abc80.qsf1214
-rwxr-xr-x[-rw-r--r--]abc80.v509
-rw-r--r--data/Makefile37
-rw-r--r--data/sdram.asm (renamed from data/cfram.asm)2
-rwxr-xr-xmega/cfram.bsf153
-rw-r--r--mega/mmuram.bsf334
-rw-r--r--mega/mmuram.cmp35
-rw-r--r--mega/mmuram.inc36
-rw-r--r--mega/mmuram.v437
-rw-r--r--mega/mmuram_bb.v216
-rw-r--r--mega/mmuram_inst.v22
-rw-r--r--mega/pll1.bsf197
-rw-r--r--mega/pll1.cmp30
-rw-r--r--mega/pll1.inc31
-rw-r--r--mega/pll1.v611
-rw-r--r--mega/pll1_bb.v427
-rw-r--r--mega/pll1_inst.v6
-rw-r--r--[-rwxr-xr-x]mega/printerrom.bsf142
-rw-r--r--[-rwxr-xr-x]mega/printerrom.v352
-rw-r--r--[-rwxr-xr-x]mega/printerrom_bb.v264
-rw-r--r--[-rwxr-xr-x]mega/sdram.v (renamed from mega/cfram.v)26
-rwxr-xr-xsddisk.v471
-rw-r--r--sound.v3
-rw-r--r--tools/z80asm/Makefile32
-rwxr-xr-x[-rw-r--r--]upload.sh0
26 files changed, 2961 insertions, 2684 deletions
diff --git a/abc80.qpf b/abc80.qpf
index 707764d..ce0fce0 100755..100644
--- a/abc80.qpf
+++ b/abc80.qpf
@@ -1,29 +1,29 @@
-# Copyright (C) 1991-2004 Altera Corporation
-# Any megafunction design, and related netlist (encrypted or decrypted),
-# support information, device programming or simulation file, and any other
-# associated documentation or information provided by Altera or a partner
-# under Altera's Megafunction Partnership Program may be used only
-# to program PLD devices (but not masked PLD devices) from Altera. Any
-# other use of such megafunction design, netlist, support information,
-# device programming or simulation file, or any other related documentation
-# or information is prohibited for any other purpose, including, but not
-# limited to modification, reverse engineering, de-compiling, or use with
-# any other silicon devices, unless such use is explicitly licensed under
-# a separate agreement with Altera or a megafunction partner. Title to the
-# intellectual property, including patents, copyrights, trademarks, trade
-# secrets, or maskworks, embodied in any such megafunction design, netlist,
-# support information, device programming or simulation file, or any other
-# related documentation or information provided by Altera or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-
-QUARTUS_VERSION = "4.1"
-DATE = "10:30:54 January 31, 2005"
-
-
-# Revisions
-
-PROJECT_REVISION = "abc80"
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.1"
+DATE = "10:30:54 January 31, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "abc80"
diff --git a/abc80.qsf b/abc80.qsf
index 5fb0f87..49ab14b 100755..100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -1,595 +1,619 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Any megafunction design, and related netlist (encrypted or decrypted),
-# support information, device programming or simulation file, and any other
-# associated documentation or information provided by Altera or a partner
-# under Altera's Megafunction Partnership Program may be used only
-# to program PLD devices (but not masked PLD devices) from Altera. Any
-# other use of such megafunction design, netlist, support information,
-# device programming or simulation file, or any other related documentation
-# or information is prohibited for any other purpose, including, but not
-# limited to modification, reverse engineering, de-compiling, or use with
-# any other silicon devices, unless such use is explicitly licensed under
-# a separate agreement with Altera or a megafunction partner. Title to the
-# intellectual property, including patents, copyrights, trademarks, trade
-# secrets, or maskworks, embodied in any such megafunction design, netlist,
-# support information, device programming or simulation file, or any other
-# related documentation or information provided by Altera or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-# The default values for assignments are stored in the file
-# abc80_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
-set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2"
-set_global_assignment -name VERILOG_FILE sound.v
-set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
-set_global_assignment -name VHDL_FILE t80/T80.vhd
-set_global_assignment -name VHDL_FILE t80/T80s.vhd
-set_global_assignment -name VHDL_FILE t80/T80se.vhd
-set_global_assignment -name MIF_FILE data/basic80.mif
-set_global_assignment -name MIF_FILE data/cfram.mif
-set_global_assignment -name MIF_FILE data/videoram.mif
-set_global_assignment -name MIF_FILE data/abcdos.mif
-set_global_assignment -name MIF_FILE data/chargen.mif
-set_global_assignment -name MIF_FILE data/keyboard.mif
-set_global_assignment -name MIF_FILE data/mmu.mif
-set_global_assignment -name MIF_FILE data/abcbasic.mif
-set_global_assignment -name VERILOG_FILE mega/cfram.v
-set_global_assignment -name VERILOG_FILE mega/chargen.v
-set_global_assignment -name VERILOG_FILE mega/pll1.v
-set_global_assignment -name VERILOG_FILE mega/pll2.v
-set_global_assignment -name VERILOG_FILE mega/basic80.v
-set_global_assignment -name VERILOG_FILE mega/basicrom.v
-set_global_assignment -name VERILOG_FILE mega/mmuram.v
-set_global_assignment -name VERILOG_FILE mega/dosrom.v
-set_global_assignment -name VERILOG_FILE mega/printerrom.v
-set_global_assignment -name VERILOG_FILE mega/videoram.v
-set_global_assignment -name VERILOG_FILE mega/kbdram.v
-set_global_assignment -name VERILOG_FILE t80pio/t80pio.v
-set_global_assignment -name VERILOG_FILE debounce.v
-set_global_assignment -name VERILOG_FILE cfdisk.v
-set_global_assignment -name VERILOG_FILE display.v
-set_global_assignment -name VERILOG_FILE printer.v
-set_global_assignment -name VERILOG_FILE keyboard.v
-set_global_assignment -name VERILOG_FILE hexled.v
-set_global_assignment -name VERILOG_FILE hexascii.v
-set_global_assignment -name VERILOG_FILE abc80.v
-
-# Pin & Location Assignments
-# ==========================
-set_location_assignment PIN_W9 -to audio_l
-set_location_assignment PIN_U10 -to audio_r
-set_location_assignment PIN_H17 -to cf_a[0]
-set_location_assignment PIN_J15 -to cf_a[10]
-set_location_assignment PIN_H18 -to cf_a[1]
-set_location_assignment PIN_H19 -to cf_a[2]
-set_location_assignment PIN_W18 -to cf_a[3]
-set_location_assignment PIN_K15 -to cf_a[4]
-set_location_assignment PIN_J18 -to cf_a[5]
-set_location_assignment PIN_J17 -to cf_a[6]
-set_location_assignment PIN_J14 -to cf_a[7]
-set_location_assignment PIN_H14 -to cf_a[8]
-set_location_assignment PIN_J20 -to cf_a[9]
-set_location_assignment PIN_J19 -to cf_bvd1
-set_location_assignment PIN_J16 -to cf_bvd2
-set_location_assignment PIN_B13 -to cf_cd1_n
-set_location_assignment PIN_H20 -to cf_ce1_n
-set_location_assignment PIN_U19 -to cf_ce2_n
-set_location_assignment PIN_F20 -to cf_d[0]
-set_location_assignment PIN_D20 -to cf_d[10]
-set_location_assignment PIN_F17 -to cf_d[11]
-set_location_assignment PIN_E18 -to cf_d[12]
-set_location_assignment PIN_F16 -to cf_d[13]
-set_location_assignment PIN_F19 -to cf_d[14]
-set_location_assignment PIN_G16 -to cf_d[15]
-set_location_assignment PIN_F15 -to cf_d[1]
-set_location_assignment PIN_E19 -to cf_d[2]
-set_location_assignment PIN_F18 -to cf_d[3]
-set_location_assignment PIN_E17 -to cf_d[4]
-set_location_assignment PIN_D17 -to cf_d[5]
-set_location_assignment PIN_D18 -to cf_d[6]
-set_location_assignment PIN_C18 -to cf_d[7]
-set_location_assignment PIN_C19 -to cf_d[8]
-set_location_assignment PIN_D19 -to cf_d[9]
-set_location_assignment PIN_V19 -to cf_inpack_n
-set_location_assignment PIN_G19 -to cf_iord_n
-set_location_assignment PIN_G20 -to cf_iowr_n
-set_location_assignment PIN_D13 -to cf_oe_n
-set_location_assignment PIN_G17 -to cf_rdy
-set_location_assignment PIN_U20 -to cf_reg_n
-set_location_assignment PIN_G14 -to cf_wait_n
-set_location_assignment PIN_V18 -to cf_we_n
-set_location_assignment PIN_H16 -to cf_wp
-set_location_assignment PIN_K5 -to clkin
-set_location_assignment PIN_A14 -to enet_ads_n
-set_location_assignment PIN_B15 -to enet_aen
-set_location_assignment PIN_C16 -to enet_be_n[0]
-set_location_assignment PIN_B16 -to enet_be_n[1]
-set_location_assignment PIN_D16 -to enet_be_n[2]
-set_location_assignment PIN_E16 -to enet_be_n[3]
-set_location_assignment PIN_B17 -to enet_cycle_n
-set_location_assignment PIN_C15 -to enet_datacs_n
-set_location_assignment PIN_D15 -to enet_intrq0
-set_location_assignment PIN_F14 -to enet_iochrdy
-set_location_assignment PIN_A15 -to enet_ior_n
-set_location_assignment PIN_E15 -to enet_iow_n
-set_location_assignment PIN_C17 -to enet_lclk
-set_location_assignment PIN_D3 -to enet_ldev_n
-set_location_assignment PIN_B18 -to enet_rdyrtn_n
-set_location_assignment PIN_A17 -to enet_w_r_n
-set_location_assignment PIN_A12 -to flash_cs_n
-set_location_assignment PIN_B12 -to flash_oe_n
-set_location_assignment PIN_D12 -to flash_rw_n
-set_location_assignment PIN_C12 -to flash_ry_by_n
-set_location_assignment PIN_B4 -to fse_a[0]
-set_location_assignment PIN_E4 -to fse_a[10]
-set_location_assignment PIN_E5 -to fse_a[11]
-set_location_assignment PIN_F3 -to fse_a[12]
-set_location_assignment PIN_E3 -to fse_a[13]
-set_location_assignment PIN_E2 -to fse_a[14]
-set_location_assignment PIN_F4 -to fse_a[15]
-set_location_assignment PIN_F5 -to fse_a[16]
-set_location_assignment PIN_F2 -to fse_a[17]
-set_location_assignment PIN_F1 -to fse_a[18]
-set_location_assignment PIN_F6 -to fse_a[19]
-set_location_assignment PIN_A4 -to fse_a[1]
-set_location_assignment PIN_G5 -to fse_a[20]
-set_location_assignment PIN_G1 -to fse_a[21]
-set_location_assignment PIN_G2 -to fse_a[22]
-set_location_assignment PIN_D5 -to fse_a[2]
-set_location_assignment PIN_D6 -to fse_a[3]
-set_location_assignment PIN_C5 -to fse_a[4]
-set_location_assignment PIN_B5 -to fse_a[5]
-set_location_assignment PIN_C2 -to fse_a[6]
-set_location_assignment PIN_D2 -to fse_a[7]
-set_location_assignment PIN_D4 -to fse_a[8]
-set_location_assignment PIN_D1 -to fse_a[9]
-set_location_assignment PIN_C6 -to fse_d[0]
-set_location_assignment PIN_F8 -to fse_d[10]
-set_location_assignment PIN_E8 -to fse_d[11]
-set_location_assignment PIN_B8 -to fse_d[12]
-set_location_assignment PIN_A8 -to fse_d[13]
-set_location_assignment PIN_D8 -to fse_d[14]
-set_location_assignment PIN_C8 -to fse_d[15]
-set_location_assignment PIN_B9 -to fse_d[16]
-set_location_assignment PIN_A9 -to fse_d[17]
-set_location_assignment PIN_D9 -to fse_d[18]
-set_location_assignment PIN_C9 -to fse_d[19]
-set_location_assignment PIN_E6 -to fse_d[1]
-set_location_assignment PIN_E9 -to fse_d[20]
-set_location_assignment PIN_E10 -to fse_d[21]
-set_location_assignment PIN_B10 -to fse_d[22]
-set_location_assignment PIN_A10 -to fse_d[23]
-set_location_assignment PIN_F10 -to fse_d[24]
-set_location_assignment PIN_C10 -to fse_d[25]
-set_location_assignment PIN_D10 -to fse_d[26]
-set_location_assignment PIN_C11 -to fse_d[27]
-set_location_assignment PIN_D11 -to fse_d[28]
-set_location_assignment PIN_B11 -to fse_d[29]
-set_location_assignment PIN_B6 -to fse_d[2]
-set_location_assignment PIN_A11 -to fse_d[30]
-set_location_assignment PIN_E11 -to fse_d[31]
-set_location_assignment PIN_A6 -to fse_d[3]
-set_location_assignment PIN_F7 -to fse_d[4]
-set_location_assignment PIN_E7 -to fse_d[5]
-set_location_assignment PIN_B7 -to fse_d[6]
-set_location_assignment PIN_A7 -to fse_d[7]
-set_location_assignment PIN_D7 -to fse_d[8]
-set_location_assignment PIN_C7 -to fse_d[9]
-set_location_assignment PIN_E14 -to led[0]
-set_location_assignment PIN_E13 -to led[1]
-set_location_assignment PIN_C14 -to led[2]
-set_location_assignment PIN_D14 -to led[3]
-set_location_assignment PIN_E12 -to led[4]
-set_location_assignment PIN_F12 -to led[5]
-set_location_assignment PIN_B3 -to led[6]
-set_location_assignment PIN_B14 -to led[7]
-set_location_assignment PIN_G15 -to p1_a21
-set_location_assignment PIN_H15 -to p1_a28
-set_location_assignment PIN_G18 -to p1_a29
-set_location_assignment PIN_U18 -to p1_a38
-set_location_assignment PIN_P27 -to p1_clkout
-set_location_assignment PIN_L14 -to pld_clkfb
-set_location_assignment PIN_L8 -to pld_clkout
-set_location_assignment PIN_K6 -to proto1_clkout
-set_location_assignment PIN_K14 -to proto2_clkout
-set_location_assignment PIN_Y10 -to ps2_kclk
-set_location_assignment PIN_V10 -to ps2_kdata
-set_location_assignment PIN_T10 -to ps2_mclk
-set_location_assignment PIN_Y9 -to ps2_mdata
-set_location_assignment PIN_W10 -to ps2_sel
-set_location_assignment PIN_C4 -to reset_n
-set_location_assignment PIN_U6 -to s7_0[0]
-set_location_assignment PIN_V6 -to s7_0[1]
-set_location_assignment PIN_W7 -to s7_0[2]
-set_location_assignment PIN_Y7 -to s7_0[3]
-set_location_assignment PIN_R7 -to s7_0[4]
-set_location_assignment PIN_T8 -to s7_0[5]
-set_location_assignment PIN_V7 -to s7_0[6]
-set_location_assignment PIN_U7 -to s7_0[7]
-set_location_assignment PIN_T5 -to s7_1[0]
-set_location_assignment PIN_U5 -to s7_1[1]
-set_location_assignment PIN_V5 -to s7_1[2]
-set_location_assignment PIN_W5 -to s7_1[3]
-set_location_assignment PIN_T6 -to s7_1[4]
-set_location_assignment PIN_T7 -to s7_1[5]
-set_location_assignment PIN_W6 -to s7_1[6]
-set_location_assignment PIN_Y6 -to s7_1[7]
-set_location_assignment PIN_M2 -to sd_a[0]
-set_location_assignment PIN_H6 -to sd_a[10]
-set_location_assignment PIN_H5 -to sd_a[11]
-set_location_assignment PIN_M1 -to sd_a[1]
-set_location_assignment PIN_M6 -to sd_a[2]
-set_location_assignment PIN_M4 -to sd_a[3]
-set_location_assignment PIN_J8 -to sd_a[4]
-set_location_assignment PIN_J7 -to sd_a[5]
-set_location_assignment PIN_J6 -to sd_a[6]
-set_location_assignment PIN_J5 -to sd_a[7]
-set_location_assignment PIN_J4 -to sd_a[8]
-set_location_assignment PIN_J3 -to sd_a[9]
-set_location_assignment PIN_H7 -to sd_ba[0]
-set_location_assignment PIN_H1 -to sd_ba[1]
-set_location_assignment PIN_G3 -to sd_cas_n
-set_location_assignment PIN_G7 -to sd_cke
-set_location_assignment PIN_L13 -to sd_clk
-set_location_assignment PIN_G6 -to sd_cs_n
-set_location_assignment PIN_M5 -to sd_dq[0]
-set_location_assignment PIN_P7 -to sd_dq[10]
-set_location_assignment PIN_P2 -to sd_dq[11]
-set_location_assignment PIN_P1 -to sd_dq[12]
-set_location_assignment PIN_P6 -to sd_dq[13]
-set_location_assignment PIN_P5 -to sd_dq[14]
-set_location_assignment PIN_P3 -to sd_dq[15]
-set_location_assignment PIN_P4 -to sd_dq[16]
-set_location_assignment PIN_R1 -to sd_dq[17]
-set_location_assignment PIN_R2 -to sd_dq[18]
-set_location_assignment PIN_R6 -to sd_dq[19]
-set_location_assignment PIN_M3 -to sd_dq[1]
-set_location_assignment PIN_R5 -to sd_dq[20]
-set_location_assignment PIN_R3 -to sd_dq[21]
-set_location_assignment PIN_R4 -to sd_dq[22]
-set_location_assignment PIN_T4 -to sd_dq[23]
-set_location_assignment PIN_T2 -to sd_dq[24]
-set_location_assignment PIN_T3 -to sd_dq[25]
-set_location_assignment PIN_U1 -to sd_dq[26]
-set_location_assignment PIN_U4 -to sd_dq[27]
-set_location_assignment PIN_U2 -to sd_dq[28]
-set_location_assignment PIN_U3 -to sd_dq[29]
-set_location_assignment PIN_M7 -to sd_dq[2]
-set_location_assignment PIN_V3 -to sd_dq[30]
-set_location_assignment PIN_V2 -to sd_dq[31]
-set_location_assignment PIN_N6 -to sd_dq[3]
-set_location_assignment PIN_N1 -to sd_dq[4]
-set_location_assignment PIN_N2 -to sd_dq[5]
-set_location_assignment PIN_N4 -to sd_dq[6]
-set_location_assignment PIN_N3 -to sd_dq[7]
-set_location_assignment PIN_N5 -to sd_dq[8]
-set_location_assignment PIN_N7 -to sd_dq[9]
-set_location_assignment PIN_J2 -to sd_dqm[0]
-set_location_assignment PIN_J1 -to sd_dqm[1]
-set_location_assignment PIN_H4 -to sd_dqm[2]
-set_location_assignment PIN_H3 -to sd_dqm[3]
-set_location_assignment PIN_H2 -to sd_ras_n
-set_location_assignment PIN_G4 -to sd_we_n
-set_location_assignment PIN_V17 -to sram_be_n[0]
-set_location_assignment PIN_V16 -to sram_be_n[1]
-set_location_assignment PIN_W16 -to sram_be_n[2]
-set_location_assignment PIN_T16 -to sram_be_n[3]
-set_location_assignment PIN_W17 -to sram_cs_n
-set_location_assignment PIN_Y17 -to sram_oe_n
-set_location_assignment PIN_U16 -to sram_we_n
-set_location_assignment PIN_W3 -to sw[0]
-set_location_assignment PIN_Y4 -to sw[1]
-set_location_assignment PIN_V4 -to sw[2]
-set_location_assignment PIN_W4 -to sw[3]
-set_location_assignment PIN_J13 -to ttya_cts
-set_location_assignment PIN_M16 -to ttya_dcd
-set_location_assignment PIN_M20 -to ttya_dsr
-set_location_assignment PIN_M15 -to ttya_dtr
-set_location_assignment PIN_M19 -to ttya_ri
-set_location_assignment PIN_K19 -to ttya_rts
-set_location_assignment PIN_K16 -to ttya_rxd
-set_location_assignment PIN_M14 -to ttya_txd
-set_location_assignment PIN_C13 -to ttyb_rxd
-set_location_assignment PIN_A13 -to ttyb_txd
-set_location_assignment PIN_T12 -to vga_b[0]
-set_location_assignment PIN_T11 -to vga_b[1]
-set_location_assignment PIN_W12 -to vga_b[2]
-set_location_assignment PIN_W8 -to vga_b[3]
-set_location_assignment PIN_Y12 -to vga_b[4]
-set_location_assignment PIN_Y8 -to vga_b[5]
-set_location_assignment PIN_V9 -to vga_b[6]
-set_location_assignment PIN_U9 -to vga_b[7]
-set_location_assignment PIN_R14 -to vga_blank_n
-set_location_assignment PIN_T15 -to vga_g[0]
-set_location_assignment PIN_W15 -to vga_g[1]
-set_location_assignment PIN_Y15 -to vga_g[2]
-set_location_assignment PIN_U15 -to vga_g[3]
-set_location_assignment PIN_V15 -to vga_g[4]
-set_location_assignment PIN_V14 -to vga_g[5]
-set_location_assignment PIN_U14 -to vga_g[6]
-set_location_assignment PIN_Y14 -to vga_g[7]
-set_location_assignment PIN_T9 -to vga_hs
-set_location_assignment PIN_V11 -to vga_m1
-set_location_assignment PIN_U11 -to vga_m2
-set_location_assignment PIN_U12 -to vga_r[0]
-set_location_assignment PIN_V12 -to vga_r[1]
-set_location_assignment PIN_T13 -to vga_r[2]
-set_location_assignment PIN_R13 -to vga_r[3]
-set_location_assignment PIN_Y13 -to vga_r[4]
-set_location_assignment PIN_W13 -to vga_r[5]
-set_location_assignment PIN_U13 -to vga_r[6]
-set_location_assignment PIN_V13 -to vga_r[7]
-set_location_assignment PIN_T14 -to vga_sync_n
-set_location_assignment PIN_W14 -to vga_sync_t
-set_location_assignment PIN_R9 -to vga_vs
-set_location_assignment PIN_M13 -to cf_power
-
-# Timing Assignments
-# ==================
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS OFF
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name FAMILY Cyclone
-set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name AUTO_ROM_RECOGNITION OFF
-set_global_assignment -name AUTO_RAM_RECOGNITION OFF
-set_global_assignment -name AUTO_RESOURCE_SHARING ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name TOP_LEVEL_ENTITY abc80
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP1C20F400C7
-set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS OFF
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
-set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
-set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name GENERATE_HEX_FILE ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Design Assistant Assignments
-# ============================
-set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
-set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
-set_global_assignment -name ASSG_CAT OFF
-set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
-set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
-set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
-set_global_assignment -name CLK_CAT OFF
-set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
-set_global_assignment -name CLK_RULE_INV_CLOCK OFF
-set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
-set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
-set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
-set_global_assignment -name CLK_RULE_MIX_EDGES OFF
-set_global_assignment -name RESET_CAT OFF
-set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
-set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
-set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
-set_global_assignment -name TIMING_CAT OFF
-set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
-set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
-set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
-set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
-set_global_assignment -name SIGNALRACE_CAT OFF
-set_global_assignment -name ACLK_CAT OFF
-set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
-set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
-set_global_assignment -name HCPY_CAT ON
-set_global_assignment -name HCPY_VREF_PINS OFF
-
-# Programmer Assignments
-# ======================
-set_global_assignment -name GENERATE_JAM_FILE ON
-
-# SignalTap II Assignments
-# ========================
-set_global_assignment -name ENABLE_SIGNALTAP off
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-
-# LogicLock Region Assignments
-# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# ------------------
-# start CLOCK(clkin)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id clkin
- set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz" -section_id clkin
-
-# end CLOCK(clkin)
-# ----------------
-
-# ----------------------
-# start CLOCK(pld_clkfb)
-
- # Timing Assignments
- # ==================
-set_global_assignment -name DUTY_CYCLE 50 -section_id pld_clkfb
-set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id pld_clkfb
- set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id pld_clkfb
-set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id pld_clkfb
- set_global_assignment -name BASED_ON_CLOCK_SETTINGS clkin -section_id pld_clkfb
-
-# end CLOCK(pld_clkfb)
-# --------------------
-
-# -----------------------------------------
-# start EDA_TOOL_SETTINGS(eda_board_design)
-
- # EDA Netlist Writer Assignments
- # ==============================
- set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design
-
-# end EDA_TOOL_SETTINGS(eda_board_design)
-# ---------------------------------------
-
-# ------------------------------------------------
-# start EDA_TOOL_SETTINGS(eda_formal_verification)
-
- # EDA Netlist Writer Assignments
- # ==============================
- set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification
-
-# end EDA_TOOL_SETTINGS(eda_formal_verification)
-# ----------------------------------------------
-
-# -----------------------------------
-# start EDA_TOOL_SETTINGS(eda_palace)
-
- # EDA Netlist Writer Assignments
- # ==============================
- set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace
-
-# end EDA_TOOL_SETTINGS(eda_palace)
-# ---------------------------------
-
-# ---------------------------------------
-# start EDA_TOOL_SETTINGS(eda_simulation)
-
- # EDA Netlist Writer Assignments
- # ==============================
- set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation
-
-# end EDA_TOOL_SETTINGS(eda_simulation)
-# -------------------------------------
-
-# --------------------------------------------
-# start EDA_TOOL_SETTINGS(eda_timing_analysis)
-
- # EDA Netlist Writer Assignments
- # ==============================
- set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis
-
-# end EDA_TOOL_SETTINGS(eda_timing_analysis)
-# ------------------------------------------
-
-# -------------------
-# start ENTITY(abc80)
-
- # Timing Assignments
- # ==================
- set_instance_assignment -name CLOCK_SETTINGS pld_clkfb -to pld_clkfb
- set_instance_assignment -name CLOCK_SETTINGS clkin -to clkin
-
- # Fitter Assignments
- # ==================
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[0]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[10]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[1]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[2]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[3]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[4]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[5]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[6]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[7]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[8]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[9]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_bvd1
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_bvd2
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_cd1_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_ce1_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_ce2_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[0]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[10]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[11]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[12]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[13]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[14]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[15]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[1]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[2]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[3]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[4]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[5]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[6]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[7]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[8]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[9]
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_inpack_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_iord_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_iowr_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_oe_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_rdy
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_reg_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_wait_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_we_n
- set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_wp
- set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to enet_iochrdy
-
-# end ENTITY(abc80)
-# -----------------
+# Copyright (C) 1991-2005 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+# The default values for assignments are stored in the file
+# abc80_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION 8.1
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_A13 -to gpio_0[0]
+set_location_assignment PIN_B13 -to gpio_0[1]
+set_location_assignment PIN_A14 -to gpio_0[2]
+set_location_assignment PIN_B14 -to gpio_0[3]
+set_location_assignment PIN_A15 -to gpio_0[4]
+set_location_assignment PIN_B15 -to gpio_0[5]
+set_location_assignment PIN_A16 -to gpio_0[6]
+set_location_assignment PIN_B16 -to gpio_0[7]
+set_location_assignment PIN_A17 -to gpio_0[8]
+set_location_assignment PIN_B17 -to gpio_0[9]
+set_location_assignment PIN_A18 -to gpio_0[10]
+set_location_assignment PIN_B18 -to gpio_0[11]
+set_location_assignment PIN_A19 -to gpio_0[12]
+set_location_assignment PIN_B19 -to gpio_0[13]
+set_location_assignment PIN_A20 -to gpio_0[14]
+set_location_assignment PIN_B20 -to gpio_0[15]
+set_location_assignment PIN_C21 -to gpio_0[16]
+set_location_assignment PIN_C22 -to gpio_0[17]
+set_location_assignment PIN_D21 -to gpio_0[18]
+set_location_assignment PIN_D22 -to gpio_0[19]
+set_location_assignment PIN_E21 -to gpio_0[20]
+set_location_assignment PIN_E22 -to gpio_0[21]
+set_location_assignment PIN_F21 -to gpio_0[22]
+set_location_assignment PIN_F22 -to gpio_0[23]
+set_location_assignment PIN_G21 -to gpio_0[24]
+set_location_assignment PIN_G22 -to gpio_0[25]
+set_location_assignment PIN_J21 -to gpio_0[26]
+set_location_assignment PIN_J22 -to gpio_0[27]
+set_location_assignment PIN_K21 -to gpio_0[28]
+set_location_assignment PIN_K22 -to gpio_0[29]
+set_location_assignment PIN_J19 -to gpio_0[30]
+set_location_assignment PIN_J20 -to gpio_0[31]
+set_location_assignment PIN_J18 -to gpio_0[32]
+set_location_assignment PIN_K20 -to gpio_0[33]
+set_location_assignment PIN_L19 -to gpio_0[34]
+set_location_assignment PIN_L18 -to gpio_0[35]
+set_location_assignment PIN_H12 -to gpio_1[0]
+set_location_assignment PIN_H13 -to gpio_1[1]
+set_location_assignment PIN_H14 -to gpio_1[2]
+set_location_assignment PIN_G15 -to gpio_1[3]
+set_location_assignment PIN_E14 -to gpio_1[4]
+set_location_assignment PIN_E15 -to gpio_1[5]
+set_location_assignment PIN_F15 -to gpio_1[6]
+set_location_assignment PIN_G16 -to gpio_1[7]
+set_location_assignment PIN_F12 -to gpio_1[8]
+set_location_assignment PIN_F13 -to gpio_1[9]
+set_location_assignment PIN_C14 -to gpio_1[10]
+set_location_assignment PIN_D14 -to gpio_1[11]
+set_location_assignment PIN_D15 -to gpio_1[12]
+set_location_assignment PIN_D16 -to gpio_1[13]
+set_location_assignment PIN_C17 -to gpio_1[14]
+set_location_assignment PIN_C18 -to gpio_1[15]
+set_location_assignment PIN_C19 -to gpio_1[16]
+set_location_assignment PIN_C20 -to gpio_1[17]
+set_location_assignment PIN_D19 -to gpio_1[18]
+set_location_assignment PIN_D20 -to gpio_1[19]
+set_location_assignment PIN_E20 -to gpio_1[20]
+set_location_assignment PIN_F20 -to gpio_1[21]
+set_location_assignment PIN_E19 -to gpio_1[22]
+set_location_assignment PIN_E18 -to gpio_1[23]
+set_location_assignment PIN_G20 -to gpio_1[24]
+set_location_assignment PIN_G18 -to gpio_1[25]
+set_location_assignment PIN_G17 -to gpio_1[26]
+set_location_assignment PIN_H17 -to gpio_1[27]
+set_location_assignment PIN_J15 -to gpio_1[28]
+set_location_assignment PIN_H18 -to gpio_1[29]
+set_location_assignment PIN_N22 -to gpio_1[30]
+set_location_assignment PIN_N21 -to gpio_1[31]
+set_location_assignment PIN_P15 -to gpio_1[32]
+set_location_assignment PIN_N15 -to gpio_1[33]
+set_location_assignment PIN_P17 -to gpio_1[34]
+set_location_assignment PIN_P18 -to gpio_1[35]
+set_location_assignment PIN_L22 -to sw[0]
+set_location_assignment PIN_L21 -to sw[1]
+set_location_assignment PIN_M22 -to sw[2]
+set_location_assignment PIN_V12 -to sw[3]
+set_location_assignment PIN_W12 -to sw[4]
+set_location_assignment PIN_U12 -to sw[5]
+set_location_assignment PIN_U11 -to sw[6]
+set_location_assignment PIN_M2 -to sw[7]
+set_location_assignment PIN_M1 -to sw[8]
+set_location_assignment PIN_L2 -to sw[9]
+set_location_assignment PIN_J2 -to s7_0[0]
+set_location_assignment PIN_J1 -to s7_0[1]
+set_location_assignment PIN_H2 -to s7_0[2]
+set_location_assignment PIN_H1 -to s7_0[3]
+set_location_assignment PIN_F2 -to s7_0[4]
+set_location_assignment PIN_F1 -to s7_0[5]
+set_location_assignment PIN_E2 -to s7_0[6]
+set_location_assignment PIN_E1 -to s7_1[0]
+set_location_assignment PIN_H6 -to s7_1[1]
+set_location_assignment PIN_H5 -to s7_1[2]
+set_location_assignment PIN_H4 -to s7_1[3]
+set_location_assignment PIN_G3 -to s7_1[4]
+set_location_assignment PIN_D2 -to s7_1[5]
+set_location_assignment PIN_D1 -to s7_1[6]
+set_location_assignment PIN_G5 -to s7_2[0]
+set_location_assignment PIN_G6 -to s7_2[1]
+set_location_assignment PIN_C2 -to s7_2[2]
+set_location_assignment PIN_C1 -to s7_2[3]
+set_location_assignment PIN_E3 -to s7_2[4]
+set_location_assignment PIN_E4 -to s7_2[5]
+set_location_assignment PIN_D3 -to s7_2[6]
+set_location_assignment PIN_F4 -to s7_3[0]
+set_location_assignment PIN_D5 -to s7_3[1]
+set_location_assignment PIN_D6 -to s7_3[2]
+set_location_assignment PIN_J4 -to s7_3[3]
+set_location_assignment PIN_L8 -to s7_3[4]
+set_location_assignment PIN_F3 -to s7_3[5]
+set_location_assignment PIN_D4 -to s7_3[6]
+set_location_assignment PIN_R22 -to key_n[0]
+set_location_assignment PIN_R21 -to key_n[1]
+set_location_assignment PIN_T22 -to key_n[2]
+set_location_assignment PIN_T21 -to key_n[3]
+set_location_assignment PIN_R20 -to ledr[0]
+set_location_assignment PIN_R19 -to ledr[1]
+set_location_assignment PIN_U19 -to ledr[2]
+set_location_assignment PIN_Y19 -to ledr[3]
+set_location_assignment PIN_T18 -to ledr[4]
+set_location_assignment PIN_V19 -to ledr[5]
+set_location_assignment PIN_Y18 -to ledr[6]
+set_location_assignment PIN_U18 -to ledr[7]
+set_location_assignment PIN_R18 -to ledr[8]
+set_location_assignment PIN_R17 -to ledr[9]
+set_location_assignment PIN_U22 -to ledg[0]
+set_location_assignment PIN_U21 -to ledg[1]
+set_location_assignment PIN_V22 -to ledg[2]
+set_location_assignment PIN_V21 -to ledg[3]
+set_location_assignment PIN_W22 -to ledg[4]
+set_location_assignment PIN_W21 -to ledg[5]
+set_location_assignment PIN_Y22 -to ledg[6]
+set_location_assignment PIN_Y21 -to ledg[7]
+set_location_assignment PIN_D12 -to clock_27[0]
+set_location_assignment PIN_E12 -to clock_27[1]
+set_location_assignment PIN_B12 -to clock_24[0]
+set_location_assignment PIN_A12 -to clock_24[1]
+set_location_assignment PIN_L1 -to clock_50
+set_location_assignment PIN_M21 -to ext_clock
+set_location_assignment PIN_H15 -to ps2_clk
+set_location_assignment PIN_J14 -to ps2_dat
+set_location_assignment PIN_F14 -to uart_rxd
+set_location_assignment PIN_G12 -to uart_txd
+set_location_assignment PIN_E8 -to tdi
+set_location_assignment PIN_D8 -to tcs
+set_location_assignment PIN_C7 -to tck
+set_location_assignment PIN_D7 -to tdo
+set_location_assignment PIN_D9 -to vga_r[0]
+set_location_assignment PIN_C9 -to vga_r[1]
+set_location_assignment PIN_A7 -to vga_r[2]
+set_location_assignment PIN_B7 -to vga_r[3]
+set_location_assignment PIN_B8 -to vga_g[0]
+set_location_assignment PIN_C10 -to vga_g[1]
+set_location_assignment PIN_B9 -to vga_g[2]
+set_location_assignment PIN_A8 -to vga_g[3]
+set_location_assignment PIN_A9 -to vga_b[0]
+set_location_assignment PIN_D11 -to vga_b[1]
+set_location_assignment PIN_A10 -to vga_b[2]
+set_location_assignment PIN_B10 -to vga_b[3]
+set_location_assignment PIN_A11 -to vga_hs
+set_location_assignment PIN_B11 -to vga_vs
+set_location_assignment PIN_A3 -to i2c_sclk
+set_location_assignment PIN_B3 -to i2c_sdat
+set_location_assignment PIN_A6 -to aud_adclrck
+set_location_assignment PIN_B6 -to aud_adcdat
+set_location_assignment PIN_A5 -to aud_daclrck
+set_location_assignment PIN_B5 -to aud_dacdat
+set_location_assignment PIN_B4 -to aud_xck
+set_location_assignment PIN_A4 -to aud_bclk
+set_location_assignment PIN_W4 -to dram_a[0]
+set_location_assignment PIN_W5 -to dram_a[1]
+set_location_assignment PIN_Y3 -to dram_a[2]
+set_location_assignment PIN_Y4 -to dram_a[3]
+set_location_assignment PIN_R6 -to dram_a[4]
+set_location_assignment PIN_R5 -to dram_a[5]
+set_location_assignment PIN_P6 -to dram_a[6]
+set_location_assignment PIN_P5 -to dram_a[7]
+set_location_assignment PIN_P3 -to dram_a[8]
+set_location_assignment PIN_N4 -to dram_a[9]
+set_location_assignment PIN_W3 -to dram_a[10]
+set_location_assignment PIN_N6 -to dram_a[11]
+set_location_assignment PIN_U3 -to dram_ba[0]
+set_location_assignment PIN_V4 -to dram_ba[1]
+set_location_assignment PIN_T3 -to dram_cas_n
+set_location_assignment PIN_N3 -to dram_cke
+set_location_assignment PIN_U4 -to dram_clk
+set_location_assignment PIN_T6 -to dram_cs_n
+set_location_assignment PIN_U1 -to dram_dq[0]
+set_location_assignment PIN_U2 -to dram_dq[1]
+set_location_assignment PIN_V1 -to dram_dq[2]
+set_location_assignment PIN_V2 -to dram_dq[3]
+set_location_assignment PIN_W1 -to dram_dq[4]
+set_location_assignment PIN_W2 -to dram_dq[5]
+set_location_assignment PIN_Y1 -to dram_dq[6]
+set_location_assignment PIN_Y2 -to dram_dq[7]
+set_location_assignment PIN_N1 -to dram_dq[8]
+set_location_assignment PIN_N2 -to dram_dq[9]
+set_location_assignment PIN_P1 -to dram_dq[10]
+set_location_assignment PIN_P2 -to dram_dq[11]
+set_location_assignment PIN_R1 -to dram_dq[12]
+set_location_assignment PIN_R2 -to dram_dq[13]
+set_location_assignment PIN_T1 -to dram_dq[14]
+set_location_assignment PIN_T2 -to dram_dq[15]
+set_location_assignment PIN_R7 -to dram_dqm[0]
+set_location_assignment PIN_T5 -to dram_ras_n
+set_location_assignment PIN_M5 -to dram_dqm[1]
+set_location_assignment PIN_R8 -to dram_we_n
+set_location_assignment PIN_AB20 -to fl_a[0]
+set_location_assignment PIN_AA14 -to fl_a[1]
+set_location_assignment PIN_Y16 -to fl_a[2]
+set_location_assignment PIN_R15 -to fl_a[3]
+set_location_assignment PIN_T15 -to fl_a[4]
+set_location_assignment PIN_U15 -to fl_a[5]
+set_location_assignment PIN_V15 -to fl_a[6]
+set_location_assignment PIN_W15 -to fl_a[7]
+set_location_assignment PIN_R14 -to fl_a[8]
+set_location_assignment PIN_Y13 -to fl_a[9]
+set_location_assignment PIN_R12 -to fl_a[10]
+set_location_assignment PIN_T12 -to fl_a[11]
+set_location_assignment PIN_AB14 -to fl_a[12]
+set_location_assignment PIN_AA13 -to fl_a[13]
+set_location_assignment PIN_AB13 -to fl_a[14]
+set_location_assignment PIN_AA12 -to fl_a[15]
+set_location_assignment PIN_AB12 -to fl_a[16]
+set_location_assignment PIN_AA20 -to fl_a[17]
+set_location_assignment PIN_U14 -to fl_a[18]
+set_location_assignment PIN_V14 -to fl_a[19]
+set_location_assignment PIN_U13 -to fl_a[20]
+set_location_assignment PIN_R13 -to fl_a[21]
+set_location_assignment PIN_AB16 -to fl_dq[0]
+set_location_assignment PIN_AA16 -to fl_dq[1]
+set_location_assignment PIN_AB17 -to fl_dq[2]
+set_location_assignment PIN_AA17 -to fl_dq[3]
+set_location_assignment PIN_AB18 -to fl_dq[4]
+set_location_assignment PIN_AA18 -to fl_dq[5]
+set_location_assignment PIN_AB19 -to fl_dq[6]
+set_location_assignment PIN_AA19 -to fl_dq[7]
+set_location_assignment PIN_AA15 -to fl_oe_n
+set_location_assignment PIN_W14 -to fl_rst_n
+set_location_assignment PIN_Y14 -to fl_we_n
+set_location_assignment PIN_AA3 -to sram_a[0]
+set_location_assignment PIN_AB3 -to sram_a[1]
+set_location_assignment PIN_AA4 -to sram_a[2]
+set_location_assignment PIN_AB4 -to sram_a[3]
+set_location_assignment PIN_AA5 -to sram_a[4]
+set_location_assignment PIN_AB10 -to sram_a[5]
+set_location_assignment PIN_AA11 -to sram_a[6]
+set_location_assignment PIN_AB11 -to sram_a[7]
+set_location_assignment PIN_V11 -to sram_a[8]
+set_location_assignment PIN_W11 -to sram_a[9]
+set_location_assignment PIN_R11 -to sram_a[10]
+set_location_assignment PIN_T11 -to sram_a[11]
+set_location_assignment PIN_Y10 -to sram_a[12]
+set_location_assignment PIN_U10 -to sram_a[13]
+set_location_assignment PIN_R10 -to sram_a[14]
+set_location_assignment PIN_T7 -to sram_a[15]
+set_location_assignment PIN_Y6 -to sram_a[16]
+set_location_assignment PIN_Y5 -to sram_a[17]
+set_location_assignment PIN_AB5 -to sram_ce_n
+set_location_assignment PIN_AA6 -to sram_dq[0]
+set_location_assignment PIN_AB6 -to sram_dq[1]
+set_location_assignment PIN_AA7 -to sram_dq[2]
+set_location_assignment PIN_AB7 -to sram_dq[3]
+set_location_assignment PIN_AA8 -to sram_dq[4]
+set_location_assignment PIN_AB8 -to sram_dq[5]
+set_location_assignment PIN_AA9 -to sram_dq[6]
+set_location_assignment PIN_AB9 -to sram_dq[7]
+set_location_assignment PIN_Y9 -to sram_dq[8]
+set_location_assignment PIN_W9 -to sram_dq[9]
+set_location_assignment PIN_V9 -to sram_dq[10]
+set_location_assignment PIN_U9 -to sram_dq[11]
+set_location_assignment PIN_R9 -to sram_dq[12]
+set_location_assignment PIN_W8 -to sram_dq[13]
+set_location_assignment PIN_V8 -to sram_dq[14]
+set_location_assignment PIN_U8 -to sram_dq[15]
+set_location_assignment PIN_Y7 -to sram_be_n[0]
+set_location_assignment PIN_T8 -to sram_oe_n
+set_location_assignment PIN_W7 -to sram_be_n[1]
+set_location_assignment PIN_AA10 -to sram_we_n
+set_location_assignment PIN_V20 -to sd_clk
+set_location_assignment PIN_Y20 -to sd_cmd
+set_location_assignment PIN_W20 -to sd_dat0
+set_location_assignment PIN_U20 -to sd_dat3
+
+# Timing Assignments
+# ==================
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS OFF
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name AUTO_ROM_RECOGNITION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name TOP_LEVEL_ENTITY abc80
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS OFF
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
+set_global_assignment -name MAX_SCC_SIZE 50
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name GENERATE_HEX_FILE ON
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+
+# Design Assistant Assignments
+# ============================
+set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
+set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
+set_global_assignment -name ASSG_CAT OFF
+set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
+set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
+set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
+set_global_assignment -name CLK_CAT OFF
+set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
+set_global_assignment -name CLK_RULE_INV_CLOCK OFF
+set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
+set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
+set_global_assignment -name CLK_RULE_MIX_EDGES OFF
+set_global_assignment -name RESET_CAT OFF
+set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
+set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
+set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
+set_global_assignment -name TIMING_CAT OFF
+set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
+set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
+set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
+set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
+set_global_assignment -name SIGNALRACE_CAT OFF
+set_global_assignment -name ACLK_CAT OFF
+set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
+set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
+set_global_assignment -name HCPY_CAT ON
+set_global_assignment -name HCPY_VREF_PINS OFF
+
+# Programmer Assignments
+# ======================
+set_global_assignment -name GENERATE_JAM_FILE ON
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# ------------------
+# start CLOCK(clkin)
+
+ # Timing Assignments
+ # ==================
+
+# end CLOCK(clkin)
+# ----------------
+
+# ----------------------
+# start CLOCK(pld_clkfb)
+
+ # Timing Assignments
+ # ==================
+
+# end CLOCK(pld_clkfb)
+# --------------------
+
+# -----------------------------------------
+# start EDA_TOOL_SETTINGS(eda_board_design)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design
+
+# end EDA_TOOL_SETTINGS(eda_board_design)
+# ---------------------------------------
+
+# ------------------------------------------------
+# start EDA_TOOL_SETTINGS(eda_formal_verification)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification
+
+# end EDA_TOOL_SETTINGS(eda_formal_verification)
+# ----------------------------------------------
+
+# -----------------------------------
+# start EDA_TOOL_SETTINGS(eda_palace)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace
+
+# end EDA_TOOL_SETTINGS(eda_palace)
+# ---------------------------------
+
+# ---------------------------------------
+# start EDA_TOOL_SETTINGS(eda_simulation)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# --------------------------------------------
+# start EDA_TOOL_SETTINGS(eda_timing_analysis)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
+set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis
+
+# end EDA_TOOL_SETTINGS(eda_timing_analysis)
+# ------------------------------------------
+
+# -------------------
+# start ENTITY(abc80)
+
+ # Timing Assignments
+ # ==================
+
+ # Fitter Assignments
+ # ==================
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[0]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[10]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[7]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[8]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_a[9]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_bvd1
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_bvd2
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_cd1_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_ce1_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_ce2_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[0]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[10]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[11]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[12]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[13]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[14]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[15]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[1]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[2]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[3]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[4]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[5]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[6]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[7]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[8]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_d[9]
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_inpack_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_iord_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_iowr_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_oe_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_rdy
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_reg_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_wait_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_we_n
+set_instance_assignment -name SLOW_SLEW_RATE ON -to cf_wp
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to enet_iochrdy
+
+# end ENTITY(abc80)
+# -----------------
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VERILOG_FILE mega/sdram.v
+set_global_assignment -name MIF_FILE data/sdram.mif
+set_global_assignment -name VERILOG_FILE sddisk.v
+set_global_assignment -name VERILOG_FILE sound.v
+set_global_assignment -name VHDL_FILE t80/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE t80/T80.vhd
+set_global_assignment -name VHDL_FILE t80/T80s.vhd
+set_global_assignment -name VHDL_FILE t80/T80se.vhd
+set_global_assignment -name MIF_FILE data/basic80.mif
+set_global_assignment -name MIF_FILE data/videoram.mif
+set_global_assignment -name MIF_FILE data/abcdos.mif
+set_global_assignment -name MIF_FILE data/chargen.mif
+set_global_assignment -name MIF_FILE data/keyboard.mif
+set_global_assignment -name MIF_FILE data/mmu.mif
+set_global_assignment -name MIF_FILE data/abcbasic.mif
+set_global_assignment -name VERILOG_FILE mega/chargen.v
+set_global_assignment -name VERILOG_FILE mega/pll1.v
+set_global_assignment -name VERILOG_FILE mega/pll2.v
+set_global_assignment -name VERILOG_FILE mega/basic80.v
+set_global_assignment -name VERILOG_FILE mega/basicrom.v
+set_global_assignment -name VERILOG_FILE mega/mmuram.v
+set_global_assignment -name VERILOG_FILE mega/dosrom.v
+set_global_assignment -name VERILOG_FILE mega/printerrom.v
+set_global_assignment -name VERILOG_FILE mega/videoram.v
+set_global_assignment -name VERILOG_FILE mega/kbdram.v
+set_global_assignment -name VERILOG_FILE t80pio/t80pio.v
+set_global_assignment -name VERILOG_FILE debounce.v
+set_global_assignment -name VERILOG_FILE display.v
+set_global_assignment -name VERILOG_FILE printer.v
+set_global_assignment -name VERILOG_FILE keyboard.v
+set_global_assignment -name VERILOG_FILE hexled.v
+set_global_assignment -name VERILOG_FILE hexascii.v
+set_global_assignment -name VERILOG_FILE abc80.v
+set_global_assignment -name QIP_FILE mega/pll1.qip
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS PROGRAMMING PIN"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name QIP_FILE mega/mmuram.qip
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clock_50
+set_instance_assignment -name CLOCK_SETTINGS clock_50 -to clock_50
+set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id clock_27
+set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[0]
+set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[1]
+set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id clock_24
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1] \ No newline at end of file
diff --git a/abc80.v b/abc80.v
index df44609..d68180d 100644..100755
--- a/abc80.v
+++ b/abc80.v
@@ -1,6 +1,6 @@
// -----------------------------------------------------------------------
//
-// Copyright 2003-2005 H. Peter Anvin - All Rights Reserved
+// Copyright 2003-2008 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -9,7 +9,6 @@
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
-// "$Id$"
//
// abc80.v
@@ -26,153 +25,65 @@
`define RESET_WIDTH 1
module abc80 (
- clkin, // PLL1 input clock (50 MHz)
- pld_clkout, // Clock output to I/O devices
- pld_clkfb, // Feedback from pld_clkout to PLL2
- reset_n, // Reset button
- ps2_sel, // PS/2 port input/output select
- ps2_kclk, // PS/2 keyboard clock
- ps2_kdata, // PS/2 keyboard data
- ps2_mclk, // PS/2 mouse clock
- ps2_mdata, // PS/2 mouse data
- led, // Debugging LEDs
- s7_0, s7_1, // Debugging 7-segment LEDs
- sw, // Pushbutton switches
- fse_a, // Mainboard common bus address
- fse_d, // Mainboard common bus data
- flash_cs_n, // Flash ROM CS#
- enet_aen, // Ethernet Access Enable
- enet_ads_n, // Ethernet Address Strobe
- enet_be_n, // Ethernet byte enables
- enet_cycle_n, // Ethernet EISA burst mode cycle
- enet_datacs_n, // Ethernet data chip select
- enet_intrq0, // Ethernet interrupt request
- enet_iochrdy, // Ethernet async ready (ARDY)
- enet_ior_n, // Ethernet async IO read (OE#)
- enet_iow_n, // Ethernet async IO write (WE#)
- enet_lclk, // Ethernet synchronous clock
- enet_ldev_n, // Ethernet selected output
- enet_rdyrtn_n, // Ethernet ready return
- enet_w_r_n, // Ethernet sync IO W/R#
- sram_be_n, // SRAM byte enables
- sram_cs_n, // SRAM CS#
- sram_oe_n, // SRAM OE#
- sram_we_n, // SRAM WE#
- ttya_dcd, // V.24 DCD#
- ttya_txd, // V.24 TxD
- ttya_rxd, // V.24 RxD
- ttya_dtr, // V.24 DTR#
- ttya_dsr, // V.24 DSR#
- ttya_rts, // V.24 RTS#
- ttya_cts, // V.24 CTS#
- ttya_ri, // V.24 RI#
- ttyb_txd, // Debug port TxD
- vga_r, // VGA red
- vga_g, // VGA green
- vga_b, // VGA blue
- vga_hs, // VGA horz sync
- vga_vs, // VGA vert sync
- vga_blank_n, // VGA DAC force blank
- vga_sync_n, // VGA sync enable
- vga_sync_t, // VGA sync on R/G/B
- vga_m1, // VGA color space config
- vga_m2, // VGA color space config
- cf_power, // CompactFlash power enable
- cf_a, // CompactFlash address bus
- cf_d, // CompactFlash data bus
- cf_rdy, // CompactFlash RDY
- cf_wait_n, // CompactFlash WAIT#
- cf_ce1_n, // CompactFlash CE1#
- cf_ce2_n, // CompactFlash CE2#
- cf_oe_n, // CompactFlash OE#
- cf_we_n, // CompactFlash WE#
- cf_reg_n, // CompactFlash REG#
- cf_iord_n, // CompactFlash IORD#
- cf_iowr_n, // CompactFlash IOWR#
- cf_cd1_n, // CompactFlash card detect
- audio_l, // Audio left
- audio_r, // Audio right
- p1_a28, // Proto1 (J11) pin 28
- p1_a29, // Proto1 (J11) pin 29
- p1_a38, // Proto1 (J11) pin 38
+ input clock_50, // 50 MHz clock
+ input [1:0] clock_24, // 24 MHz clock (on two pins)
+ input [1:0] clock_27, // 27 MHz clock (on two pins)
+ input ext_clock, // External clock input
+
+ output ps2_clk, // PS/2 keyboard clock
+ inout ps2_dat, // PS/2 keyboard data
+
+ output [7:0] ledr, // Red LEDs
+ output [9:0] ledg, // Green LEDs
+ output [6:0] s7_0, // 7-segment LEDs
+ output [6:0] s7_1, // 7-segment LEDs
+ output [6:0] s7_2, // 7-segment LEDs
+ output [6:0] s7_3, // 7-segment LEDs
+
+ input [3:0] key_n, // Pushbutton switches
+ input [9:0] sw, // Slide switches
+
+ output fl_rst_n, // Flash ROM RST#
+ output fl_oe_n, // Flash ROM OE#
+ output fl_we_n, // Flash ROM WE#
+ output [21:0] fl_a, // Flash ROM address bus
+ inout [7:0] fl_dq, // Flash ROM data bus
+
+ output [1:0] dram_ba, // SDRAM bank selects
+ output dram_ras_n, // SDRAM RAS#
+ output dram_cas_n, // SDRAM CAS#
+ output dram_cke, // SDRAM clock enable
+ output dram_clk, // SDRAM clock
+ output dram_cs_n, // SDRAM CS#
+ output dram_we_n, // SDRAM WE#
+ output [1:0] dram_dqm, // SDRAM DQM (per byte)
+ output [11:0] dram_a, // SDRAM address bus
+ inout [15:0] dram_dq, // SDRAM data bus
+
+ output sram_ce_n, // SRAM CE#
+ output sram_oe_n, // SRAM OE#
+ output sram_we_n, // SRAM WE#
+ output [1:0] sram_be_n, // SRAM LB#, UB#
+ output [17:0] sram_a, // SRAM address bus
+ inout [15:0] sram_dq, // SRAM data bus
+
+ output sd_clk, // SD card clock
+ inout sd_cmd, // SD card DI/MOSI/CMD
+ inout sd_dat0, // SD card SO/MISO/DAT0
+ inout sd_dat3, // SD card CS#/CD/DAT3
+
+ output uart_txd, // RS232 port TxD
+ input uart_rxd, // RS232 port RxD
+
+ output [3:0] vga_r, // VGA red
+ output [3:0] vga_g, // VGA green
+ output [3:0] vga_b, // VGA blue
+ output vga_hs, // VGA horz sync
+ output vga_vs, // VGA vert sync
+
+ inout [35:0] gpio_0, // GPIO headers
+ inout [35:0] gpio_1 // GPIO headers
);
-
- input clkin;
- output pld_clkout;
- input pld_clkfb;
- input reset_n;
- output ps2_sel;
- inout ps2_kclk;
- inout ps2_kdata;
- inout ps2_mclk;
- inout ps2_mdata;
- input [3:0] sw;
- output [7:0] led;
- output [7:0] s7_0;
- output [7:0] s7_1;
- output [22:0] fse_a;
- inout [31:0] fse_d;
- output flash_cs_n;
- output enet_aen;
- output enet_ads_n;
- output [3:0] enet_be_n;
- output enet_cycle_n;
- output enet_datacs_n;
- input enet_intrq0;
- input enet_iochrdy;
- output enet_ior_n;
- output enet_iow_n;
- output enet_lclk;
- input enet_ldev_n;
- output enet_rdyrtn_n;
- output enet_w_r_n;
- output [3:0] sram_be_n;
- output sram_cs_n;
- output sram_oe_n;
- output sram_we_n;
- output ttya_dcd; // DTE DTR
- output ttya_txd;
- input ttya_rxd;
- input ttya_dtr; // DTE DCD
- output ttya_dsr;
- input ttya_rts; // DTE CTS
- output ttya_cts; // DTE RTS
- output ttya_ri;
- output ttyb_txd;
- output [7:0] vga_r;
- output [7:0] vga_g;
- output [7:0] vga_b;
- output vga_hs;
- output vga_vs;
- output vga_blank_n;
- output vga_sync_n;
- output vga_sync_t;
- output vga_m1;
- output vga_m2;
- output cf_power;
- output [10:0] cf_a;
- inout [15:0] cf_d;
- input cf_rdy;
- input cf_wait_n;
- output cf_ce1_n;
- output cf_ce2_n;
- output cf_oe_n;
- output cf_we_n;
- output cf_reg_n;
- output cf_iord_n;
- output cf_iowr_n;
- input cf_cd1_n;
- output audio_l;
- output audio_r;
- output p1_a29;
- output p1_a28;
- input p1_a38;
-
- // ------------------------------------------------------------------------
- // Reset
- // (there is option for extending the reset internally here, if necessary)
- // ------------------------------------------------------------------------
- wire rst_n = reset_n;
// ------------------------------------------------------------------------
// PLLs and clock distribution
@@ -181,24 +92,22 @@ module abc80 (
wire cpu_clk; // 25 MHz
wire video_clk; // 25 MHz = screen pixel rate
wire fast_clk; // 100 MHz
- wire cpu_clk_d;
pll1 pll1 (
- .inclk0 ( clkin ), // 50 MHz input clock
- .c0 ( fast_clk ), // x2/1 = 100 MHz output clock
- .c1 ( cpu_clk_d ), // x1/2 = 25 MHz output clock
- .e0 ( pld_clkout ) // External only output x1/2 = 25 MHz
- );
-
- assign cpu_clk = cpu_clk_d;
-
- // pld_clkfb is pld_clkout routed externally through a zero-skew buffer
- pll2 pll2 (
- .inclk0 ( pld_clkfb ), // 25 MHz input clock
- .c0 ( video_clk )
+ .inclk0 ( clock_50 ), // 50 MHz input clock
+ .c0 ( fast_clk ), // x2/1 = 100 MHz output clock
+ .c1 ( cpu_clk ), // x1/2 = 25 MHz output clock
+ .c2 ( video_clk ) // x1/2 = 25 MHz pixel clock
);
// ------------------------------------------------------------------------
+ // Reset
+ // ------------------------------------------------------------------------
+ reg rst_n = 1'b0;
+ always @(posedge cpu_clk)
+ rst_n <= 1'b1;
+
+ // ------------------------------------------------------------------------
// Standard LEDs (here so that we can switch around the LEDs more easily
// for quick debugging.)
// ------------------------------------------------------------------------
@@ -211,23 +120,28 @@ module abc80 (
reg [7:0] prog_s7_0;
reg [1:0] prog_led_ctl;
- assign led = prog_led_ctl[1] ? prog_led : std_led;
- assign s7_1 = prog_led_ctl[0] ? ~prog_s7_1 : ~std_s7_1;
- assign s7_0 = prog_led_ctl[0] ? ~prog_s7_0 : ~std_s7_0;
+ assign ledr = std_led;
+ assign ledg = { 2'b00, prog_led };
+
+ assign s7_3 = prog_s7_1[6:0];
+ assign s7_2 = prog_s7_0[6:0];
+ assign s7_1 = std_s7_1[6:0];
+ assign s7_0 = std_s7_0[6:0];
// ------------------------------------------------------------------------
// Timers
// ------------------------------------------------------------------------
// ABC80 has two interrupt-capable timers: one at 128 us (7812.5 Hz) and
- // one at 20 ms (50 Hz). This is assuming a 12 MHz crystal, which the real
- // ABC80 didn't have -- it had 11.9808 MHz, but everyone treated it as
- // 12 MHz (0.16% error). We have a 50 MHz crystal; cpu_clk is already
+ // one at 20 ms (50 Hz). The 128 us clock was slightly off, since
+ // the real ABC80 had 11.9808 MHz and not 12 MHz for its crystal
+ // (the 50 Hz clock was exact), but everyone treated it as 128 us
+ // (0.16% error). We have a 50 MHz crystal; cpu_clk is already
// divided by 2 to obtain 25 MHz (40 ns); we then divide it by 400 to
// obtain a 16 us clock, which then is divided by 8 for 128 us and by
// 625*2 for the 50 Hz clock. Note the last stage is always divide by 2,
// so we get 50% duty cycle. I'm so anal-retentive.
-
+
reg [8:0] clk_div0; // 16 us counter
reg [2:0] clk_div1; // 128 us counter
reg [9:0] clk_div2; // 10 ms counter
@@ -302,10 +216,10 @@ module abc80 (
.clkin ( cpu_clk ),
.reset_n ( rst_n ),
.ps2_sel ( ps2_sel ),
- .ps2_kclk ( ps2_kclk ),
- .ps2_kdata ( ps2_kdata ),
- .ps2_mclk ( ps2_mclk ),
- .ps2_mdata ( ps2_mdata ),
+ .ps2_kclk ( ps2_clk ),
+ .ps2_kdata ( ps2_dta ),
+ .ps2_mclk ( ),
+ .ps2_mdata ( ),
.kb_data ( kb_data ),
.kb_stat ( kb_stat )
);
@@ -349,8 +263,8 @@ module abc80 (
display video (
.clk ( video_clk ),
- .width ( video_width ^ ~sw[1] ),
- .reveal ( ~sw[0] ),
+ .width ( video_width ^ ~key_n[1] ),
+ .reveal ( ~key_n[0] ),
.a ( video_a ),
.d ( video_d ),
.ga ( chargen_a ),
@@ -360,99 +274,32 @@ module abc80 (
.hsync ( vga_hs )
);
- assign vga_r = { rgb[5:4],rgb[5:4],rgb[5:4],rgb[5:4] };
- assign vga_g = { rgb[3:2],rgb[3:2],rgb[3:2],rgb[3:2] };
- assign vga_b = { rgb[1:0],rgb[1:0],rgb[1:0],rgb[1:0] };
+ // This is ugly as hell. Fix this.
+ assign vga_r = { rgb[5:4],rgb[5:4] };
+ assign vga_g = { rgb[3:2],rgb[3:2] };
+ assign vga_b = { rgb[1:0],rgb[1:0] };
- assign vga_blank_n = 1;
- assign vga_sync_n = 1;
- assign vga_sync_t = 0; // Not sync on R/G/B
- assign vga_m1 = 0; // RGB color mode
- assign vga_m2 = 0; // RGB color mode
-
// ------------------------------------------------------------------------
- // External SRAM and Ethernet (common bus)
- // FIX: Need to connect enet_iochrdy (ARDY)
+ // External SRAM
// ------------------------------------------------------------------------
- // Ethernet ABC-bus select logic
- // Note: This is a bit more awkward than it should be, because in a real
- // hardware system the memory and the Ethernet controller wouldn't be
- // sharing a bus.
-
- reg enet_selected = 0;
- reg [3:0] enet_address;
- parameter enet_select_code = 6'd25;
-
- always @(negedge rst_n or posedge cpu_clk)
- begin
- if ( ~rst_n )
- enet_selected <= 0;
- else
- begin
- if ( ~abc_in_n[7] )
- enet_selected <= 0;
- else if ( ~abc_out_n[1] )
- enet_selected <= ( cpu_do[5:0] == enet_select_code );
- end
- end // always @ (negedge rst_n or posedge cpu_clk)
-
- always @(negedge rst_n or posedge cpu_clk)
- begin
- if ( ~rst_n )
- enet_address <= ~0;
- else
- begin
- if ( ~abc_in_n[7] )
- enet_address <= ~0;
- else if ( enet_selected & ~abc_out_n[2] )
- enet_address <= cpu_do[6:3];
- end
- end // always @ (negedge rst_n or posedge cpu_clk)
-
-
- reg [7:0] sram_do; // Data out from sram
- wire sram_oe_w;
- wire sram_we_w;
- reg sram_we_q1;
- reg sram_we_q2;
+ wire [7:0] sram_do; // Data out from sram
+ wire sram_oe_w;
+ wire sram_we_w;
+ reg sram_we_q1;
+ reg sram_we_q2;
- reg [7:0] enet_do; // Data out from Ethernet
- wire enet_oe_w;
- wire enet_we_w;
- reg enet_oe_q;
- reg enet_we_q1;
- reg enet_we_q2;
- reg enet_we_q3;
-
- assign flash_cs_n = 1; // Disable flash ROM
- assign sram_cs_n = 0; // Enable SRAM
- assign enet_aen = 0; // Enable Ethernet
+ assign fl_ce_n = 1'b1; // Disable flash ROM
+ assign sram_ce_n = 1'b1; // Enable SRAM
assign sram_oe_w = msel[0] & ~cpu_rd_n;
assign sram_we_w = msel[0] & ~cpu_wr_n;
- assign enet_oe_w = enet_selected & ~abc_in_n[0];
- assign enet_we_w = enet_selected & (~abc_out_n[0] | ~abc_out_n[2]);
-
- wire enet_addr_w = enet_oe_w | enet_we_w;
- reg enet_ads_q1;
- reg enet_ads_q2;
-
- assign enet_ads_n = enet_ads_q1;
-
always @(negedge rst_n or posedge fast_clk)
if ( ~rst_n )
begin
sram_we_q1 <= 0;
sram_we_q2 <= 0;
-
- enet_ads_q1 <= 0;
- enet_ads_q2 <= 0;
- enet_oe_q <= 0;
- enet_we_q1 <= 0;
- enet_we_q2 <= 0;
- enet_we_q3 <= 0;
end // if ( ~rst_n )
else
begin
@@ -460,78 +307,19 @@ module abc80 (
// doesn't latch data late
sram_we_q1 <= sram_we_w;
sram_we_q2 <= sram_we_q1;
-
- if ( enet_iochrdy )
- begin
- enet_ads_q1 <= enet_addr_w;
- enet_ads_q2 <= enet_ads_q1;
-
- enet_oe_q <= enet_oe_w;
- enet_we_q1 <= enet_we_w;
- enet_we_q2 <= enet_we_q1;
- enet_we_q3 <= enet_we_q2;
- end
end // else: !if( ~rst_n )
// Driving output pins...
- // Note: The SRAM is connected to FSE_A[19:2] only.
- // Note: For the Ethernet chip we use ADS# to latch the address, to
- // make sure we don't miss setup for the next SRAM cycle.
- assign fse_a = (~enet_ads_q2 & enet_selected & ~abc_out_n[0] | ~abc_in_n[0]) ?
- { 19'h00030, enet_address[3:1], 1'b0 } :
- (~enet_ads_q2 & enet_selected & ~abc_out_n[2]) ?
- { 19'h00030, 4'b1110 } :
- { 3'b000, mmu_a[19:2], 2'b00 };
-
- assign sram_be_n =
- (mmu_a[1:0] == 2'h0) ? ~4'b0001 :
- (mmu_a[1:0] == 2'h1) ? ~4'b0010 :
- (mmu_a[1:0] == 2'h2) ? ~4'b0100 :
- /* (mmu_a[1:0] == 2'h3) ? */ ~4'b1000;
-
- assign enet_be_n =
- ~abc_out_n[2] ? ~4'b0001 :
- (enet_address[0] == 1'b0) ? ~4'b0001 :
- /* (enet_address[0] == 1'h1) ? */ ~4'b0010;
+ assign sram_a = mmu_a[18:1];
+ assign sram_be_n = mmu_a[0] ? ~2'b10 : ~2'b01;
assign sram_oe_n = ~sram_oe_w;
assign sram_we_n = ~(sram_we_w & ~sram_we_q2);
- assign enet_ior_n = ~enet_oe_q;
- assign enet_iow_n = ~(enet_we_q1 & ~enet_we_q3);
-
- assign fse_d = (sram_we_w|enet_we_w) ? { cpu_do, cpu_do, cpu_do, cpu_do } : 32'bz;
+ assign sram_dq = sram_we_w ? { cpu_do, cpu_do } : 16'bz;
// SRAM Input side MUX
- always @(*)
- case ( mmu_a[1:0] )
- 2'h0:
- sram_do = fse_d[7:0];
- 2'h1:
- sram_do = fse_d[15:8];
- 2'h2:
- sram_do = fse_d[23:16];
- 2'h3:
- sram_do = fse_d[31:24];
- endcase // case( mmu_a[1:0] )
-
- assign enet_cycle_n = 1; // Don't use EISA burst mode
- assign enet_rdyrtn_n = 1; // Not using synchronous bursting
- assign enet_datacs_n = 1; // Not using synchronous bursting
- assign enet_lclk = 1; // Synchronous clock (unused)
- assign enet_w_r_n = 1; // Unused
-
- // Ethernet input side MUX
- always @(posedge fast_clk)
- if ( enet_oe_w )
- case ( enet_address[0] )
- 1'b0:
- enet_do <= fse_d[7:0];
- 1'b1:
- enet_do <= fse_d[15:8];
- endcase // case( enet_address[0] )
- else
- enet_do <= ~0;
+ assign sram_do = mmu_a[0] ? sram_dq[15:8] : sram_dq[7:0];
// ------------------------------------------------------------------------
// Internal ROMs
@@ -598,9 +386,9 @@ module abc80 (
.address_a ( { mmu_map, cpu_a[15:8] } ),
.data_a ( 16'bx ), // Never written
.q_a ( mmu_q ),
- .wren_a ( 0 ),
- .address_b ( mmu_mod_addr ),
- .data_b ( { cpu_do, mmu_mod_data } ),
+ .wren_a ( 1'b0 ),
+ .address_b ( mmu_mod_addr[9:0] ),
+ .data_b ( { cpu_do, mmu_mod_data[7:0] } ),
.q_b ( mmu_rd_data ),
.wren_b ( mmu_wr_e ),
.clock ( fast_clk )
@@ -702,9 +490,9 @@ module abc80 (
// Map the cassette port to some of the very few unclaimed (by the
// CF card) pins on Prototype Connector 1.
- assign p1_a29 = cas_relay;
- assign p1_a28 = cas_output;
- assign cas_input = p1_a38;
+ //assign p1_a29 = cas_relay;
+ //assign p1_a28 = cas_output;
+ //assign cas_input = p1_a38;
assign std_led[3] = cas_relay;
assign std_led[4] = cas_output;
@@ -746,29 +534,22 @@ module abc80 (
abc_in_n = ~8'h00;
end // always @ (*)
- // CompactFlash controller
- wire [7:0] abc_cf_di;
- wire cf_select;
- wire cf_active;
+ // SD card controller
+ wire [7:0] abc_sd_di;
+ wire sd_select;
+ wire sd_active;
- cfcontroller cfcontroller (
- .reset_n ( reset_n ),
+ sdcontroller sdcontroller (
+ .reset_n ( rst_n ),
.clk ( cpu_clk ),
- .cf_power ( cf_power ),
- .cf_a ( cf_a ),
- .cf_d ( cf_d ),
- .cf_rdy ( cf_rdy ),
- .cf_wait_n ( cf_wait_n ),
- .cf_ce1_n ( cf_ce1_n ),
- .cf_ce2_n ( cf_ce2_n ),
- .cf_oe_n ( cf_oe_n ),
- .cf_we_n ( cf_we_n ),
- .cf_reg_n ( cf_reg_n ),
- .cf_iord_n ( cf_iord_n ),
- .cf_iowr_n ( cf_iowr_n ),
- .cf_cd1_n ( cf_cd1_n ),
+
+ .sd_cs_n ( sd_dat3 ),
+ .sd_di ( sd_cmd ),
+ .sd_clk ( sd_clk ),
+ .sd_do ( sd_dat0 ),
+
.abc_do ( cpu_do ),
- .abc_di ( abc_cf_di ),
+ .abc_di ( abc_sd_di ),
.abc_out_n ( abc_out_n[0] ),
.abc_cs_n ( abc_out_n[1] ),
.abc_c1_n ( abc_out_n[2] ),
@@ -778,8 +559,9 @@ module abc80 (
.abc_inp_n ( abc_in_n[0] ),
.abc_status_n ( abc_in_n[1] ),
.abc_rst_n ( abc_in_n[7] ),
- .select ( cf_select ),
- .active ( cf_active )
+
+ .select ( sd_select ),
+ .active ( sd_active )
);
// Printer controller
@@ -806,21 +588,21 @@ module abc80 (
// The terminology gets a bit funny there. abc_do means data from
// the ABC-bus to the main CPU.
- wire [7:0] abc_do = abc_cf_di & abc_pr_di & enet_do;
+ wire [7:0] abc_do = abc_sd_di & abc_pr_di;
// Closest thing we get to a disk LED
- reg cf_active_led;
+ reg sd_active_led;
- assign std_led[0] = cf_active_led;
- assign std_led[1] = cf_select;
- assign std_led[2] = ~cf_cd1_n;
+ assign std_led[0] = sd_active_led;
+ assign std_led[1] = sd_select;
+ assign std_led[2] = 1'b0; // Do something interesting here...
// Make sure the activity light stays on long enough to see it
- always @(posedge cf_active or posedge ctr_20ms)
- if ( cf_active )
- cf_active_led <= 1'b1;
+ always @(posedge sd_active or posedge ctr_20ms)
+ if ( sd_active )
+ sd_active_led <= 1'b1;
else
- cf_active_led <= 1'b0;
+ sd_active_led <= 1'b0;
// Video width control INP 4 = 80, INP 3 = 40
always @(negedge reset_n or posedge cpu_clk)
@@ -957,17 +739,17 @@ module abc80 (
end
end
- // Turbo control: sw3 = toggle turbo
- wire sw3_debounced;
- wire sw3_strobe;
+ // Turbo control: key_n3 = toggle turbo
+ wire key_n3_debounced;
+ wire key_n3_strobe;
reg [1:0] cpu_turbo;
- debounce sw3_debounce (
+ debounce key_n3_debounce (
.clk ( cpu_clk ),
.reset_n ( rst_n ),
- .in ( ~sw[3] ),
- .out ( sw3_debounced ),
- .strobe ( sw3_strobe )
+ .in ( ~key_n[3] ),
+ .out ( key_n3_debounced ),
+ .strobe ( key_n3_strobe )
);
// This needs to operate in the cpu_clk domain, so use the
@@ -981,7 +763,7 @@ module abc80 (
begin
if ( turbo_set )
cpu_turbo <= cpu_do[1:0];
- else if ( sw3_strobe & sw3_debounced )
+ else if ( key_n3_strobe & key_n3_debounced )
cpu_turbo <= cpu_turbo - 1;
end
end
@@ -1068,9 +850,8 @@ module abc80 (
endcase // case( cpu_turbo )
end // always @ (posedge cpu_clk)
- assign cpu_clk_en = &(cpu_slow_ctr[2:0] | cpu_slow_mask)
- & ~(enet_selected & ~enet_iochrdy);
-
+ assign cpu_clk_en = &(cpu_slow_ctr[2:0] | cpu_slow_mask);
+
assign std_led[7:5] = cpu_slow_mask;
always @(*)
diff --git a/data/Makefile b/data/Makefile
index a80170f..a8d6da6 100644
--- a/data/Makefile
+++ b/data/Makefile
@@ -1,4 +1,5 @@
-BIN2MIF = ./bin2mif.pl
+PERL = perl
+BIN2MIF = bin2mif.pl
Z80ASM = ../tools/z80asm/z80asm
.SUFFIXES: .bdf .asm .obj .bin .mif .bas
@@ -7,55 +8,55 @@ Z80ASM = ../tools/z80asm/z80asm
$(Z80ASM) -o $@ -l $*.lst $<
all : keyboard.mif abcbasic.mif basic80.mif abcdos.mif \
- mmu.mif chargen.mif videoram.mif cfram.mif printer.mif \
+ mmu.mif chargen.mif videoram.mif sdram.mif printer.mif \
abcsefi.bas abcdkno.bas abcintl.bas
keyboard.mif : keyboard.bin $(BIN2MIF)
- $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
basic80.mif : munge_basic.pl
- ./munge_basic.pl || ( rm -f $@ ; exit 1 )
+ $(PERL) munge_basic.pl || ( rm -f $@ ; exit 1 )
abcbasic.mif : abcbasic.rom $(BIN2MIF)
- $(BIN2MIF) 16384 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 16384 8 < $< > $@ || ( rm -f $@ ; exit 1 )
abcdos.mif : ufddos.rom $(BIN2MIF)
- $(BIN2MIF) 4096 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 4096 8 < $< > $@ || ( rm -f $@ ; exit 1 )
videoram.mif : videoram.bin $(BIN2MIF)
- $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-cfram.mif : cfram.bin $(BIN2MIF)
- $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+sdram.mif : sdram.bin $(BIN2MIF)
+ $(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
printer.mif : printer.bin $(BIN2MIF)
- $(BIN2MIF) 512 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 512 8 < $< > $@ || ( rm -f $@ ; exit 1 )
mmu.mif : mmuinit.pl
- ./mmuinit.pl > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) mmuinit.pl > $@ || ( rm -f $@ ; exit 1 )
FONT = 8x16-abc-l1.bdf
CHARSET = abcsefi
chargen.bin : $(FONT) bdf2bin.pl
- ./bdf2bin.pl $(CHARSET) < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) bdf2bin.pl $(CHARSET) < $< > $@ || ( rm -f $@ ; exit 1 )
chargen.mif : chargen.bin $(BIN2MIF)
- $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
videoram.bin: video.txt genvideo.pl
- ./genvideo.pl -40 < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) genvideo.pl -40 < $< > $@ || ( rm -f $@ ; exit 1 )
clean:
rm -f *.obj *.bin *.mif *.bas
.bin.bas:
- ./bin2poke $< 16384 100 RETURN | cat charpoke.bah - > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) bin2poke $< 16384 100 RETURN | cat charpoke.bah - > $@ || ( rm -f $@ ; exit 1 )
abcsefi.bin : $(FONT) bdf2bin.pl
- ./bdf2bin.pl abcsefi < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) bdf2bin.pl abcsefi < $< > $@ || ( rm -f $@ ; exit 1 )
abcdkno.bin : $(FONT) bdf2bin.pl
- ./bdf2bin.pl abcdkno < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) bdf2bin.pl abcdkno < $< > $@ || ( rm -f $@ ; exit 1 )
abcintl.bin : $(FONT) bdf2bin.pl
- ./bdf2bin.pl abcintl < $< > $@ || ( rm -f $@ ; exit 1 )
+ $(PERL) bdf2bin.pl abcintl < $< > $@ || ( rm -f $@ ; exit 1 )
diff --git a/data/cfram.asm b/data/sdram.asm
index 4a228e7..f703e14 100644
--- a/data/cfram.asm
+++ b/data/sdram.asm
@@ -33,7 +33,7 @@ interrupt:
idle:
ld e,0
-idle_err: ; Errcode in A
+idle_err: ; Errcode in E
ei ; Allow interrupts
; Prepare to receive command
diff --git a/mega/cfram.bsf b/mega/cfram.bsf
deleted file mode 100755
index a896a58..0000000
--- a/mega/cfram.bsf
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2004 Altera Corporation
-Any megafunction design, and related netlist (encrypted or decrypted),
-support information, device programming or simulation file, and any other
-associated documentation or information provided by Altera or a partner
-under Altera's Megafunction Partnership Program may be used only
-to program PLD devices (but not masked PLD devices) from Altera. Any
-other use of such megafunction design, netlist, support information,
-device programming or simulation file, or any other related documentation
-or information is prohibited for any other purpose, including, but not
-limited to modification, reverse engineering, de-compiling, or use with
-any other silicon devices, unless such use is explicitly licensed under
-a separate agreement with Altera or a megafunction partner. Title to the
-intellectual property, including patents, copyrights, trademarks, trade
-secrets, or maskworks, embodied in any such megafunction design, netlist,
-support information, device programming or simulation file, or any other
-related documentation or information provided by Altera or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 256 192)
- (text "cfram" (rect 112 1 149 17)(font "Arial" (font_size 10)))
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diff --git a/mega/mmuram.bsf b/mega/mmuram.bsf
index 6ed2410..fa5c183 100644
--- a/mega/mmuram.bsf
+++ b/mega/mmuram.bsf
@@ -1,170 +1,164 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2003 Altera Corporation
-Any megafunction design, and related netlist (encrypted or decrypted),
-support information, device programming or simulation file, and any other
-associated documentation or information provided by Altera or a partner
-under Altera's Megafunction Partnership Program may be used only
-to program PLD devices (but not masked PLD devices) from Altera. Any
-other use of such megafunction design, netlist, support information,
-device programming or simulation file, or any other related documentation
-or information is prohibited for any other purpose, including, but not
-limited to modification, reverse engineering, de-compiling, or use with
-any other silicon devices, unless such use is explicitly licensed under
-a separate agreement with Altera or a megafunction partner. Title to the
-intellectual property, including patents, copyrights, trademarks, trade
-secrets, or maskworks, embodied in any such megafunction design, netlist,
-support information, device programming or simulation file, or any other
-related documentation or information provided by Altera or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 256 192)
- (text "mmuram" (rect 103 1 163 17)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 176 25 188)(font "Arial" ))
- (port
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- (text "data_a[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
- (text "data_a[15..0]" (rect 4 19 67 32)(font "Arial" (font_size 8)))
- (line (pt 0 32)(pt 112 32)(line_width 3))
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- (line (pt 112 91)(pt 120 91)(line_width 1))
- (line (pt 120 91)(pt 120 103)(line_width 1))
- (line (pt 120 103)(pt 112 103)(line_width 1))
- (line (pt 112 103)(pt 112 91)(line_width 1))
- (line (pt 112 98)(pt 114 100)(line_width 1))
- (line (pt 114 100)(pt 112 102)(line_width 1))
- (line (pt 104 100)(pt 112 100)(line_width 1))
- (line (pt 120 96)(pt 128 96)(line_width 3))
- (line (pt 112 107)(pt 120 107)(line_width 1))
- (line (pt 120 107)(pt 120 119)(line_width 1))
- (line (pt 120 119)(pt 112 119)(line_width 1))
- (line (pt 112 119)(pt 112 107)(line_width 1))
- (line (pt 112 114)(pt 114 116)(line_width 1))
- (line (pt 114 116)(pt 112 118)(line_width 1))
- (line (pt 104 116)(pt 112 116)(line_width 1))
- (line (pt 120 112)(pt 128 112)(line_width 3))
- (line (pt 112 123)(pt 120 123)(line_width 1))
- (line (pt 120 123)(pt 120 135)(line_width 1))
- (line (pt 120 135)(pt 112 135)(line_width 1))
- (line (pt 112 135)(pt 112 123)(line_width 1))
- (line (pt 112 130)(pt 114 132)(line_width 1))
- (line (pt 114 132)(pt 112 134)(line_width 1))
- (line (pt 104 132)(pt 112 132)(line_width 1))
- (line (pt 120 128)(pt 128 128)(line_width 1))
- (line (pt 104 36)(pt 104 161)(line_width 1))
- (line (pt 176 36)(pt 176 161)(line_width 1))
- (line (pt 184 27)(pt 192 27)(line_width 1))
- (line (pt 192 27)(pt 192 39)(line_width 1))
- (line (pt 192 39)(pt 184 39)(line_width 1))
- (line (pt 184 39)(pt 184 27)(line_width 1))
- (line (pt 184 34)(pt 186 36)(line_width 1))
- (line (pt 186 36)(pt 184 38)(line_width 1))
- (line (pt 176 36)(pt 184 36)(line_width 1))
- (line (pt 168 32)(pt 184 32)(line_width 3))
- (line (pt 184 91)(pt 192 91)(line_width 1))
- (line (pt 192 91)(pt 192 103)(line_width 1))
- (line (pt 192 103)(pt 184 103)(line_width 1))
- (line (pt 184 103)(pt 184 91)(line_width 1))
- (line (pt 184 98)(pt 186 100)(line_width 1))
- (line (pt 186 100)(pt 184 102)(line_width 1))
- (line (pt 176 100)(pt 184 100)(line_width 1))
- (line (pt 168 96)(pt 184 96)(line_width 3))
- )
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 256 192)
+ (text "mmuram" (rect 103 1 163 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 176 25 188)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data_a[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+ (text "data_a[15..0]" (rect 4 19 67 32)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 112 32)(line_width 3))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+ (text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+ (line (pt 0 48)(pt 112 48)(line_width 3))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+ (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 112 64)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "data_b[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+ (text "data_b[15..0]" (rect 4 83 67 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 112 96)(line_width 3))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+ (text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+ (line (pt 0 112)(pt 112 112)(line_width 3))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+ (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+ (line (pt 0 128)(pt 112 128)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 147 27 160)(font "Arial" (font_size 8)))
+ (line (pt 0 160)(pt 176 160)(line_width 1))
+ )
+ (port
+ (pt 256 32)
+ (output)
+ (text "q_a[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+ (text "q_a[15..0]" (rect 205 19 253 32)(font "Arial" (font_size 8)))
+ (line (pt 256 32)(pt 192 32)(line_width 3))
+ )
+ (port
+ (pt 256 96)
+ (output)
+ (text "q_b[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+ (text "q_b[15..0]" (rect 205 83 253 96)(font "Arial" (font_size 8)))
+ (line (pt 256 96)(pt 192 96)(line_width 3))
+ )
+ (drawing
+ (text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
+ (text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+ (text "Block Type: AUTO" (rect 41 172 119 184)(font "Arial" ))
+ (line (pt 128 24)(pt 168 24)(line_width 1))
+ (line (pt 168 24)(pt 168 144)(line_width 1))
+ (line (pt 168 144)(pt 128 144)(line_width 1))
+ (line (pt 128 144)(pt 128 24)(line_width 1))
+ (line (pt 112 27)(pt 120 27)(line_width 1))
+ (line (pt 120 27)(pt 120 39)(line_width 1))
+ (line (pt 120 39)(pt 112 39)(line_width 1))
+ (line (pt 112 39)(pt 112 27)(line_width 1))
+ (line (pt 112 34)(pt 114 36)(line_width 1))
+ (line (pt 114 36)(pt 112 38)(line_width 1))
+ (line (pt 104 36)(pt 112 36)(line_width 1))
+ (line (pt 120 32)(pt 128 32)(line_width 3))
+ (line (pt 112 43)(pt 120 43)(line_width 1))
+ (line (pt 120 43)(pt 120 55)(line_width 1))
+ (line (pt 120 55)(pt 112 55)(line_width 1))
+ (line (pt 112 55)(pt 112 43)(line_width 1))
+ (line (pt 112 50)(pt 114 52)(line_width 1))
+ (line (pt 114 52)(pt 112 54)(line_width 1))
+ (line (pt 104 52)(pt 112 52)(line_width 1))
+ (line (pt 120 48)(pt 128 48)(line_width 3))
+ (line (pt 112 59)(pt 120 59)(line_width 1))
+ (line (pt 120 59)(pt 120 71)(line_width 1))
+ (line (pt 120 71)(pt 112 71)(line_width 1))
+ (line (pt 112 71)(pt 112 59)(line_width 1))
+ (line (pt 112 66)(pt 114 68)(line_width 1))
+ (line (pt 114 68)(pt 112 70)(line_width 1))
+ (line (pt 104 68)(pt 112 68)(line_width 1))
+ (line (pt 120 64)(pt 128 64)(line_width 1))
+ (line (pt 112 91)(pt 120 91)(line_width 1))
+ (line (pt 120 91)(pt 120 103)(line_width 1))
+ (line (pt 120 103)(pt 112 103)(line_width 1))
+ (line (pt 112 103)(pt 112 91)(line_width 1))
+ (line (pt 112 98)(pt 114 100)(line_width 1))
+ (line (pt 114 100)(pt 112 102)(line_width 1))
+ (line (pt 104 100)(pt 112 100)(line_width 1))
+ (line (pt 120 96)(pt 128 96)(line_width 3))
+ (line (pt 112 107)(pt 120 107)(line_width 1))
+ (line (pt 120 107)(pt 120 119)(line_width 1))
+ (line (pt 120 119)(pt 112 119)(line_width 1))
+ (line (pt 112 119)(pt 112 107)(line_width 1))
+ (line (pt 112 114)(pt 114 116)(line_width 1))
+ (line (pt 114 116)(pt 112 118)(line_width 1))
+ (line (pt 104 116)(pt 112 116)(line_width 1))
+ (line (pt 120 112)(pt 128 112)(line_width 3))
+ (line (pt 112 123)(pt 120 123)(line_width 1))
+ (line (pt 120 123)(pt 120 135)(line_width 1))
+ (line (pt 120 135)(pt 112 135)(line_width 1))
+ (line (pt 112 135)(pt 112 123)(line_width 1))
+ (line (pt 112 130)(pt 114 132)(line_width 1))
+ (line (pt 114 132)(pt 112 134)(line_width 1))
+ (line (pt 104 132)(pt 112 132)(line_width 1))
+ (line (pt 120 128)(pt 128 128)(line_width 1))
+ (line (pt 104 36)(pt 104 161)(line_width 1))
+ (line (pt 176 36)(pt 176 161)(line_width 1))
+ (line (pt 184 27)(pt 192 27)(line_width 1))
+ (line (pt 192 27)(pt 192 39)(line_width 1))
+ (line (pt 192 39)(pt 184 39)(line_width 1))
+ (line (pt 184 39)(pt 184 27)(line_width 1))
+ (line (pt 184 34)(pt 186 36)(line_width 1))
+ (line (pt 186 36)(pt 184 38)(line_width 1))
+ (line (pt 176 36)(pt 184 36)(line_width 1))
+ (line (pt 168 32)(pt 184 32)(line_width 3))
+ (line (pt 184 91)(pt 192 91)(line_width 1))
+ (line (pt 192 91)(pt 192 103)(line_width 1))
+ (line (pt 192 103)(pt 184 103)(line_width 1))
+ (line (pt 184 103)(pt 184 91)(line_width 1))
+ (line (pt 184 98)(pt 186 100)(line_width 1))
+ (line (pt 186 100)(pt 184 102)(line_width 1))
+ (line (pt 176 100)(pt 184 100)(line_width 1))
+ (line (pt 168 96)(pt 184 96)(line_width 3))
+ )
+)
diff --git a/mega/mmuram.cmp b/mega/mmuram.cmp
deleted file mode 100644
index 0e97f22..0000000
--- a/mega/mmuram.cmp
+++ /dev/null
@@ -1,35 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any megafunction design, and related netlist (encrypted or decrypted),
---support information, device programming or simulation file, and any other
---associated documentation or information provided by Altera or a partner
---under Altera's Megafunction Partnership Program may be used only
---to program PLD devices (but not masked PLD devices) from Altera. Any
---other use of such megafunction design, netlist, support information,
---device programming or simulation file, or any other related documentation
---or information is prohibited for any other purpose, including, but not
---limited to modification, reverse engineering, de-compiling, or use with
---any other silicon devices, unless such use is explicitly licensed under
---a separate agreement with Altera or a megafunction partner. Title to the
---intellectual property, including patents, copyrights, trademarks, trade
---secrets, or maskworks, embodied in any such megafunction design, netlist,
---support information, device programming or simulation file, or any other
---related documentation or information provided by Altera or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component mmuram
- PORT
- (
- data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
- wren_a : IN STD_LOGIC := '1';
- address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
- data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
- address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
- wren_b : IN STD_LOGIC := '1';
- clock : IN STD_LOGIC ;
- q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
- q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
- );
-end component;
diff --git a/mega/mmuram.inc b/mega/mmuram.inc
deleted file mode 100644
index 77b2ce0..0000000
--- a/mega/mmuram.inc
+++ /dev/null
@@ -1,36 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any megafunction design, and related netlist (encrypted or decrypted),
---support information, device programming or simulation file, and any other
---associated documentation or information provided by Altera or a partner
---under Altera's Megafunction Partnership Program may be used only
---to program PLD devices (but not masked PLD devices) from Altera. Any
---other use of such megafunction design, netlist, support information,
---device programming or simulation file, or any other related documentation
---or information is prohibited for any other purpose, including, but not
---limited to modification, reverse engineering, de-compiling, or use with
---any other silicon devices, unless such use is explicitly licensed under
---a separate agreement with Altera or a megafunction partner. Title to the
---intellectual property, including patents, copyrights, trademarks, trade
---secrets, or maskworks, embodied in any such megafunction design, netlist,
---support information, device programming or simulation file, or any other
---related documentation or information provided by Altera or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION mmuram
-(
- data_a[15..0],
- wren_a,
- address_a[9..0],
- data_b[15..0],
- address_b[9..0],
- wren_b,
- clock
-)
-
-RETURNS (
- q_a[15..0],
- q_b[15..0]
-);
diff --git a/mega/mmuram.v b/mega/mmuram.v
index aeb8628..420ffa0 100644
--- a/mega/mmuram.v
+++ b/mega/mmuram.v
@@ -1,201 +1,236 @@
-// megafunction wizard: %ALTSYNCRAM%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: mmuram.v
-// Megafunction Name(s):
-// altsyncram
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-module mmuram (
- data_a,
- wren_a,
- address_a,
- data_b,
- address_b,
- wren_b,
- clock,
- q_a,
- q_b);
-
- input [15:0] data_a;
- input wren_a;
- input [9:0] address_a;
- input [15:0] data_b;
- input [9:0] address_b;
- input wren_b;
- input clock;
- output [15:0] q_a;
- output [15:0] q_b;
-
- wire [15:0] sub_wire0;
- wire [15:0] sub_wire1;
- wire [15:0] q_a = sub_wire0[15:0];
- wire [15:0] q_b = sub_wire1[15:0];
-
- altsyncram altsyncram_component (
- .wren_a (wren_a),
- .clock0 (clock),
- .wren_b (wren_b),
- .address_a (address_a),
- .address_b (address_b),
- .data_a (data_a),
- .data_b (data_b),
- .q_a (sub_wire0),
- .q_b (sub_wire1));
- defparam
- altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
- altsyncram_component.width_a = 16,
- altsyncram_component.widthad_a = 10,
- altsyncram_component.numwords_a = 1024,
- altsyncram_component.width_b = 16,
- altsyncram_component.widthad_b = 10,
- altsyncram_component.numwords_b = 1024,
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.width_byteena_a = 1,
- altsyncram_component.width_byteena_b = 1,
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_reg_b = "CLOCK0",
- altsyncram_component.indata_aclr_a = "NONE",
- altsyncram_component.wrcontrol_aclr_a = "NONE",
- altsyncram_component.address_aclr_a = "NONE",
- altsyncram_component.indata_reg_b = "CLOCK0",
- altsyncram_component.address_reg_b = "CLOCK0",
- altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
- altsyncram_component.indata_aclr_b = "NONE",
- altsyncram_component.wrcontrol_aclr_b = "NONE",
- altsyncram_component.address_aclr_b = "NONE",
- altsyncram_component.outdata_aclr_b = "NONE",
- altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.ram_block_type = "AUTO",
- altsyncram_component.init_file = "data/mmu.mif",
- altsyncram_component.maximum_depth = 256,
- altsyncram_component.intended_device_family = "Stratix";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: REGrren NUMERIC "0"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/mmu.mif"
-// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/mmu.mif"
-// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
-// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
-// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]
-// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
-// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]
-// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// megafunction wizard: %ALTSYNCRAM%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: mmuram.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Build 163 10/28/2008 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module mmuram (
+ address_a,
+ address_b,
+ clock,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [7:0] address_a;
+ input [7:0] address_b;
+ input clock;
+ input [15:0] data_a;
+ input [15:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [15:0] q_a;
+ output [15:0] q_b;
+
+ wire [15:0] sub_wire0;
+ wire [15:0] sub_wire1;
+ wire [15:0] q_a = sub_wire0[15:0];
+ wire [15:0] q_b = sub_wire1[15:0];
+
+ altsyncram altsyncram_component (
+ .wren_a (wren_a),
+ .clock0 (clock),
+ .wren_b (wren_b),
+ .address_a (address_a),
+ .address_b (address_b),
+ .data_a (data_a),
+ .data_b (data_b),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clock1 (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1));
+ defparam
+ altsyncram_component.address_reg_b = "CLOCK0",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_input_b = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.clock_enable_output_b = "BYPASS",
+ altsyncram_component.indata_reg_b = "CLOCK0",
+ altsyncram_component.init_file = "data/mmu.mif",
+ altsyncram_component.intended_device_family = "Cyclone II",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.maximum_depth = 256,
+ altsyncram_component.numwords_a = 256,
+ altsyncram_component.numwords_b = 256,
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_aclr_b = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.outdata_reg_b = "CLOCK0",
+ altsyncram_component.power_up_uninitialized = "FALSE",
+ altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+ altsyncram_component.widthad_a = 8,
+ altsyncram_component.widthad_b = 8,
+ altsyncram_component.width_a = 16,
+ altsyncram_component.width_b = 16,
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.width_byteena_b = 1,
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: ECC NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "data/mmu.mif"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data/mmu.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/mmuram_bb.v b/mega/mmuram_bb.v
index cdc050b..d5c826e 100644
--- a/mega/mmuram_bb.v
+++ b/mega/mmuram_bb.v
@@ -1,43 +1,173 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module mmuram (
- data_a,
- wren_a,
- address_a,
- data_b,
- address_b,
- wren_b,
- clock,
- q_a,
- q_b);
-
- input [15:0] data_a;
- input wren_a;
- input [9:0] address_a;
- input [15:0] data_b;
- input [9:0] address_b;
- input wren_b;
- input clock;
- output [15:0] q_a;
- output [15:0] q_b;
-
-endmodule
-
+// megafunction wizard: %ALTSYNCRAM%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: mmuram.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Build 163 10/28/2008 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module mmuram (
+ address_a,
+ address_b,
+ clock,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [7:0] address_a;
+ input [7:0] address_b;
+ input clock;
+ input [15:0] data_a;
+ input [15:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [15:0] q_a;
+ output [15:0] q_b;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: ECC NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "data/mmu.mif"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data/mmu.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/mmuram_inst.v b/mega/mmuram_inst.v
index d2f6996..3088a8e 100644
--- a/mega/mmuram_inst.v
+++ b/mega/mmuram_inst.v
@@ -1,11 +1,11 @@
-mmuram mmuram_inst (
- .data_a ( data_a_sig ),
- .wren_a ( wren_a_sig ),
- .address_a ( address_a_sig ),
- .data_b ( data_b_sig ),
- .address_b ( address_b_sig ),
- .wren_b ( wren_b_sig ),
- .clock ( clock_sig ),
- .q_a ( q_a_sig ),
- .q_b ( q_b_sig )
- );
+mmuram mmuram_inst (
+ .address_a ( address_a_sig ),
+ .address_b ( address_b_sig ),
+ .clock ( clock_sig ),
+ .data_a ( data_a_sig ),
+ .data_b ( data_b_sig ),
+ .wren_a ( wren_a_sig ),
+ .wren_b ( wren_b_sig ),
+ .q_a ( q_a_sig ),
+ .q_b ( q_b_sig )
+ );
diff --git a/mega/pll1.bsf b/mega/pll1.bsf
index 2d1bb90..c7956b7 100644
--- a/mega/pll1.bsf
+++ b/mega/pll1.bsf
@@ -1,104 +1,93 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2004 Altera Corporation
-Any megafunction design, and related netlist (encrypted or decrypted),
-support information, device programming or simulation file, and any other
-associated documentation or information provided by Altera or a partner
-under Altera's Megafunction Partnership Program may be used only
-to program PLD devices (but not masked PLD devices) from Altera. Any
-other use of such megafunction design, netlist, support information,
-device programming or simulation file, or any other related documentation
-or information is prohibited for any other purpose, including, but not
-limited to modification, reverse engineering, de-compiling, or use with
-any other silicon devices, unless such use is explicitly licensed under
-a separate agreement with Altera or a megafunction partner. Title to the
-intellectual property, including patents, copyrights, trademarks, trade
-secrets, or maskworks, embodied in any such megafunction design, netlist,
-support information, device programming or simulation file, or any other
-related documentation or information provided by Altera or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 272 184)
- (text "pll1" (rect 136 0 159 16)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 168 25 180)(font "Arial" ))
- (port
- (pt 0 64)
- (input)
- (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
- (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
- (line (pt 0 64)(pt 40 64)(line_width 1))
- )
- (port
- (pt 272 64)
- (output)
- (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
- (text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
- (line (pt 272 64)(pt 240 64)(line_width 1))
- )
- (port
- (pt 272 80)
- (output)
- (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
- (text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
- (line (pt 272 80)(pt 240 80)(line_width 1))
- )
- (port
- (pt 272 96)
- (output)
- (text "e0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
- (text "e0" (rect 257 83 269 96)(font "Arial" (font_size 8)))
- (line (pt 272 96)(pt 240 96)(line_width 1))
- )
- (drawing
- (text "Cyclone" (rect 229 169 264 181)(font "Arial" ))
- (text "inclk0 frequency: 50.000 MHz" (rect 50 59 175 71)(font "Arial" ))
- (text "Operation Mode: Normal" (rect 50 73 151 85)(font "Arial" ))
- (text "Clk " (rect 51 96 68 108)(font "Arial" ))
- (text "Ratio" (rect 73 96 95 108)(font "Arial" ))
- (text "Ph (dg)" (rect 100 96 130 108)(font "Arial" ))
- (text "Td (ns)" (rect 135 96 164 108)(font "Arial" ))
- (text "DC (%)" (rect 169 96 200 108)(font "Arial" ))
- (text "c0" (rect 54 111 64 123)(font "Arial" ))
- (text "2/1" (rect 78 111 91 123)(font "Arial" ))
- (text "0.00" (rect 106 111 124 123)(font "Arial" ))
- (text "0.00" (rect 140 111 158 123)(font "Arial" ))
- (text "50.00" (rect 173 111 196 123)(font "Arial" ))
- (text "c1" (rect 54 126 64 138)(font "Arial" ))
- (text "1/2" (rect 78 126 91 138)(font "Arial" ))
- (text "0.00" (rect 106 126 124 138)(font "Arial" ))
- (text "0.00" (rect 140 126 158 138)(font "Arial" ))
- (text "50.00" (rect 173 126 196 138)(font "Arial" ))
- (text "e0" (rect 54 141 64 153)(font "Arial" ))
- (text "1/2" (rect 78 141 91 153)(font "Arial" ))
- (text "0.00" (rect 106 141 124 153)(font "Arial" ))
- (text "0.00" (rect 140 141 158 153)(font "Arial" ))
- (text "50.00" (rect 173 141 196 153)(font "Arial" ))
- (line (pt 0 0)(pt 273 0)(line_width 1))
- (line (pt 273 0)(pt 273 185)(line_width 1))
- (line (pt 0 185)(pt 273 185)(line_width 1))
- (line (pt 0 0)(pt 0 185)(line_width 1))
- (line (pt 48 94)(pt 202 94)(line_width 1))
- (line (pt 48 108)(pt 202 108)(line_width 1))
- (line (pt 48 123)(pt 202 123)(line_width 1))
- (line (pt 48 138)(pt 202 138)(line_width 1))
- (line (pt 48 153)(pt 202 153)(line_width 1))
- (line (pt 48 94)(pt 48 153)(line_width 1))
- (line (pt 70 94)(pt 70 153)(line_width 3))
- (line (pt 97 94)(pt 97 153)(line_width 3))
- (line (pt 132 94)(pt 132 153)(line_width 3))
- (line (pt 166 94)(pt 166 153)(line_width 3))
- (line (pt 201 94)(pt 201 153)(line_width 1))
- (line (pt 40 48)(pt 240 48)(line_width 1))
- (line (pt 240 48)(pt 240 168)(line_width 1))
- (line (pt 40 168)(pt 240 168)(line_width 1))
- (line (pt 40 48)(pt 40 168)(line_width 1))
- )
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 240 184)
+ (text "pll1" (rect 110 0 133 16)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 168 25 180)(font "Arial" ))
+ (port
+ (pt 0 64)
+ (input)
+ (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 40 64)(line_width 1))
+ )
+ (port
+ (pt 240 64)
+ (output)
+ (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 225 51 236 64)(font "Arial" (font_size 8)))
+ (line (pt 240 64)(pt 208 64)(line_width 1))
+ )
+ (port
+ (pt 240 80)
+ (output)
+ (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "c1" (rect 225 67 236 80)(font "Arial" (font_size 8)))
+ (line (pt 240 80)(pt 208 80)(line_width 1))
+ )
+ (port
+ (pt 240 96)
+ (output)
+ (text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+ (text "c2" (rect 225 83 236 96)(font "Arial" (font_size 8)))
+ (line (pt 240 96)(pt 208 96)(line_width 1))
+ )
+ (drawing
+ (text "Cyclone II" (rect 183 169 227 181)(font "Arial" ))
+ (text "inclk0 frequency: 50.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+ (text "Operation Mode: Normal" (rect 50 73 151 85)(font "Arial" ))
+ (text "Clk " (rect 51 96 68 108)(font "Arial" ))
+ (text "Ratio" (rect 73 96 95 108)(font "Arial" ))
+ (text "Ph (dg)" (rect 100 96 130 108)(font "Arial" ))
+ (text "DC (%)" (rect 135 96 166 108)(font "Arial" ))
+ (text "c0" (rect 54 111 64 123)(font "Arial" ))
+ (text "2/1" (rect 78 111 91 123)(font "Arial" ))
+ (text "0.00" (rect 106 111 124 123)(font "Arial" ))
+ (text "50.00" (rect 139 111 162 123)(font "Arial" ))
+ (text "c1" (rect 54 126 64 138)(font "Arial" ))
+ (text "1/2" (rect 78 126 91 138)(font "Arial" ))
+ (text "0.00" (rect 106 126 124 138)(font "Arial" ))
+ (text "50.00" (rect 139 126 162 138)(font "Arial" ))
+ (text "c2" (rect 54 141 64 153)(font "Arial" ))
+ (text "1/2" (rect 78 141 91 153)(font "Arial" ))
+ (text "0.00" (rect 106 141 124 153)(font "Arial" ))
+ (text "50.00" (rect 139 141 162 153)(font "Arial" ))
+ (line (pt 0 0)(pt 241 0)(line_width 1))
+ (line (pt 241 0)(pt 241 185)(line_width 1))
+ (line (pt 0 185)(pt 241 185)(line_width 1))
+ (line (pt 0 0)(pt 0 185)(line_width 1))
+ (line (pt 48 94)(pt 168 94)(line_width 1))
+ (line (pt 48 108)(pt 168 108)(line_width 1))
+ (line (pt 48 123)(pt 168 123)(line_width 1))
+ (line (pt 48 138)(pt 168 138)(line_width 1))
+ (line (pt 48 153)(pt 168 153)(line_width 1))
+ (line (pt 48 94)(pt 48 153)(line_width 1))
+ (line (pt 70 94)(pt 70 153)(line_width 3))
+ (line (pt 97 94)(pt 97 153)(line_width 3))
+ (line (pt 132 94)(pt 132 153)(line_width 3))
+ (line (pt 167 94)(pt 167 153)(line_width 1))
+ (line (pt 40 48)(pt 208 48)(line_width 1))
+ (line (pt 208 48)(pt 208 168)(line_width 1))
+ (line (pt 40 168)(pt 208 168)(line_width 1))
+ (line (pt 40 48)(pt 40 168)(line_width 1))
+ )
+)
diff --git a/mega/pll1.cmp b/mega/pll1.cmp
deleted file mode 100644
index 89fa33a..0000000
--- a/mega/pll1.cmp
+++ /dev/null
@@ -1,30 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any megafunction design, and related netlist (encrypted or decrypted),
---support information, device programming or simulation file, and any other
---associated documentation or information provided by Altera or a partner
---under Altera's Megafunction Partnership Program may be used only
---to program PLD devices (but not masked PLD devices) from Altera. Any
---other use of such megafunction design, netlist, support information,
---device programming or simulation file, or any other related documentation
---or information is prohibited for any other purpose, including, but not
---limited to modification, reverse engineering, de-compiling, or use with
---any other silicon devices, unless such use is explicitly licensed under
---a separate agreement with Altera or a megafunction partner. Title to the
---intellectual property, including patents, copyrights, trademarks, trade
---secrets, or maskworks, embodied in any such megafunction design, netlist,
---support information, device programming or simulation file, or any other
---related documentation or information provided by Altera or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-component pll1
- PORT
- (
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- e0 : OUT STD_LOGIC
- );
-end component;
diff --git a/mega/pll1.inc b/mega/pll1.inc
deleted file mode 100644
index a5055c3..0000000
--- a/mega/pll1.inc
+++ /dev/null
@@ -1,31 +0,0 @@
---Copyright (C) 1991-2003 Altera Corporation
---Any megafunction design, and related netlist (encrypted or decrypted),
---support information, device programming or simulation file, and any other
---associated documentation or information provided by Altera or a partner
---under Altera's Megafunction Partnership Program may be used only
---to program PLD devices (but not masked PLD devices) from Altera. Any
---other use of such megafunction design, netlist, support information,
---device programming or simulation file, or any other related documentation
---or information is prohibited for any other purpose, including, but not
---limited to modification, reverse engineering, de-compiling, or use with
---any other silicon devices, unless such use is explicitly licensed under
---a separate agreement with Altera or a megafunction partner. Title to the
---intellectual property, including patents, copyrights, trademarks, trade
---secrets, or maskworks, embodied in any such megafunction design, netlist,
---support information, device programming or simulation file, or any other
---related documentation or information provided by Altera or a megafunction
---partner, remains with Altera, the megafunction partner, or their respective
---licensors. No other licenses, including any licenses needed under any third
---party's intellectual property, are provided herein.
-
-
-FUNCTION pll1
-(
- inclk0
-)
-
-RETURNS (
- c0,
- c1,
- e0
-);
diff --git a/mega/pll1.v b/mega/pll1.v
index 8528e8f..7f7e921 100644
--- a/mega/pll1.v
+++ b/mega/pll1.v
@@ -1,262 +1,349 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll1.v
-// Megafunction Name(s):
-// altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.1 Build 208 09/10/2004 SP 2 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll1 (
- inclk0,
- c0,
- c1,
- e0);
-
- input inclk0;
- output c0;
- output c1;
- output e0;
-
- wire [5:0] sub_wire0;
- wire [3:0] sub_wire3;
- wire [0:0] sub_wire7 = 1'h0;
- wire [1:1] sub_wire2 = sub_wire0[1:1];
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire c1 = sub_wire2;
- wire [0:0] sub_wire4 = sub_wire3[0:0];
- wire e0 = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
-
- altpll altpll_component (
- .inclk (sub_wire6),
- .clk (sub_wire0),
- .extclk (sub_wire3)
- // synopsys translate_off
- ,
- .clkswitch (),
- .extclkena (),
- .scandataout (),
- .pfdena (),
- .locked (),
- .clkena (),
- .clkbad (),
- .pllena (),
- .areset (),
- .activeclock (),
- .scanclk (),
- .enable0 (),
- .enable1 (),
- .clkloss (),
- .scandata (),
- .scanread (),
- .scandone (),
- .scanaclr (),
- .sclkout0 (),
- .sclkout1 (),
- .scanwrite (),
- .fbin ()
- // synopsys translate_on
- );
- defparam
- altpll_component.clk1_divide_by = 2,
- altpll_component.clk1_phase_shift = "0",
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.lpm_type = "altpll",
- altpll_component.clk0_multiply_by = 2,
- altpll_component.inclk0_input_frequency = 20000,
- altpll_component.extclk0_duty_cycle = 50,
- altpll_component.clk0_divide_by = 1,
- altpll_component.extclk0_phase_shift = "0",
- altpll_component.extclk0_divide_by = 2,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.pll_type = "AUTO",
- altpll_component.clk1_multiply_by = 1,
- altpll_component.clk0_time_delay = "0",
- altpll_component.intended_device_family = "Cyclone",
- altpll_component.extclk0_time_delay = "0",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.extclk0_multiply_by = 1,
- altpll_component.compensate_clock = "CLK0",
- altpll_component.clk1_time_delay = "0",
- altpll_component.clk0_phase_shift = "0";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: TIME_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
-// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: EXTCLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll1.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Build 163 10/28/2008 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll1 (
+ inclk0,
+ c0,
+ c1,
+ c2);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [2:2] sub_wire3 = sub_wire0[2:2];
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire c2 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .locked (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 2,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_UNUSED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll1_bb.v b/mega/pll1_bb.v
index 04f673d..079df61 100644
--- a/mega/pll1_bb.v
+++ b/mega/pll1_bb.v
@@ -1,191 +1,236 @@
-// megafunction wizard: %ALTPLL%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll1.v
-// Megafunction Name(s):
-// altpll
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.1 Build 208 09/10/2004 SP 2 SJ Web Edition
-// ************************************************************
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module pll1 (
- inclk0,
- c0,
- c1,
- e0);
-
- input inclk0;
- output c0;
- output c1;
- output e0;
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: TIME_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
-// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "2"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
-// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: EXTCLK0_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0"
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll1.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 8.1 Build 163 10/28/2008 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2008 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module pll1 (
+ inclk0,
+ c0,
+ c1,
+ c2);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll1_inst.v b/mega/pll1_inst.v
deleted file mode 100644
index 994b65d..0000000
--- a/mega/pll1_inst.v
+++ /dev/null
@@ -1,6 +0,0 @@
-pll1 pll1_inst (
- .inclk0 ( inclk0_sig ),
- .c0 ( c0_sig ),
- .c1 ( c1_sig ),
- .e0 ( e0_sig )
- );
diff --git a/mega/printerrom.bsf b/mega/printerrom.bsf
index a9dcb40..62b481f 100755..100644
--- a/mega/printerrom.bsf
+++ b/mega/printerrom.bsf
@@ -1,71 +1,71 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2004 Altera Corporation
-Any megafunction design, and related netlist (encrypted or decrypted),
-support information, device programming or simulation file, and any other
-associated documentation or information provided by Altera or a partner
-under Altera's Megafunction Partnership Program may be used only
-to program PLD devices (but not masked PLD devices) from Altera. Any
-other use of such megafunction design, netlist, support information,
-device programming or simulation file, or any other related documentation
-or information is prohibited for any other purpose, including, but not
-limited to modification, reverse engineering, de-compiling, or use with
-any other silicon devices, unless such use is explicitly licensed under
-a separate agreement with Altera or a megafunction partner. Title to the
-intellectual property, including patents, copyrights, trademarks, trade
-secrets, or maskworks, embodied in any such megafunction design, netlist,
-support information, device programming or simulation file, or any other
-related documentation or information provided by Altera or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 256 112)
- (text "printerrom" (rect 99 1 167 17)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 96 25 108)(font "Arial" ))
- (port
- (pt 0 32)
- (input)
- (text "address[8..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
- (text "address[8..0]" (rect 4 19 63 32)(font "Arial" (font_size 8)))
- (line (pt 0 32)(pt 112 32)(line_width 3))
- )
- (port
- (pt 0 88)
- (input)
- (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
- (text "clock" (rect 4 75 27 88)(font "Arial" (font_size 8)))
- (line (pt 0 88)(pt 104 88)(line_width 1))
- )
- (port
- (pt 256 32)
- (output)
- (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
- (text "q[7..0]" (rect 223 19 253 32)(font "Arial" (font_size 8)))
- (line (pt 256 32)(pt 168 32)(line_width 3))
- )
- (drawing
- (text "512 Word(s)" (rect 136 26 148 77)(font "Arial" )(vertical))
- (text "RAM" (rect 149 42 161 62)(font "Arial" )(vertical))
- (text "Block Type: AUTO" (rect 41 92 119 104)(font "Arial" ))
- (line (pt 128 24)(pt 168 24)(line_width 1))
- (line (pt 168 24)(pt 168 80)(line_width 1))
- (line (pt 168 80)(pt 128 80)(line_width 1))
- (line (pt 128 80)(pt 128 24)(line_width 1))
- (line (pt 112 27)(pt 120 27)(line_width 1))
- (line (pt 120 27)(pt 120 39)(line_width 1))
- (line (pt 120 39)(pt 112 39)(line_width 1))
- (line (pt 112 39)(pt 112 27)(line_width 1))
- (line (pt 112 34)(pt 114 36)(line_width 1))
- (line (pt 114 36)(pt 112 38)(line_width 1))
- (line (pt 104 36)(pt 112 36)(line_width 1))
- (line (pt 120 32)(pt 128 32)(line_width 3))
- (line (pt 104 36)(pt 104 89)(line_width 1))
- )
-)
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2004 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 256 112)
+ (text "printerrom" (rect 99 1 167 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 96 25 108)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "address[8..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+ (text "address[8..0]" (rect 4 19 63 32)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 112 32)(line_width 3))
+ )
+ (port
+ (pt 0 88)
+ (input)
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 4 75 27 88)(font "Arial" (font_size 8)))
+ (line (pt 0 88)(pt 104 88)(line_width 1))
+ )
+ (port
+ (pt 256 32)
+ (output)
+ (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "q[7..0]" (rect 223 19 253 32)(font "Arial" (font_size 8)))
+ (line (pt 256 32)(pt 168 32)(line_width 3))
+ )
+ (drawing
+ (text "512 Word(s)" (rect 136 26 148 77)(font "Arial" )(vertical))
+ (text "RAM" (rect 149 42 161 62)(font "Arial" )(vertical))
+ (text "Block Type: AUTO" (rect 41 92 119 104)(font "Arial" ))
+ (line (pt 128 24)(pt 168 24)(line_width 1))
+ (line (pt 168 24)(pt 168 80)(line_width 1))
+ (line (pt 168 80)(pt 128 80)(line_width 1))
+ (line (pt 128 80)(pt 128 24)(line_width 1))
+ (line (pt 112 27)(pt 120 27)(line_width 1))
+ (line (pt 120 27)(pt 120 39)(line_width 1))
+ (line (pt 120 39)(pt 112 39)(line_width 1))
+ (line (pt 112 39)(pt 112 27)(line_width 1))
+ (line (pt 112 34)(pt 114 36)(line_width 1))
+ (line (pt 114 36)(pt 112 38)(line_width 1))
+ (line (pt 104 36)(pt 112 36)(line_width 1))
+ (line (pt 120 32)(pt 128 32)(line_width 3))
+ (line (pt 104 36)(pt 104 89)(line_width 1))
+ )
+)
diff --git a/mega/printerrom.v b/mega/printerrom.v
index eccde8f..5a0fbbb 100755..100644
--- a/mega/printerrom.v
+++ b/mega/printerrom.v
@@ -1,176 +1,176 @@
-// megafunction wizard: %ALTSYNCRAM%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: printerrom.v
-// Megafunction Name(s):
-// altsyncram
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module printerrom (
- address,
- clock,
- q);
-
- input [8:0] address;
- input clock;
- output [7:0] q;
-
- wire [7:0] sub_wire0;
- wire [7:0] q = sub_wire0[7:0];
-
- altsyncram altsyncram_component (
- .clock0 (clock),
- .address_a (address),
- .q_a (sub_wire0),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .rden_b (1'b1),
- .clock1 (1'b1),
- .data_a (8'b11111111),
- .data_b (1'b1),
- .wren_a (1'b0),
- .wren_b (1'b0),
- .q_b (),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .address_b (1'b1),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0));
- defparam
- altsyncram_component.operation_mode = "ROM",
- altsyncram_component.width_a = 8,
- altsyncram_component.widthad_a = 9,
- altsyncram_component.numwords_a = 512,
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.width_byteena_a = 1,
- altsyncram_component.outdata_reg_a = "UNREGISTERED",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.address_aclr_a = "NONE",
- altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.init_file = "data/printer.mif",
- altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
- altsyncram_component.intended_device_family = "Cyclone";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGrren NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/printer.mif"
-// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/printer.mif"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_wave*.jpg FALSE
+// megafunction wizard: %ALTSYNCRAM%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: printerrom.v
+// Megafunction Name(s):
+// altsyncram
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module printerrom (
+ address,
+ clock,
+ q);
+
+ input [8:0] address;
+ input clock;
+ output [7:0] q;
+
+ wire [7:0] sub_wire0;
+ wire [7:0] q = sub_wire0[7:0];
+
+ altsyncram altsyncram_component (
+ .clock0 (clock),
+ .address_a (address),
+ .q_a (sub_wire0),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .rden_b (1'b1),
+ .clock1 (1'b1),
+ .data_a (8'b11111111),
+ .data_b (1'b1),
+ .wren_a (1'b0),
+ .wren_b (1'b0),
+ .q_b (),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .address_b (1'b1),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0));
+ defparam
+ altsyncram_component.operation_mode = "ROM",
+ altsyncram_component.width_a = 8,
+ altsyncram_component.widthad_a = 9,
+ altsyncram_component.numwords_a = 512,
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.address_aclr_a = "NONE",
+ altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+ altsyncram_component.init_file = "data/printer.mif",
+ altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+ altsyncram_component.intended_device_family = "Cyclone";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "data/printer.mif"
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data/printer.mif"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_wave*.jpg FALSE
diff --git a/mega/printerrom_bb.v b/mega/printerrom_bb.v
index a52254a..ccdd820 100755..100644
--- a/mega/printerrom_bb.v
+++ b/mega/printerrom_bb.v
@@ -1,132 +1,132 @@
-// megafunction wizard: %ALTSYNCRAM%VBB%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: printerrom.v
-// Megafunction Name(s):
-// altsyncram
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
-// ************************************************************
-
-//Copyright (C) 1991-2004 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-module printerrom (
- address,
- clock,
- q);
-
- input [8:0] address;
- input clock;
- output [7:0] q;
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGrren NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/printer.mif"
-// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/printer.mif"
-// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
-// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_wave*.jpg FALSE
+// megafunction wizard: %ALTSYNCRAM%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: printerrom.v
+// Megafunction Name(s):
+// altsyncram
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2004 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module printerrom (
+ address,
+ clock,
+ q);
+
+ input [8:0] address;
+ input clock;
+ output [7:0] q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGrren NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "data/printer.mif"
+// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data/printer.mif"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL address[8..0]
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL printerrom_wave*.jpg FALSE
diff --git a/mega/cfram.v b/mega/sdram.v
index e8956bc..00d6516 100755..100644
--- a/mega/cfram.v
+++ b/mega/sdram.v
@@ -4,7 +4,7 @@
// MODULE: altsyncram
// ============================================================
-// File Name: cfram.v
+// File Name: sdram.v
// Megafunction Name(s):
// altsyncram
// ============================================================
@@ -39,7 +39,7 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
-module cfram (
+module sdram (
data_a,
wren_a,
address_a,
@@ -110,7 +110,7 @@ module cfram (
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.init_file = "data/cfram.mif",
+ altsyncram_component.init_file = "data/sdram.mif",
altsyncram_component.intended_device_family = "Cyclone";
@@ -162,7 +162,7 @@ endmodule
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/cfram.mif"
+// Retrieval info: PRIVATE: MIFfilename STRING "data/sdram.mif"
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
@@ -197,7 +197,7 @@ endmodule
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/cfram.mif"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data/sdram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
@@ -218,11 +218,11 @@ endmodule
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL cfram_wave*.jpg FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sdram_wave*.jpg FALSE
diff --git a/sddisk.v b/sddisk.v
new file mode 100755
index 0000000..2b01f29
--- /dev/null
+++ b/sddisk.v
@@ -0,0 +1,471 @@
+// MMC/SD controller for ABC80
+// Designed to be compatible with the standard ABC-DOS controllers
+//
+// Note: in order for this to not require internal tristate buffers in
+// the FPGA, the data bus is split, and the "input" bus will be driven
+// to all FF when the card is not selected, so all inputs can be ANDed.
+
+//
+// The I/O port range is decoded as follows:
+//
+// A7..A6 - unused
+// A5 - SD card (1) / DMA engine (0)
+// A4..A0 - register select on CompactFlash card/DMA engine, see
+// respective unit
+
+module sdcontroller(
+ reset_n, // Global reset
+ clk, // CPU clk (25 MHz)
+
+ sd_cs_n, // SD card CS# (CD, DAT3)
+ sd_di, // SD card DI (MOSI, CMD)
+ sd_clk, // SD card CLK (SCLK)
+ sd_do, // SD card SO (MISO, DAT0)
+
+ abc_do, // ABC-bus data out (CPU->controller)
+ abc_di, // ABC-bus data in (controller->CPU)
+ abc_out_n, // ABC-bus data out select (OUT 0)
+ abc_cs_n, // ABC-bus Card Select
+ abc_c1_n, // ABC-bus Command 1 (OUT 2)
+ abc_c2_n, // ABC-bus Command 2 (OUT 3)
+ abc_c3_n, // ABC-bus Command 3 (OUT 4)
+ abc_c4_n, // ABC-bus Command 4 (OUT 5)
+ abc_inp_n, // ABC-bus data in select (IN 0)
+ abc_status_n, // ABC-bus status (IN 1)
+ abc_rst_n, // ABC-bus reset (IN 7)
+
+ select, // Selected LED
+ active // Active LED
+ );
+
+ input reset_n;
+ input clk;
+
+ output sd_cs_n;
+ output sd_di;
+ output sd_clk;
+ input sd_do;
+
+ input [7:0] abc_do;
+ output [7:0] abc_di;
+ input abc_out_n;
+ input abc_cs_n;
+ input abc_c1_n;
+ input abc_c2_n;
+ input abc_c3_n;
+ input abc_c4_n;
+ input abc_inp_n;
+ input abc_status_n;
+ input abc_rst_n;
+
+ output select;
+ output active;
+
+ // Forward declaration
+ wire cpu_wait_n; // If we should raise WAIT# to CPU
+
+ // Which select code this device uses... select code 36 decimal is used
+ // for hard disk controllers; this maps this device as HDx:
+ parameter selectcode = 6'd36;
+ reg selected;
+
+ assign select = selected; // For external LED, might need hysteresis
+
+ // ------------------------------------------------------------------------
+ // Reset and ABC-bus select
+ // Note: for glitch prevention reasons, treat RST# and C3# as synchronous
+ // resets only.
+ // ------------------------------------------------------------------------
+ reg ireset;
+
+ always @(negedge reset_n or posedge clk)
+ begin
+ if ( ~reset_n )
+ begin
+ ireset <= 1;
+ selected <= 0;
+ end
+ else // clock
+ begin
+ ireset <= 0;
+ if ( ~abc_rst_n )
+ begin
+ ireset <= 1;
+ selected <= 0;
+ end
+ else
+ begin
+ if ( selected & ~abc_c3_n )
+ ireset <= 1;
+
+ if ( ~abc_cs_n )
+ selected <= (abc_do[5:0] == selectcode);
+ end
+ end
+ end
+
+ // ------------------------------------------------------------------------
+ // Controller CPU
+ // ------------------------------------------------------------------------
+
+ wire cpu_m1_n;
+ wire cpu_iorq_n;
+ wire cpu_mreq_n;
+ wire cpu_rd_n;
+ wire cpu_wr_n;
+ wire [15:0] cpu_a;
+ wire [7:0] cpu_di;
+ wire [7:0] cpu_do;
+ reg cpu_int_n;
+
+ T80se sd_cpu (
+ .clk_n ( clk ),
+ .reset_n ( ~ireset ),
+ .clken ( cpu_wait_n ),
+ .wait_n ( 1'b1 ),
+ .int_n ( cpu_int_n ),
+ .nmi_n ( 1'b1 ),
+ .busrq_n ( 1'b1 ),
+ .m1_n ( cpu_m1_n ),
+ .mreq_n ( cpu_mreq_n ),
+ .iorq_n ( cpu_iorq_n ),
+ .rd_n ( cpu_rd_n ),
+ .wr_n ( cpu_wr_n ),
+ .a ( cpu_a ),
+ .di ( cpu_di ),
+ .do ( cpu_do )
+ );
+
+ // C1# from the ABC bus generates interrupt; this is used to
+ // reset the controller state machine to the command state.
+ always @(posedge ireset or posedge clk)
+ begin
+ if ( ireset )
+ cpu_int_n <= 1'b1;
+ else
+ if ( selected & ~abc_c1_n )
+ cpu_int_n <= 1'b0;
+ else if ( ~cpu_m1_n & ~cpu_iorq_n ) // INTAK
+ cpu_int_n <= 1'b1;
+ end // always @ (posedge ireset or posedge clk)
+
+
+ // ------------------------------------------------------------------------
+ // Memory -- second port used for "DMA" to the main CPU
+ // ------------------------------------------------------------------------
+
+ wire [7:0] memrd; // Read data to controller CPU
+ reg write_flag; // DMA if we should write data to controller RAM
+ reg read_flag; // DMA if we just read data from controller RAM
+ reg [7:0] cpudata_di; // DMA data to controller memory
+ wire [7:0] cpudata_do; // DMA data from controller memory
+ reg [10:0] cpudata_addr; // DMA target address
+
+ sdram sdram_inst (
+ .clock ( ~clk ),
+ .address_a ( cpu_a[10:0] ),
+ .data_a ( cpu_do ),
+ .wren_a ( ~cpu_mreq_n & ~cpu_wr_n ),
+ .q_a ( memrd ),
+ .address_b ( cpudata_addr ),
+ .data_b ( cpudata_di ),
+ .wren_b ( write_flag ),
+ .q_b ( cpudata_do )
+ );
+
+ // ------------------------------------------------------------------------
+ // ABC-bus interface (DMA engine)
+ //
+ // Control interface addressed on I/O with A5 = 0
+ // The following ports are decoded:
+ // OUT 0x00: write main CPU status (returned to main CPU by IN 0)
+ // OUT 0x01: write aux CPU status (returned to main CPU by IN 1)
+ // OUT 0x04: bits [7:0] of DMA address
+ // OUT 0x05: bits [10:8] of DMA address; D7 is direction bit
+ // (0 = main CPU->controller, 1 = controller->main CPU)
+ // OUT 0x06-0x07: set DMA byte counter, A0 is bit 8 of counter
+ // IN 0x00: D0 = DMA active (transaction in progress)
+ // D1 = direction bit (see above)
+ // ------------------------------------------------------------------------
+
+ reg [8:0] cpudata_ctr; // Bytes left to DMA
+ reg cpudata_dir; // 0 = out, 1 = inp
+ reg [7:0] aux_status; // Auxilliary status
+ reg [7:0] main_status; // Primary status
+ wire [7:0] dma_status; // Controller CPU query DMA engine status
+ wire dma_stat_sel = ~cpu_iorq_n & cpu_m1_n & ~cpu_a[5]; // IN 0x00
+ wire dma_active = |cpudata_ctr;
+
+ reg [7:0] abc_di;
+ always @(*)
+ begin
+ if ( selected & ~abc_inp_n )
+ if ( dma_active && cpudata_dir == 1 )
+ abc_di = cpudata_do;
+ else
+ abc_di = aux_status;
+ else if ( selected & ~abc_status_n )
+ abc_di = main_status;
+ else
+ abc_di = 8'hFF;
+ end // always @ (*)
+
+ always @(posedge ireset or posedge clk)
+ begin
+ if ( ireset )
+ begin
+ cpudata_addr <= ~11'b0;
+ cpudata_ctr <= 0;
+ cpudata_dir <= 0;
+ write_flag <= 0;
+ read_flag <= 0;
+ main_status <= 0;
+ aux_status <= 0;
+ end
+ else
+ begin
+ write_flag <= 0;
+ read_flag <= 0;
+
+ if ( selected & ~abc_out_n )
+ begin
+ if ( dma_active && cpudata_dir == 0 )
+ begin
+ cpudata_di <= abc_do;
+ write_flag <= 1;
+ end
+ end // if ( selected & ~abc_out_n )
+
+ if ( selected & ~abc_inp_n )
+ begin
+ if ( dma_active && cpudata_dir == 1 )
+ begin
+ // abc_di is generated above
+ read_flag <= 1;
+ end
+ end // if ( selected & ~abc_inp_n )
+
+ if ( (write_flag & ~(selected & ~abc_out_n)) |
+ (read_flag & ~(selected & ~abc_inp_n)) )
+ begin
+ // We just completed an OUT or INP cycle
+ cpudata_addr <= cpudata_addr + 1;
+ cpudata_ctr <= cpudata_ctr - 1;
+ // Turn off START COMMAND
+ main_status[7] <= 0;
+ // If this was the last byte, turn on busy
+ if ( cpudata_ctr == 1 )
+ main_status[0] <= 0;
+ end
+
+ // Set counters or status based on commands from controller CPU
+ if ( ~cpu_iorq_n & cpu_m1_n & ~cpu_wr_n & ~cpu_a[5] )
+ begin
+ casex ( cpu_a[2:0] )
+ 3'b0x0: // OUT 0x00
+ main_status <= cpu_do;
+ 3'b0x1: // OUT 0x01
+ aux_status <= cpu_do;
+ 3'b100: // OUT 0x04
+ cpudata_addr[7:0] <= cpu_do;
+ 3'b101: // OUT 0x05
+ begin
+ cpudata_addr[10:8] <= cpu_do[2:0];
+ cpudata_dir <= cpu_do[7];
+ end
+ 3'b11x: // OUT 0x06-0x07
+ cpudata_ctr <= { cpu_a[0], cpu_do };
+ endcase // casex( cpu_a[2:0] )
+ end
+
+ end // else: !if( ireset )
+ end // always @ (posedge ireset or posedge clk)
+
+ assign dma_status = { 6'b0, cpudata_dir, dma_active };
+
+
+ // ------------------------------------------------------------------------
+ // SD card interface
+ //
+ // This drives the SD card in SPI mode. We support two speeds:
+ // 12.5 MHz for normal operation, and 25 MHz/64 = 391 kHz for
+ // initialization.
+ //
+ // This is addressed by I/O with A5 = 1, and exports the following I/O
+ // ports, address bits can be combined:
+ //
+ // A0 write - loads the output shift register from the CPU
+ // A1 write - set speed (D0 = low speed) and CS# (D1, 1 = not selected)
+ // A2 - clear CRC registers
+ // A3 - select CRC register input (0 = input, 1 = output)
+ // A4 - start bus transaction
+ // On read, A[1:0]:
+ // 00 - read input latch
+ // 01 - read CRC7 (in D[7:1], D0 = 1)
+ // 10 - read CRC16[15:8]
+ // 11 - read CRC16[7:0]
+ // ------------------------------------------------------------------------
+
+ reg sd_data_out; // Output data register
+ reg [7:0] sd_shr_out;
+ reg [7:0] sd_shr_in;
+ reg [2:0] sd_out_ctr; // Output bit counter
+ reg sd_active; // Transfer in progress
+ reg sd_active_neg; // Transfer in progress, first pos clock seen
+ reg sd_cs_reg;
+ reg sd_slow;
+ reg [5:0] sd_clk_ctr; // Counter for the clock
+ reg sd_clk_out;
+ wire sd_clk_pos; // SD clock positive strobe
+ wire sd_clk_neg; // SD clock negative strobe
+ reg sd_crcsrc; // CRC generator input
+ reg sd_crcstb; // Strobe for CRC generator
+ reg [6:0] sd_crc7; // CRC-7 generator
+ reg [15:0] sd_crc16; // CRC-16 generator
+ wire sd_sel = ~cpu_iorq_n & cpu_m1_n & cpu_a[5];
+ wire sd_cmd = sd_sel & ~sd_active; // CPU command we can act on
+ reg sd_cmd_ok; // Valid CPU command received
+
+ // If we try an action while a bus transaction is in progress,
+ // wait. The register sd_cmd_ok is used to prevent WAIT# from
+ // being asserted when we already started a transaction on *this*
+ // I/O operation.
+ //
+ // sd_sel: 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0
+ // sd_active: 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
+ // sd_cmd: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
+ // sd_cmd_ok: 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0
+ // cpu_wait_n: 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1
+
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ sd_cmd_ok <= 1'b0;
+ else
+ sd_cmd_ok <= sd_sel & (~sd_active | sd_cmd_ok);
+
+ assign cpu_wait_n = ~(sd_sel & sd_active) | sd_cmd_ok;
+
+ // SD clock generator; this counter is used to generate the slow clock.
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ sd_clk_ctr <= 6'h00;
+ else
+ sd_clk_ctr <= sd_clk_ctr+1;
+
+ // Generate strobes from the sd_clk_ctr; this is defined to be 1
+ // in the internal cycle before sd_clk goes positive/negative.
+ wire ctr_pol = sd_slow ? sd_clk_ctr[5] : sd_clk_ctr[0];
+ wire ctr_val = ~sd_slow | &sd_clk_ctr[4:0];
+
+ assign sd_clk_pos = sd_active & ctr_val & ctr_pol;
+ assign sd_clk_neg = sd_active_neg & ctr_val & ~ctr_pol;
+
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ sd_clk_out <= 1'b0;
+ else
+ sd_clk_out <= (sd_clk_out | sd_clk_pos) & ~sd_clk_neg;
+
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ begin
+ sd_shr_out <= 8'hFF;
+ sd_cs_reg <= 1'b1;
+ sd_slow <= 1'b1;
+ sd_active <= 1'b0;
+ sd_active_neg <= 1'b0;
+ sd_out_ctr <= 3'h0;
+ sd_data_out <= 1'b1;
+ sd_crcstb <= 1'b0;
+ sd_shr_in <= 8'hxx;
+ sd_crcsrc <= 1'bx;
+ end
+ else
+ begin
+ if (sd_cmd)
+ begin
+ if (~cpu_wr_n & ~cpu_a[0])
+ sd_shr_out <= cpu_do;
+
+ if (~cpu_wr_n & cpu_a[1])
+ {sd_cs_reg, sd_slow} <= cpu_do[1:0];
+
+ if (cpu_a[4])
+ begin
+ sd_active <= 1'b1;
+ sd_out_ctr <= 3'h0; // Should be the case already
+ sd_crcsrc <= cpu_a[3];
+ end
+ end // if (sd_cmd)
+
+ if (sd_clk_pos)
+ begin
+ {sd_data_out, sd_shr_out} <= {sd_shr_out, 1'b1};
+ sd_active_neg <= 1'b1;
+ end
+ else if (sd_clk_neg)
+ begin
+ sd_shr_in <= {sd_shr_in[6:0], sd_di};
+ sd_out_ctr <= sd_out_ctr + 1;
+ sd_active <= ~&sd_out_ctr;
+ sd_active_neg <= ~&sd_out_ctr;
+ end
+ sd_crcstb <= sd_clk_neg; // CRCs are computed one cycle later
+ end
+
+ // CRC generators: we have one 7-bit and one 16-bit, shared between
+ // input and output. The controller CPU has to specify where it wants
+ // the input from by setting A3 properly when starting a bus
+ // transaction (A4 = 1).
+
+ wire sd_crcbit = sd_crcsrc ? sd_data_out : sd_shr_in[0];
+
+ wire sd_crc7in = sd_crcbit ^ sd_crc7[6];
+
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ sd_crc7 <= 7'h00;
+ else if (sd_cmd & cpu_a[2])
+ sd_crc7 <= 7'h00;
+ else if (sd_crcstb)
+ sd_crc7 <= {sd_crc7[5:3], sd_crc7[2]^sd_crc7in,
+ sd_crc7[1:0], sd_crc7in};
+
+ wire sd_crc16in = sd_crcbit ^ sd_crc16[15];
+
+ always @(posedge ireset or posedge clk)
+ if (ireset)
+ sd_crc16 <= 16'h0000;
+ else if (sd_cmd & cpu_a[2])
+ sd_crc16 <= 16'h0000;
+ else if (sd_crcstb)
+ sd_crc16 <= {sd_crc16[14:12], sd_crc16[11]^sd_crc16in,
+ sd_crc16[10:5], sd_crc16[4]^sd_crc16in,
+ sd_crc16[3:0], sd_crc16in};
+
+ // Data out to controller CPU
+
+ reg [7:0] sd_cpu_rd;
+ always @(*)
+ case (cpu_a[1:0])
+ 2'b00:
+ sd_cpu_rd = sd_shr_in;
+ 2'b01:
+ sd_cpu_rd = {sd_crc7, 1'b1};
+ 2'b10:
+ sd_cpu_rd = sd_crc16[15:8];
+ 2'b11:
+ sd_cpu_rd = sd_crc16[7:0];
+ endcase // case(cpu_a[1:0])
+
+ // ------------------------------------------------------------------------
+ // Controller CPU data select
+ // ------------------------------------------------------------------------
+
+ assign cpu_di =
+ {8{cpu_rd_n}} | // Always FF unless we're reading something
+ (({8{cpu_mreq_n}} | memrd) &
+ ({8{~sd_sel}} | sd_cpu_rd) &
+ ({8{~dma_stat_sel}} | dma_status));
+
+endmodule // cfcontroller
diff --git a/sound.v b/sound.v
index ca3154d..5bd4d0f 100644
--- a/sound.v
+++ b/sound.v
@@ -75,7 +75,8 @@ module vco(
endmodule // vco
//
-// Noise (e.g. random number) generator./
+// Noise (e.g. random number) generator. The periodicity is ~2 Hz,
+// which should be inaudible.
//
module noise(
input clk, // 25 MHz
diff --git a/tools/z80asm/Makefile b/tools/z80asm/Makefile
index a0a976d..b022c61 100644
--- a/tools/z80asm/Makefile
+++ b/tools/z80asm/Makefile
@@ -15,25 +15,35 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-CC = gcc
-LDFLAGS = -O2 -Wall
-CFLAGS = -O2 -Wall -Wwrite-strings -Wcast-qual -Wcast-align -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wredundant-decls -Wnested-externs -Winline -Wshadow -g -W -Ignulib
-SHELL = /bin/bash
-VERSION ?= $(shell echo -n `cat VERSION | cut -d. -f1`. ; echo $$[`cat VERSION | cut -d. -f2` + 1])
+CC = gcc
+LDFLAGS = -O2 -Wall
+CFLAGS = -O2 -Wall -Wwrite-strings -Wcast-qual -Wcast-align \
+ -Wstrict-prototypes -Wmissing-prototypes \
+ -Wmissing-declarations -Wredundant-decls -Wnested-externs \
+ -Winline -Wshadow -g -W -Ignulib
+VERSION ?= $(shell echo -n `cat VERSION | cut -d. -f1`. ; echo $$[`cat VERSION | cut -d. -f2` + 1])
+ifneq (,$(findstring _NT,$(shell uname -s)))
+O = obj
+X = .exe
+else
+O = o
+X =
+endif
-all:z80asm
+all: z80asm$(X)
-z80asm:z80asm.c Makefile gnulib/getopt.o gnulib/getopt1.o
- $(CC) $(CFLAGS) $(LDFLAGS) -DVERSION=\"$(shell cat VERSION)\" $< gnulib/getopt.o gnulib/getopt1.o -o $@
+z80asm$(X): z80asm.c Makefile gnulib/getopt.$(O) gnulib/getopt1.$(O)
+ $(CC) $(CFLAGS) $(LDFLAGS) -DVERSION=\"$(shell cat VERSION)\" \
+ $< gnulib/getopt.$(O) gnulib/getopt1.$(O) -o $@
-gnulib/%.o:gnulib/%.c gnulib/getopt.h Makefile
+gnulib/%.$(O): gnulib/%.c gnulib/getopt.h Makefile
$(CC) $(CFLAGS) -c $< -o $@
clean:
for i in . gnulib examples headers ; do \
- rm -f $$i/core $$i/*~ $$i/\#* $$i/*.o $$i/*.rom ; \
+ rm -f $$i/core $$i/*~ $$i/\#* $$i/*.$(O) $$i/*.rom ; \
done
- rm -f z80asm z80asm.exe
+ rm -f z80asm$(X) z80asm.exe
dist: clean
echo $(VERSION) > VERSION
diff --git a/upload.sh b/upload.sh
index e789d49..e789d49 100644..100755
--- a/upload.sh
+++ b/upload.sh