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authorH. Peter Anvin <hpa@zytor.com>2004-10-01 03:32:30 +0000
committerH. Peter Anvin <hpa@zytor.com>2004-10-01 03:32:30 +0000
commitf36a04a4dd6e6cf1a477c866d02786d93f7a69c3 (patch)
tree726655fe71f6cba1bdcc78c3018f9d1d5e979085
parent270140afe73e806a07cf86f51ad4ba2b020da96b (diff)
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Use enet chip address latching to reduce contention on the FSE address bus; it
seemed to occationally cause SRAM read errors.
-rwxr-xr-xabc80.qpf2
-rwxr-xr-xabc80.qsf2
-rw-r--r--abc80.v59
3 files changed, 43 insertions, 20 deletions
diff --git a/abc80.qpf b/abc80.qpf
index ef1d0e0..66e8cd8 100755
--- a/abc80.qpf
+++ b/abc80.qpf
@@ -21,7 +21,7 @@
QUARTUS_VERSION = "4.1"
-DATE = "01:00:16 September 29, 2004"
+DATE = "20:15:07 September 30, 2004"
# Revisions
diff --git a/abc80.qsf b/abc80.qsf
index 2a0ab90..db720bd 100755
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -347,6 +347,7 @@ set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
# Analysis & Synthesis Assignments
# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY abc80
set_global_assignment -name SPEED_DISK_USAGE_TRADEOFF SMART
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
@@ -355,7 +356,6 @@ set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name AUTO_ROM_RECOGNITION OFF
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
-set_global_assignment -name TOP_LEVEL_ENTITY abc80
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE on
diff --git a/abc80.v b/abc80.v
index 88fbd6a..51ffe50 100644
--- a/abc80.v
+++ b/abc80.v
@@ -406,27 +406,51 @@ module abc80 (
assign enet_oe_w = enet_selected & ~abc_in_n[0];
assign enet_we_w = enet_selected & (~abc_out_n[0] | ~abc_out_n[2]);
- always @(posedge fast_clk)
- begin
- // Delayed issues of WE# - to make sure the SRAM
- // doesn't latch data late
- sram_we_q1 <= sram_we_w;
- sram_we_q2 <= sram_we_q1;
+ wire enet_addr_w = enet_oe_w | enet_we_w;
+ reg enet_ads_q1;
+ reg enet_ads_q2;
- if ( enet_iochrdy )
- begin
- enet_oe_q <= enet_oe_w;
- enet_we_q1 <= enet_we_w;
- enet_we_q2 <= enet_we_q1;
- enet_we_q3 <= enet_we_q2;
- end
- end // always @ (posedge fast_clk)
+ assign enet_ads_n = enet_ads_q1;
+
+ always @(negedge rst_n or posedge fast_clk)
+ if ( ~rst_n )
+ begin
+ sram_we_q1 <= 0;
+ sram_we_q2 <= 0;
+
+ enet_ads_q1 <= 0;
+ enet_ads_q2 <= 0;
+ enet_oe_q <= 0;
+ enet_we_q1 <= 0;
+ enet_we_q2 <= 0;
+ enet_we_q3 <= 0;
+ end // if ( ~rst_n )
+ else
+ begin
+ // Delayed issues of WE# - to make sure the SRAM
+ // doesn't latch data late
+ sram_we_q1 <= sram_we_w;
+ sram_we_q2 <= sram_we_q1;
+
+ if ( enet_iochrdy )
+ begin
+ enet_ads_q1 <= enet_addr_w;
+ enet_ads_q2 <= enet_ads_q1;
+
+ enet_oe_q <= enet_oe_w;
+ enet_we_q1 <= enet_we_w;
+ enet_we_q2 <= enet_we_q1;
+ enet_we_q3 <= enet_we_q2;
+ end
+ end // else: !if( ~rst_n )
// Driving output pins...
- // Note: The SRAM is connected to FSE_A[19:2] only...
- assign fse_a = (~abc_out_n[0] | ~abc_in_n[0]) ?
+ // Note: The SRAM is connected to FSE_A[19:2] only.
+ // Note: For the Ethernet chip we use ADS# to latch the address, to
+ // make sure we don't miss setup for the next SRAM cycle.
+ assign fse_a = (~enet_ads_q2 & enet_selected & ~abc_out_n[0] | ~abc_in_n[0]) ?
{ 19'h00030, enet_address[3:1], 1'b0 } :
- (~abc_out_n[2]) ?
+ (~enet_ads_q2 & enet_selected & ~abc_out_n[2]) ?
{ 19'h00030, 4'b1110 } :
{ 3'b000, mmu_a[19:2], 2'b00 };
@@ -462,7 +486,6 @@ module abc80 (
sram_do = fse_d[31:24];
endcase // case( mmu_a[1:0] )
- assign enet_ads_n = 0; // Don't use address data strobing
assign enet_cycle_n = 1; // Don't use EISA burst mode
assign enet_rdyrtn_n = 1; // Not using synchronous bursting
assign enet_datacs_n = 1; // Not using synchronous bursting