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authorH. Peter Anvin <hpa@zytor.com>2003-07-10 04:04:48 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2003-07-10 04:04:48 (GMT)
commit412fce2ec525e78a1cf5a6fd61e92c600b175de6 (patch)
treec4fa876bf4cfecb262554661785c21bac7eba2b4
downloadvideotest-master.zip
videotest-master.tar.gz
videotest-master.tar.bz2
videotest-master.tar.xz
Simple test of Lancelot video outputHEADoriginmaster
-rw-r--r--mypll1.bsf117
-rw-r--r--mypll1.cmp32
-rw-r--r--mypll1.inc33
-rw-r--r--mypll1.v216
-rw-r--r--mypll1_bb.v37
-rw-r--r--mypll1_inst.v8
-rw-r--r--videotest.csf494
-rw-r--r--videotest.quartus19
-rw-r--r--videotest.v142
9 files changed, 1098 insertions, 0 deletions
diff --git a/mypll1.bsf b/mypll1.bsf
new file mode 100644
index 0000000..40fc327
--- /dev/null
+++ b/mypll1.bsf
@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 280 184)
+ (text "mypll1" (rect 140 0 181 16)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 168 24 180)(font "Arial" ))
+ (port
+ (pt 0 64)
+ (input)
+ (text "inclk0" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 48 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "pllena" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "pllena" (rect 4 67 34 80)(font "Arial" (font_size 8)))
+ (line (pt 0 80)(pt 48 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "areset" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "areset" (rect 4 83 32 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 48 96)(line_width 1))
+ )
+ (port
+ (pt 280 64)
+ (output)
+ (text "c0" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 265 51 276 64)(font "Arial" (font_size 8)))
+ (line (pt 280 64)(pt 248 64)(line_width 1))
+ )
+ (port
+ (pt 280 80)
+ (output)
+ (text "c1" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c1" (rect 265 67 276 80)(font "Arial" (font_size 8)))
+ (line (pt 280 80)(pt 248 80)(line_width 1))
+ )
+ (port
+ (pt 280 96)
+ (output)
+ (text "e0" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "e0" (rect 265 83 277 96)(font "Arial" (font_size 8)))
+ (line (pt 280 96)(pt 248 96)(line_width 1))
+ )
+ (drawing
+ (text "inclk0 frequency: 50.000 MHz" (rect 58 59 183 71)(font "Arial" ))
+ (text "Operation Mode: Normal" (rect 58 73 159 85)(font "Arial" ))
+ (text "Clk " (rect 59 96 76 108)(font "Arial" ))
+ (text "Ratio" (rect 81 96 103 108)(font "Arial" ))
+ (text "Ph (dg)" (rect 108 96 138 108)(font "Arial" ))
+ (text "Td (ns)" (rect 143 96 172 108)(font "Arial" ))
+ (text "DC (%)" (rect 177 96 208 108)(font "Arial" ))
+ (text "c0" (rect 62 111 72 123)(font "Arial" ))
+ (text "4/1" (rect 86 111 99 123)(font "Arial" ))
+ (text "0.00" (rect 114 111 132 123)(font "Arial" ))
+ (text "0.00" (rect 148 111 166 123)(font "Arial" ))
+ (text "50.00" (rect 181 111 204 123)(font "Arial" ))
+ (text "c1" (rect 62 126 72 138)(font "Arial" ))
+ (text "1/2" (rect 86 126 99 138)(font "Arial" ))
+ (text "0.00" (rect 114 126 132 138)(font "Arial" ))
+ (text "0.00" (rect 148 126 166 138)(font "Arial" ))
+ (text "50.00" (rect 181 126 204 138)(font "Arial" ))
+ (text "e0" (rect 62 141 72 153)(font "Arial" ))
+ (text "1/2" (rect 86 141 99 153)(font "Arial" ))
+ (text "0.00" (rect 114 141 132 153)(font "Arial" ))
+ (text "0.00" (rect 148 141 166 153)(font "Arial" ))
+ (text "50.00" (rect 181 141 204 153)(font "Arial" ))
+ (line (pt 0 0)(pt 281 0)(line_width 1))
+ (line (pt 281 0)(pt 281 185)(line_width 1))
+ (line (pt 0 185)(pt 281 185)(line_width 1))
+ (line (pt 0 0)(pt 0 185)(line_width 1))
+ (line (pt 56 94)(pt 210 94)(line_width 1))
+ (line (pt 56 108)(pt 210 108)(line_width 1))
+ (line (pt 56 123)(pt 210 123)(line_width 1))
+ (line (pt 56 138)(pt 210 138)(line_width 1))
+ (line (pt 56 153)(pt 210 153)(line_width 1))
+ (line (pt 56 94)(pt 56 153)(line_width 1))
+ (line (pt 78 94)(pt 78 153)(line_width 3))
+ (line (pt 105 94)(pt 105 153)(line_width 3))
+ (line (pt 140 94)(pt 140 153)(line_width 3))
+ (line (pt 174 94)(pt 174 153)(line_width 3))
+ (line (pt 209 94)(pt 209 153)(line_width 1))
+ (line (pt 48 48)(pt 248 48)(line_width 1))
+ (line (pt 248 48)(pt 248 168)(line_width 1))
+ (line (pt 48 168)(pt 248 168)(line_width 1))
+ (line (pt 48 48)(pt 48 168)(line_width 1))
+ )
+)
diff --git a/mypll1.cmp b/mypll1.cmp
new file mode 100644
index 0000000..3edd9f5
--- /dev/null
+++ b/mypll1.cmp
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component mypll1
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ pllena : IN STD_LOGIC := '1';
+ areset : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ e0 : OUT STD_LOGIC
+ );
+end component;
diff --git a/mypll1.inc b/mypll1.inc
new file mode 100644
index 0000000..8883492
--- /dev/null
+++ b/mypll1.inc
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION mypll1
+(
+ inclk0,
+ pllena,
+ areset
+)
+
+RETURNS (
+ c0,
+ c1,
+ e0
+);
diff --git a/mypll1.v b/mypll1.v
new file mode 100644
index 0000000..fe144e0
--- /dev/null
+++ b/mypll1.v
@@ -0,0 +1,216 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: mypll1.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module mypll1 (
+ inclk0,
+ pllena,
+ areset,
+ c0,
+ c1,
+ e0);
+
+ input inclk0;
+ input pllena;
+ input areset;
+ output c0;
+ output c1;
+ output e0;
+
+ wire [5:0] sub_wire0;
+ wire [3:0] sub_wire3;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire [0:0] sub_wire4 = sub_wire3[0:0];
+ wire e0 = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .pllena (pllena),
+ .areset (areset),
+ .clk (sub_wire0),
+ .extclk (sub_wire3));
+ defparam
+ altpll_component.clk1_divide_by = 2,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.clk0_multiply_by = 4,
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.extclk0_duty_cycle = 50,
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.extclk0_phase_shift = "0",
+ altpll_component.extclk0_divide_by = 2,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.pll_type = "AUTO",
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk0_time_delay = "0",
+ altpll_component.extclk0_time_delay = "0",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.extclk0_multiply_by = 1,
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk1_time_delay = "0",
+ altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: JUMP2PAGE0 STRING ""
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: JUMP2PAGE1 STRING "General/Modes"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
+// Retrieval info: PRIVATE: JUMP2PAGE2 STRING "General/Modes"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
+// Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
+// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
+// Retrieval info: PRIVATE: TIME_SHIFT6 STRING "0.00000000"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: JUMP2PAGE STRING "Clock switchover"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "2"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: EXTCLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: EXTCLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: EXTCLK0_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: EXTCLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: EXTCLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: USED_PORT: e0 0 0 0 0 OUTPUT VCC "e0"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: e0 0 0 0 0 @extclk 0 0 1 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
diff --git a/mypll1_bb.v b/mypll1_bb.v
new file mode 100644
index 0000000..e2845fb
--- /dev/null
+++ b/mypll1_bb.v
@@ -0,0 +1,37 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module mypll1 (
+ inclk0,
+ pllena,
+ areset,
+ c0,
+ c1,
+ e0);
+
+ input inclk0;
+ input pllena;
+ input areset;
+ output c0;
+ output c1;
+ output e0;
+
+endmodule
+
diff --git a/mypll1_inst.v b/mypll1_inst.v
new file mode 100644
index 0000000..4ae16cf
--- /dev/null
+++ b/mypll1_inst.v
@@ -0,0 +1,8 @@
+mypll1 mypll1_inst (
+ .inclk0 ( inclk0_sig ),
+ .pllena ( pllena_sig ),
+ .areset ( areset_sig ),
+ .c0 ( c0_sig ),
+ .c1 ( c1_sig ),
+ .e0 ( e0_sig )
+ );
diff --git a/videotest.csf b/videotest.csf
new file mode 100644
index 0000000..c5e743e
--- /dev/null
+++ b/videotest.csf
@@ -0,0 +1,494 @@
+COMPILER_SETTINGS
+{
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ INITIAL_PLACEMENT_CONFIGURATION = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_AUTO_ASSIGN = 0;
+ SIGNALPROBE_COMPILATION = OFF;
+ SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
+ RUN_FITTER_IN_SIGNALPROBE_MODE = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = NORMAL_COMPILATION;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = ON;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |videotest;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CLOCK_DIVISOR = 1;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = sld_hub_inst;
+ HUB_ENTITY_NAME = sld_hub;
+}
+CHIP(videotest)
+{
+ DEVICE = EP1C20F400C7;
+ DEVICE_FILTER_PACKAGE = ANY;
+ DEVICE_FILTER_PIN_COUNT = ANY;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = ON;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ CLOCK_SOURCE = INTERNAL;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ clkin : LOCATION = Pin_K5;
+ proto1_clkout : LOCATION = Pin_K6;
+ proto2_clkout : LOCATION = Pin_K14;
+ pld_clkout : LOCATION = Pin_L8;
+ pld_clkfb : LOCATION = Pin_L14;
+ sd_clk : LOCATION = Pin_L13;
+ vga_r[0] : LOCATION = Pin_U12;
+ vga_r[1] : LOCATION = Pin_V12;
+ vga_r[2] : LOCATION = Pin_T13;
+ vga_r[3] : LOCATION = Pin_R13;
+ vga_r[4] : LOCATION = Pin_Y13;
+ vga_r[5] : LOCATION = Pin_W13;
+ vga_r[6] : LOCATION = Pin_U13;
+ vga_r[7] : LOCATION = Pin_V13;
+ vga_g[0] : LOCATION = Pin_T15;
+ vga_g[1] : LOCATION = Pin_W15;
+ vga_g[2] : LOCATION = Pin_Y15;
+ vga_g[3] : LOCATION = Pin_U15;
+ vga_g[4] : LOCATION = Pin_V15;
+ vga_g[5] : LOCATION = Pin_V14;
+ vga_g[6] : LOCATION = Pin_U14;
+ vga_g[7] : LOCATION = Pin_Y14;
+ vga_b[0] : LOCATION = Pin_T12;
+ vga_b[1] : LOCATION = Pin_T11;
+ vga_b[2] : LOCATION = Pin_W12;
+ vga_b[4] : LOCATION = Pin_Y12;
+ vga_b[3] : LOCATION = Pin_W8;
+ vga_b[5] : LOCATION = Pin_Y8;
+ vga_b[6] : LOCATION = Pin_V9;
+ vga_b[7] : LOCATION = Pin_U9;
+ vga_hs : LOCATION = Pin_T9;
+ vga_vs : LOCATION = Pin_R9;
+ vga_blank_n : LOCATION = Pin_R14;
+ vga_sync_n : LOCATION = Pin_T14;
+ vga_sync_t : LOCATION = Pin_W14;
+ vga_m1 : LOCATION = Pin_V11;
+ vga_m2 : LOCATION = Pin_U11;
+ audio_l : LOCATION = Pin_W9;
+ audio_r : LOCATION = Pin_U10;
+ ps2_sel : LOCATION = Pin_W10;
+ ps2_kclk : LOCATION = Pin_Y10;
+ ps2_kdata : LOCATION = Pin_V10;
+ ps2_mclk : LOCATION = Pin_T10;
+ ps2_mdata : LOCATION = Pin_Y9;
+ cf_d[3] : LOCATION = Pin_F18;
+ cf_d[4] : LOCATION = Pin_E17;
+ cf_d[5] : LOCATION = Pin_D17;
+ cf_d[6] : LOCATION = Pin_D18;
+ cf_d[7] : LOCATION = Pin_C18;
+ cf_ce_n : LOCATION = Pin_H20;
+ cf_a[10] : LOCATION = Pin_J15;
+ cf_oe_n : LOCATION = Pin_D13;
+ cf_a[9] : LOCATION = Pin_J20;
+ cf_a[8] : LOCATION = Pin_H14;
+ cf_a[7] : LOCATION = Pin_J14;
+ cf_a[6] : LOCATION = Pin_J17;
+ cf_a[5] : LOCATION = Pin_J18;
+ cf_a[4] : LOCATION = Pin_K15;
+ cf_a[3] : LOCATION = Pin_W18;
+ cf_a[2] : LOCATION = Pin_H19;
+ cf_a[1] : LOCATION = Pin_H18;
+ cf_a[0] : LOCATION = Pin_H17;
+ cf_d[0] : LOCATION = Pin_E19;
+ cf_d[1] : LOCATION = Pin_F15;
+ cf_d[2] : LOCATION = Pin_E19;
+ cf_wp : LOCATION = Pin_H16;
+ cf_cd1_n : LOCATION = Pin_B13;
+ cf_d[11] : LOCATION = Pin_F17;
+ cf_d[12] : LOCATION = Pin_E18;
+ cf_d[13] : LOCATION = Pin_F16;
+ cf_d[14] : LOCATION = Pin_F19;
+ cf_d[15] : LOCATION = Pin_G16;
+ cf_ce2_n : LOCATION = Pin_U19;
+ cf_oiord_n : LOCATION = Pin_G19;
+ cf_iown_n : LOCATION = Pin_G20;
+ cf_we_n : LOCATION = Pin_V18;
+ cf_rdy : LOCATION = Pin_G17;
+ cf_wait_n : LOCATION = Pin_G14;
+ cf_inpack_n : LOCATION = Pin_V19;
+ cf_reg_n : LOCATION = Pin_U20;
+ cf_bvd2 : LOCATION = Pin_J16;
+ cf_bvd1 : LOCATION = Pin_J19;
+ cf_d[8] : LOCATION = Pin_C19;
+ cf_d[9] : LOCATION = Pin_D19;
+ cf_d[10] : LOCATION = Pin_D20;
+ sd_a[0] : LOCATION = Pin_M2;
+ sd_a[1] : LOCATION = Pin_M1;
+ sd_a[2] : LOCATION = Pin_M6;
+ sd_a[3] : LOCATION = Pin_M4;
+ sd_a[4] : LOCATION = Pin_J8;
+ sd_a[5] : LOCATION = Pin_J7;
+ sd_a[6] : LOCATION = Pin_J6;
+ sd_a[7] : LOCATION = Pin_J5;
+ sd_a[8] : LOCATION = Pin_J4;
+ sd_a[9] : LOCATION = Pin_J3;
+ sd_a[10] : LOCATION = Pin_H6;
+ sd_a[11] : LOCATION = Pin_H5;
+ sd_ba[0] : LOCATION = Pin_H7;
+ sd_ba[1] : LOCATION = Pin_H1;
+ sd_dq[0] : LOCATION = Pin_M5;
+ sd_dq[1] : LOCATION = Pin_M3;
+ sd_dq[2] : LOCATION = Pin_M7;
+ sd_dq[3] : LOCATION = Pin_N6;
+ sd_dq[4] : LOCATION = Pin_N1;
+ sd_dq[5] : LOCATION = Pin_N2;
+ sd_dq[6] : LOCATION = Pin_N4;
+ sd_dq[7] : LOCATION = Pin_N3;
+ sd_dq[8] : LOCATION = Pin_N5;
+ sd_dq[9] : LOCATION = Pin_N7;
+ sd_dq[10] : LOCATION = Pin_P7;
+ sd_dq[11] : LOCATION = Pin_P2;
+ sd_dq[12] : LOCATION = Pin_P1;
+ sd_dq[13] : LOCATION = Pin_P6;
+ sd_dq[14] : LOCATION = Pin_P5;
+ sd_dq[15] : LOCATION = Pin_P3;
+ sd_dq[16] : LOCATION = Pin_P4;
+ sd_dq[17] : LOCATION = Pin_R1;
+ sd_dq[18] : LOCATION = Pin_R2;
+ sd_dq[19] : LOCATION = Pin_R6;
+ sd_dq[20] : LOCATION = Pin_R5;
+ sd_dq[21] : LOCATION = Pin_R3;
+ sd_dq[22] : LOCATION = Pin_R4;
+ sd_dq[23] : LOCATION = Pin_T4;
+ sd_dq[24] : LOCATION = Pin_T2;
+ sd_dq[25] : LOCATION = Pin_T3;
+ sd_dq[26] : LOCATION = Pin_U1;
+ sd_dq[27] : LOCATION = Pin_U4;
+ sd_dq[28] : LOCATION = Pin_U2;
+ sd_dq[29] : LOCATION = Pin_U3;
+ sd_dq[30] : LOCATION = Pin_V3;
+ sd_dq[31] : LOCATION = Pin_V2;
+ sd_dqm[0] : LOCATION = Pin_J2;
+ sd_dqm[1] : LOCATION = Pin_J1;
+ sd_dqm[2] : LOCATION = Pin_H4;
+ sd_dqm[3] : LOCATION = Pin_H3;
+ sd_ras_n : LOCATION = Pin_H2;
+ sd_cas_n : LOCATION = Pin_G3;
+ sd_cke : LOCATION = Pin_G7;
+ sd_cs_n : LOCATION = Pin_G6;
+ sd_we_n : LOCATION = Pin_G4;
+ p1_a17 : LOCATION = Pin_F20;
+ p1_a21 : LOCATION = Pin_G15;
+ p1_a28 : LOCATION = Pin_H15;
+ p1_a29 : LOCATION = Pin_G18;
+ p1_a38 : LOCATION = Pin_U18;
+ p1_clkout : LOCATION = Pin_P27;
+ ttya_dcd : LOCATION = Pin_M16;
+ ttya_txd : LOCATION = Pin_M14;
+ ttya_rxd : LOCATION = Pin_K16;
+ ttya_dtr : LOCATION = Pin_M15;
+ ttya_dsr : LOCATION = Pin_M20;
+ ttya_rts : LOCATION = Pin_K19;
+ ttya_cts : LOCATION = Pin_J13;
+ ttya_ri : LOCATION = Pin_M19;
+ ttyb_txd : LOCATION = Pin_A13;
+ ttyb_rxd : LOCATION = Pin_C13;
+ s7_0[0] : LOCATION = Pin_U6;
+ s7_0[1] : LOCATION = Pin_V6;
+ s7_0[2] : LOCATION = Pin_W7;
+ s7_0[3] : LOCATION = Pin_Y7;
+ s7_0[4] : LOCATION = Pin_R7;
+ s7_0[5] : LOCATION = Pin_T8;
+ s7_0[6] : LOCATION = Pin_V7;
+ s7_0[7] : LOCATION = Pin_U7;
+ s7_1[0] : LOCATION = Pin_T5;
+ s7_1[1] : LOCATION = Pin_U5;
+ s7_1[2] : LOCATION = Pin_V5;
+ s7_1[3] : LOCATION = Pin_W5;
+ s7_1[4] : LOCATION = Pin_T6;
+ s7_1[5] : LOCATION = Pin_T7;
+ s7_1[6] : LOCATION = Pin_W6;
+ s7_1[7] : LOCATION = Pin_Y6;
+ led[0] : LOCATION = Pin_E14;
+ led[1] : LOCATION = Pin_E13;
+ led[2] : LOCATION = Pin_C14;
+ led[3] : LOCATION = Pin_D14;
+ led[4] : LOCATION = Pin_E12;
+ led[5] : LOCATION = Pin_F12;
+ led[6] : LOCATION = Pin_B3;
+ led[7] : LOCATION = Pin_B14;
+ sw[0] : LOCATION = Pin_W3;
+ sw[1] : LOCATION = Pin_Y4;
+ sw[2] : LOCATION = Pin_V4;
+ sw[3] : LOCATION = Pin_W4;
+ fse_a[0] : LOCATION = Pin_B4;
+ fse_a[1] : LOCATION = Pin_A4;
+ fse_a[2] : LOCATION = Pin_D5;
+ fse_a[3] : LOCATION = Pin_D6;
+ fse_a[4] : LOCATION = Pin_C5;
+ fse_a[5] : LOCATION = Pin_B5;
+ fse_a[6] : LOCATION = Pin_C2;
+ fse_a[7] : LOCATION = Pin_D2;
+ fse_a[8] : LOCATION = Pin_D4;
+ fse_a[9] : LOCATION = Pin_D1;
+ fse_a[10] : LOCATION = Pin_E4;
+ fse_a[11] : LOCATION = Pin_E5;
+ fse_a[12] : LOCATION = Pin_F3;
+ fse_a[13] : LOCATION = Pin_E3;
+ fse_a[14] : LOCATION = Pin_E2;
+ fse_a[15] : LOCATION = Pin_F4;
+ fse_a[16] : LOCATION = Pin_F5;
+ fse_a[17] : LOCATION = Pin_F2;
+ fse_a[18] : LOCATION = Pin_F1;
+ fse_a[19] : LOCATION = Pin_F6;
+ fse_a[20] : LOCATION = Pin_G5;
+ fse_a[21] : LOCATION = Pin_G1;
+ fse_a[22] : LOCATION = Pin_G2;
+ fse_d[0] : LOCATION = Pin_C6;
+ fse_d[1] : LOCATION = Pin_E6;
+ fse_d[2] : LOCATION = Pin_B6;
+ fse_d[3] : LOCATION = Pin_A6;
+ fse_d[4] : LOCATION = Pin_F7;
+ fse_d[5] : LOCATION = Pin_E7;
+ fse_d[6] : LOCATION = Pin_B7;
+ fse_d[7] : LOCATION = Pin_A7;
+ fse_d[8] : LOCATION = Pin_D7;
+ fse_d[9] : LOCATION = Pin_C7;
+ fse_d[10] : LOCATION = Pin_F8;
+ fse_d[11] : LOCATION = Pin_E8;
+ fse_d[12] : LOCATION = Pin_B8;
+ fse_d[13] : LOCATION = Pin_A8;
+ fse_d[14] : LOCATION = Pin_D8;
+ fse_d[15] : LOCATION = Pin_C8;
+ fse_d[16] : LOCATION = Pin_B9;
+ fse_d[17] : LOCATION = Pin_A9;
+ fse_d[18] : LOCATION = Pin_D9;
+ fse_d[19] : LOCATION = Pin_C9;
+ fse_d[20] : LOCATION = Pin_E9;
+ fse_d[21] : LOCATION = Pin_E10;
+ fse_d[22] : LOCATION = Pin_B10;
+ fse_d[23] : LOCATION = Pin_A10;
+ fse_d[24] : LOCATION = Pin_F10;
+ fse_d[25] : LOCATION = Pin_C10;
+ fse_d[26] : LOCATION = Pin_D10;
+ fse_d[27] : LOCATION = Pin_C11;
+ fse_d[28] : LOCATION = Pin_D11;
+ fse_d[29] : LOCATION = Pin_B11;
+ fse_d[30] : LOCATION = Pin_A11;
+ fse_d[31] : LOCATION = Pin_E11;
+ flash_cs_n : LOCATION = Pin_A12;
+ flash_oe_n : LOCATION = Pin_B12;
+ flash_rw_n : LOCATION = Pin_D12;
+ flash_ry_by_n : LOCATION = Pin_C12;
+ sram_be_n[0] : LOCATION = Pin_V17;
+ sram_be_n[1] : LOCATION = Pin_V16;
+ sram_be_n[2] : LOCATION = Pin_W16;
+ sram_be_n[3] : LOCATION = Pin_T16;
+ sram_cs_n : LOCATION = Pin_W17;
+ sram_oe_n : LOCATION = Pin_Y17;
+ sram_we_n : LOCATION = Pin_U16;
+ enet_ads_n : LOCATION = Pin_A14;
+ enet_aen : LOCATION = Pin_B15;
+ enet_be_n[0] : LOCATION = Pin_C16;
+ enet_be_n[1] : LOCATION = Pin_B16;
+ enet_be_n[2] : LOCATION = Pin_D16;
+ enet_be_n[3] : LOCATION = Pin_E16;
+ enet_cycle_n : LOCATION = Pin_B17;
+ enet_datacs_n : LOCATION = Pin_C15;
+ enet_intrq0 : LOCATION = Pin_D15;
+ enet_iochrdy : LOCATION = Pin_F14;
+ enet_ior_n : LOCATION = Pin_A15;
+ enet_iow_n : LOCATION = Pin_E15;
+ enet_lclk : LOCATION = Pin_C17;
+ enet_ldev_n : LOCATION = Pin_D3;
+ enet_rdyrtn_n : LOCATION = Pin_B18;
+ enet_w_r_n : LOCATION = Pin_A17;
+}
diff --git a/videotest.quartus b/videotest.quartus
new file mode 100644
index 0000000..5a2eb06
--- /dev/null
+++ b/videotest.quartus
@@ -0,0 +1,19 @@
+COMPILER_SETTINGS_LIST
+{
+ COMPILER_SETTINGS = videotest;
+}
+SIMULATOR_SETTINGS_LIST
+{
+ SIMULATOR_SETTINGS = videotest;
+}
+SOFTWARE_SETTINGS_LIST
+{
+ SOFTWARE_SETTINGS = Debug;
+ SOFTWARE_SETTINGS = Release;
+}
+FILES
+{
+ VERILOG_FILE = videotest.v;
+ VERILOG_FILE = mypll1.v;
+ CDF_FILE = Chain1.cdf;
+}
diff --git a/videotest.v b/videotest.v
new file mode 100644
index 0000000..653b129
--- /dev/null
+++ b/videotest.v
@@ -0,0 +1,142 @@
+//
+// videotest.v
+//
+// Simple VGA graphics generator
+//
+// We use the standard VGA "text" monitor timings mode,
+// htime = 31.77 us (31.47 kHz), vtime = 14.27 ms (70 Hz)
+// The standard VGA uses a pixel clock of 25.175 MHz, we use 25 MHz,
+// and round to multiples of 8. The error is about 0.8%, which
+// is far, far less than the margin of error in real systems.
+//
+// This gives us the following timings:
+// Horizontal: 96 pixels (12 char) sync
+// 48 pixels ( 6 char) back porch/border
+// 640 pixels (80 char) graphics
+// 16 pixels ( 2 char) front porch
+// Vertical: 2 lines sync
+// 41 lines back porch/border
+// 384 lines graphics (24 rows @ 16 pixels)
+// 22 lines front porch
+//
+// The DAC used introduced in the Lancelot card introduces
+// 8 cycles of delay.
+//
+
+module videotest (
+ clkin, // PLL input clock
+ pld_clkout, // Clock to Lancelot board
+ vga_m1,
+ vga_m2,
+ vga_r,
+ vga_g,
+ vga_b,
+ vga_sync_n,
+ vga_sync_t,
+ vga_blank_n,
+ vga_hs,
+ vga_vs,
+
+ led
+ );
+
+ input clkin;
+ output pld_clkout;
+
+ output [7:0] vga_r;
+ output [7:0] vga_g;
+ output [7:0] vga_b;
+ output vga_m1;
+ output vga_m2;
+ output vga_sync_n;
+ output vga_sync_t;
+ output vga_blank_n;
+ output vga_hs;
+ output vga_vs;
+
+ output [7:0] led;
+
+ wire clk; // 25 MHz clock from PLL
+
+ wire [9:0] x_blank = 640+8;
+ wire [9:0] x_sync = x_blank+24;
+ wire [9:0] x_back = x_sync+96;
+ wire [9:0] x_max = x_back+40;
+ wire [8:0] y_blank = 384;
+ wire [8:0] y_sync = y_blank+22;
+ wire [8:0] y_back = y_sync+2;
+ wire [8:0] y_max = y_back+41;
+
+ wire hsync_neg = 1; // Negative hsync
+ wire vsync_neg = 0; // Positive vsync
+
+ reg [9:0] x;
+ reg [8:0] y;
+ reg [7:0] frame_ctr;
+
+ wire xvideo = (x < x_blank);
+ wire yvideo = (y < y_blank);
+
+ assign vga_sync_t = 0; // No sync-on-RGB
+ assign vga_sync_n = 1;
+
+ assign vga_m1 = 0; // Color space configuration: GBR
+ assign vga_m2 = 0;
+
+ wire pll_clk0; // 200 MHz clock (unused)
+
+ // e0 and c1 are both 25 MHz clocks with the same phase, but pld_clkout
+ // is a dedicated pin for pll1.e0
+ mypll1 my_pll1 (
+ .inclk0( clkin ),
+ .pllena( 1 ),
+ .areset( 0 ),
+ .c0( pll_clk0 ),
+ .c1( clk ),
+ .e0( pld_clkout )
+ );
+
+ always @( posedge clk )
+ begin
+ if ( xvideo & yvideo )
+ begin
+ vga_r <= x[7:0];
+ vga_g[7:6] <= x[9:8];
+ vga_b <= y[7:0];
+ vga_g[5] <= y[8];
+ vga_g[4:0] <= 0;
+
+ vga_blank_n <= 1; // Inverse logic
+ end
+ else
+ begin
+ vga_r <= 8'bx;
+ vga_g <= 8'bx;
+ vga_b <= 8'bx;
+
+ vga_blank_n <= 0;
+ end
+
+ vga_hs <= ( x >= x_sync && x < x_back ) ^ vsync_neg;
+ vga_vs <= ( y >= y_sync && y < y_back ) ^ hsync_neg;
+
+ if ( x == x_max-1 )
+ begin
+ x <= 0;
+ if ( y == y_max-1 )
+ begin
+ y <= 0;
+ frame_ctr <= frame_ctr + 1;
+ end
+ else
+ y <= y+1;
+ end
+ else
+ x <= x+1;
+ end // always @ ( posedge clk )
+
+ // Flash LEDs for the hell of it
+ always @( posedge clk )
+ led <= (1 << frame_ctr[7:5]);
+
+endmodule // videotest