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# Global clocks
#
# The clock routing on the NIOS board is a little confusing once you mix
# in all the internal and external requirements.  This is how it interacts
# with all the PLLs; see also fig 2-16 of the Cyclone manual vol 1.
#
# Each PLL has two inputs (dedicated pins) and three outputs; two that
# go to the internal clock trees (c0, c1) and one which goes to a
# dedicated pin (e0).
#                         +-------------------------------+
#    50 MHz --- clkin --> |>CLK0 ==\ c0->   <-c0 /== CLK2<| <-- pld_clkfb ----+
#    proto1_clkout -----> |>CLK1 PLL1           PLL2 CLK3<| <-- proto2_clkout |
#    +--- pld_clkout ---- | <-e0 ==/ c1->   <-c1 \== e0-> | --> sd_clk(SDRAM) |
#    |                    +-------------------------------+                   |
#    +----------------------------+-------------------------------------------+
#                                 |
#                                 +---> proto1_clkin, proto2_clkin, nmd_clkin
#
# The Lancelot card sits on PROTO2, and proto2_clkin is the default
# Lancelot DAC clock.
#
k5 clkin
k6 proto1_clkout
k14 proto2_clkout
l8 pld_clkout
l14 pld_clkfb
l13 sd_clk
# Global reset (can also be configured as DEV_CLRn)
c4 reset_n
# Lancelot VGA
u12 vga_r[0]
v12 vga_r[1]
t13 vga_r[2]
r13 vga_r[3]
y13 vga_r[4]
w13 vga_r[5]
u13 vga_r[6]
v13 vga_r[7]
t15 vga_g[0]
w15 vga_g[1]
y15 vga_g[2]
u15 vga_g[3]
v15 vga_g[4]
v14 vga_g[5]
u14 vga_g[6]
y14 vga_g[7]
t12 vga_b[0]
t11 vga_b[1]
w12 vga_b[2]
y12 vga_b[4]
w8 vga_b[3]
y8 vga_b[5]
v9 vga_b[6]
u9 vga_b[7]
t9 vga_hs
r9 vga_vs
r14 vga_blank_n
t14 vga_sync_n
w14 vga_sync_t
v11 vga_m1
u11 vga_m2
# Lancelot audio
w9 audio_l
u10 audio_r
# Lancelot keyboard/mouse
w10 ps2_sel
y10 ps2_kclk
v10 ps2_kdata
t10 ps2_mclk
y9 ps2_mdata
# CompactFlash connector
m13 cf_power
f18 cf_d[3]
e17 cf_d[4]
d17 cf_d[5]
d18 cf_d[6]
c18 cf_d[7]
h20 cf_ce1_n
j15 cf_a[10]
d13 cf_oe_n
j20 cf_a[9]
h14 cf_a[8]
j14 cf_a[7]
j17 cf_a[6]
j18 cf_a[5]
k15 cf_a[4]
w18 cf_a[3]
h19 cf_a[2]
h18 cf_a[1]
h17 cf_a[0]
f20 cf_d[0]
f15 cf_d[1]
e19 cf_d[2]
h16 cf_wp
b13 cf_cd1_n
f17 cf_d[11]
e18 cf_d[12]
f16 cf_d[13]
f19 cf_d[14]
g16 cf_d[15]
u19 cf_ce2_n
g19 cf_iord_n
g20 cf_iowr_n
v18 cf_we_n
g17 cf_rdy
g14 cf_wait_n
v19 cf_inpack_n
u20 cf_reg_n
j16 cf_bvd2
j19 cf_bvd1
c19 cf_d[8]
d19 cf_d[9]
d20 cf_d[10]
m2 sd_a[0]
m1 sd_a[1]
m6 sd_a[2]
m4 sd_a[3]
j8 sd_a[4]
j7 sd_a[5]
j6 sd_a[6]
j5 sd_a[7]
j4 sd_a[8]
j3 sd_a[9]
h6 sd_a[10]
h5 sd_a[11]
h7 sd_ba[0]
h1 sd_ba[1]
m5 sd_dq[0]
m3 sd_dq[1]
m7 sd_dq[2]
n6 sd_dq[3]
n1 sd_dq[4]
n2 sd_dq[5]
n4 sd_dq[6]
n3 sd_dq[7]
n5 sd_dq[8]
n7 sd_dq[9]
p7 sd_dq[10]
p2 sd_dq[11]
p1 sd_dq[12]
p6 sd_dq[13]
p5 sd_dq[14]
p3 sd_dq[15]
p4 sd_dq[16]
r1 sd_dq[17]
r2 sd_dq[18]
r6 sd_dq[19]
r5 sd_dq[20]
r3 sd_dq[21]
r4 sd_dq[22]
t4 sd_dq[23]
t2 sd_dq[24]
t3 sd_dq[25]
u1 sd_dq[26]
u4 sd_dq[27]
u2 sd_dq[28]
u3 sd_dq[29]
v3 sd_dq[30]
v2 sd_dq[31]
j2 sd_dqm[0]
j1 sd_dqm[1]
h4 sd_dqm[2]
h3 sd_dqm[3]
h2 sd_ras_n
g3 sd_cas_n
g7 sd_cke
g6 sd_cs_n
g4 sd_we_n
# The only PROTO1 expansion connectors not shared with CF
g15 p1_a21
h15 p1_a28
g18 p1_a29
u18 p1_a38
p27 p1_clkout
# Serial ports
m16 ttya_dcd
m14 ttya_txd
k16 ttya_rxd
m15 ttya_dtr
m20 ttya_dsr
k19 ttya_rts
j13 ttya_cts
m19 ttya_ri
a13 ttyb_txd
c13 ttyb_rxd
# Displays (0 = LSB, 1 = MSB)
# For each digit, the segments a-g followed by dp
u6 s7_0[0]
v6 s7_0[1]
w7 s7_0[2]
y7 s7_0[3]
r7 s7_0[4]
t8 s7_0[5]
v7 s7_0[6]
u7 s7_0[7]
t5 s7_1[0]
u5 s7_1[1]
v5 s7_1[2]
w5 s7_1[3]
t6 s7_1[4]
t7 s7_1[5]
w6 s7_1[6]
y6 s7_1[7]
# Plain LEDs
e14 led[0]
e13 led[1]
c14 led[2]
d14 led[3]
e12 led[4]
f12 led[5]
b3 led[6]
b14 led[7]
# Pushbutton switches
w3 sw[0]
y4 sw[1]
v4 sw[2]
w4 sw[3]
# Shared bus table (names per NIOS devel kit manual)
# This bus contains the flash, SRAM, and Ethernet
b4 fse_a[0]
a4 fse_a[1]
d5 fse_a[2]
d6 fse_a[3]
c5 fse_a[4]
b5 fse_a[5]
c2 fse_a[6]
d2 fse_a[7]
d4 fse_a[8]
d1 fse_a[9]
e4 fse_a[10]
e5 fse_a[11]
f3 fse_a[12]
e3 fse_a[13]
e2 fse_a[14]
f4 fse_a[15]
f5 fse_a[16]
f2 fse_a[17]
f1 fse_a[18]
f6 fse_a[19]
g5 fse_a[20]
g1 fse_a[21]
g2 fse_a[22]
c6 fse_d[0]
e6 fse_d[1]
b6 fse_d[2]
a6 fse_d[3]
f7 fse_d[4]
e7 fse_d[5]
b7 fse_d[6]
a7 fse_d[7]
d7 fse_d[8]
c7 fse_d[9]
f8 fse_d[10]
e8 fse_d[11]
b8 fse_d[12]
a8 fse_d[13]
d8 fse_d[14]
c8 fse_d[15]
b9 fse_d[16]
a9 fse_d[17]
d9 fse_d[18]
c9 fse_d[19]
e9 fse_d[20]
e10 fse_d[21]
b10 fse_d[22]
a10 fse_d[23]
f10 fse_d[24]
c10 fse_d[25]
d10 fse_d[26]
c11 fse_d[27]
d11 fse_d[28]
b11 fse_d[29]
a11 fse_d[30]
e11 fse_d[31]
a12 flash_cs_n
b12 flash_oe_n
d12 flash_rw_n
c12 flash_ry_by_n
v17 sram_be_n[0]
v16 sram_be_n[1]
w16 sram_be_n[2]
t16 sram_be_n[3]
w17 sram_cs_n
y17 sram_oe_n
u16 sram_we_n
a14 enet_ads_n
b15 enet_aen
c16 enet_be_n[0]
b16 enet_be_n[1]
d16 enet_be_n[2]
e16 enet_be_n[3]
b17 enet_cycle_n
c15 enet_datacs_n
d15 enet_intrq0
f14 enet_iochrdy
a15 enet_ior_n
e15 enet_iow_n
c17 enet_lclk
d3 enet_ldev_n
b18 enet_rdyrtn_n
a17 enet_w_r_n