summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2003-09-06 03:42:19 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2003-09-06 03:42:19 (GMT)
commite6922d76fbcec783fc0080b6b93f0669c906a42d (patch)
treeb35b09b12635b110b79d76dcec004c5ee6ae095a
downloadkeyboard-e6922d76fbcec783fc0080b6b93f0669c906a42d.zip
keyboard-e6922d76fbcec783fc0080b6b93f0669c906a42d.tar.gz
keyboard-e6922d76fbcec783fc0080b6b93f0669c906a42d.tar.bz2
keyboard-e6922d76fbcec783fc0080b6b93f0669c906a42d.tar.xz
Snapshot of keyboard controller project.
-rw-r--r--hexled.v31
-rw-r--r--keyboard.csf494
-rw-r--r--keyboard.v205
3 files changed, 730 insertions, 0 deletions
diff --git a/hexled.v b/hexled.v
new file mode 100644
index 0000000..64a6081
--- /dev/null
+++ b/hexled.v
@@ -0,0 +1,31 @@
+module hexled (
+ value,
+ s7
+ );
+
+ input [3:0] value;
+ output [7:0] s7;
+
+ always @( value )
+ begin
+ case ( value )
+ 4'h0: s7 = ~8'b00111111;
+ 4'h1: s7 = ~8'b00000110;
+ 4'h2: s7 = ~8'b01011011;
+ 4'h3: s7 = ~8'b01001111;
+ 4'h4: s7 = ~8'b01100110;
+ 4'h5: s7 = ~8'b01101101;
+ 4'h6: s7 = ~8'b01111101;
+ 4'h7: s7 = ~8'b00000111;
+ 4'h8: s7 = ~8'b01111111;
+ 4'h9: s7 = ~8'b01101111;
+ 4'hA: s7 = ~8'b01110111;
+ 4'hB: s7 = ~8'b01111100;
+ 4'hC: s7 = ~8'b00111001;
+ 4'hD: s7 = ~8'b01011110;
+ 4'hE: s7 = ~8'b01111001;
+ 4'hF: s7 = ~8'b01110001;
+ endcase
+ end
+endmodule // hexled
+
diff --git a/keyboard.csf b/keyboard.csf
new file mode 100644
index 0000000..84ee2c7
--- /dev/null
+++ b/keyboard.csf
@@ -0,0 +1,494 @@
+COMPILER_SETTINGS
+{
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ INITIAL_PLACEMENT_CONFIGURATION = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_AUTO_ASSIGN = 0;
+ SIGNALPROBE_COMPILATION = OFF;
+ SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
+ RUN_FITTER_IN_SIGNALPROBE_MODE = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = NORMAL_COMPILATION;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = ON;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |keyboard;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CLOCK_DIVISOR = 1;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = sld_hub_inst;
+ HUB_ENTITY_NAME = sld_hub;
+}
+CHIP(keyboard)
+{
+ DEVICE = EP1C20F400C7;
+ DEVICE_FILTER_PACKAGE = ANY;
+ DEVICE_FILTER_PIN_COUNT = ANY;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ USER_START_UP_CLOCK = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ USE_CONFIGURATION_DEVICE = ON;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ STRATIX_UPDATE_MODE = STANDARD;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ COMPRESSION_MODE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_HEX_FILE = OFF;
+ SECURITY_BIT = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ GENERATE_SVF_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+ BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ CLOCK_SOURCE = INTERNAL;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_DIVISOR = 1;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ clkin : LOCATION = Pin_K5;
+ proto1_clkout : LOCATION = Pin_K6;
+ proto2_clkout : LOCATION = Pin_K14;
+ pld_clkout : LOCATION = Pin_L8;
+ pld_clkfb : LOCATION = Pin_L14;
+ sd_clk : LOCATION = Pin_L13;
+ reset_n : LOCATION = Pin_C4;
+ vga_r[0] : LOCATION = Pin_U12;
+ vga_r[1] : LOCATION = Pin_V12;
+ vga_r[2] : LOCATION = Pin_T13;
+ vga_r[3] : LOCATION = Pin_R13;
+ vga_r[4] : LOCATION = Pin_Y13;
+ vga_r[5] : LOCATION = Pin_W13;
+ vga_r[6] : LOCATION = Pin_U13;
+ vga_r[7] : LOCATION = Pin_V13;
+ vga_g[0] : LOCATION = Pin_T15;
+ vga_g[1] : LOCATION = Pin_W15;
+ vga_g[2] : LOCATION = Pin_Y15;
+ vga_g[3] : LOCATION = Pin_U15;
+ vga_g[4] : LOCATION = Pin_V15;
+ vga_g[5] : LOCATION = Pin_V14;
+ vga_g[6] : LOCATION = Pin_U14;
+ vga_g[7] : LOCATION = Pin_Y14;
+ vga_b[0] : LOCATION = Pin_T12;
+ vga_b[1] : LOCATION = Pin_T11;
+ vga_b[2] : LOCATION = Pin_W12;
+ vga_b[4] : LOCATION = Pin_Y12;
+ vga_b[3] : LOCATION = Pin_W8;
+ vga_b[5] : LOCATION = Pin_Y8;
+ vga_b[6] : LOCATION = Pin_V9;
+ vga_b[7] : LOCATION = Pin_U9;
+ vga_hs : LOCATION = Pin_T9;
+ vga_vs : LOCATION = Pin_R9;
+ vga_blank_n : LOCATION = Pin_R14;
+ vga_sync_n : LOCATION = Pin_T14;
+ vga_sync_t : LOCATION = Pin_W14;
+ vga_m1 : LOCATION = Pin_V11;
+ vga_m2 : LOCATION = Pin_U11;
+ audio_l : LOCATION = Pin_W9;
+ audio_r : LOCATION = Pin_U10;
+ ps2_sel : LOCATION = Pin_W10;
+ ps2_kclk : LOCATION = Pin_Y10;
+ ps2_kdata : LOCATION = Pin_V10;
+ ps2_mclk : LOCATION = Pin_T10;
+ ps2_mdata : LOCATION = Pin_Y9;
+ cf_d[3] : LOCATION = Pin_F18;
+ cf_d[4] : LOCATION = Pin_E17;
+ cf_d[5] : LOCATION = Pin_D17;
+ cf_d[6] : LOCATION = Pin_D18;
+ cf_d[7] : LOCATION = Pin_C18;
+ cf_ce1_n : LOCATION = Pin_H20;
+ cf_a[10] : LOCATION = Pin_J15;
+ cf_oe_n : LOCATION = Pin_D13;
+ cf_a[9] : LOCATION = Pin_J20;
+ cf_a[8] : LOCATION = Pin_H14;
+ cf_a[7] : LOCATION = Pin_J14;
+ cf_a[6] : LOCATION = Pin_J17;
+ cf_a[5] : LOCATION = Pin_J18;
+ cf_a[4] : LOCATION = Pin_K15;
+ cf_a[3] : LOCATION = Pin_W18;
+ cf_a[2] : LOCATION = Pin_H19;
+ cf_a[1] : LOCATION = Pin_H18;
+ cf_a[0] : LOCATION = Pin_H17;
+ cf_d[0] : LOCATION = Pin_F20;
+ cf_d[1] : LOCATION = Pin_F15;
+ cf_d[2] : LOCATION = Pin_E19;
+ cf_wp : LOCATION = Pin_H16;
+ cf_cd1_n : LOCATION = Pin_B13;
+ cf_d[11] : LOCATION = Pin_F17;
+ cf_d[12] : LOCATION = Pin_E18;
+ cf_d[13] : LOCATION = Pin_F16;
+ cf_d[14] : LOCATION = Pin_F19;
+ cf_d[15] : LOCATION = Pin_G16;
+ cf_ce2_n : LOCATION = Pin_U19;
+ cf_iord_n : LOCATION = Pin_G19;
+ cf_iowr_n : LOCATION = Pin_G20;
+ cf_we_n : LOCATION = Pin_V18;
+ cf_rdy : LOCATION = Pin_G17;
+ cf_wait_n : LOCATION = Pin_G14;
+ cf_inpack_n : LOCATION = Pin_V19;
+ cf_reg_n : LOCATION = Pin_U20;
+ cf_bvd2 : LOCATION = Pin_J16;
+ cf_bvd1 : LOCATION = Pin_J19;
+ cf_d[8] : LOCATION = Pin_C19;
+ cf_d[9] : LOCATION = Pin_D19;
+ cf_d[10] : LOCATION = Pin_D20;
+ sd_a[0] : LOCATION = Pin_M2;
+ sd_a[1] : LOCATION = Pin_M1;
+ sd_a[2] : LOCATION = Pin_M6;
+ sd_a[3] : LOCATION = Pin_M4;
+ sd_a[4] : LOCATION = Pin_J8;
+ sd_a[5] : LOCATION = Pin_J7;
+ sd_a[6] : LOCATION = Pin_J6;
+ sd_a[7] : LOCATION = Pin_J5;
+ sd_a[8] : LOCATION = Pin_J4;
+ sd_a[9] : LOCATION = Pin_J3;
+ sd_a[10] : LOCATION = Pin_H6;
+ sd_a[11] : LOCATION = Pin_H5;
+ sd_ba[0] : LOCATION = Pin_H7;
+ sd_ba[1] : LOCATION = Pin_H1;
+ sd_dq[0] : LOCATION = Pin_M5;
+ sd_dq[1] : LOCATION = Pin_M3;
+ sd_dq[2] : LOCATION = Pin_M7;
+ sd_dq[3] : LOCATION = Pin_N6;
+ sd_dq[4] : LOCATION = Pin_N1;
+ sd_dq[5] : LOCATION = Pin_N2;
+ sd_dq[6] : LOCATION = Pin_N4;
+ sd_dq[7] : LOCATION = Pin_N3;
+ sd_dq[8] : LOCATION = Pin_N5;
+ sd_dq[9] : LOCATION = Pin_N7;
+ sd_dq[10] : LOCATION = Pin_P7;
+ sd_dq[11] : LOCATION = Pin_P2;
+ sd_dq[12] : LOCATION = Pin_P1;
+ sd_dq[13] : LOCATION = Pin_P6;
+ sd_dq[14] : LOCATION = Pin_P5;
+ sd_dq[15] : LOCATION = Pin_P3;
+ sd_dq[16] : LOCATION = Pin_P4;
+ sd_dq[17] : LOCATION = Pin_R1;
+ sd_dq[18] : LOCATION = Pin_R2;
+ sd_dq[19] : LOCATION = Pin_R6;
+ sd_dq[20] : LOCATION = Pin_R5;
+ sd_dq[21] : LOCATION = Pin_R3;
+ sd_dq[22] : LOCATION = Pin_R4;
+ sd_dq[23] : LOCATION = Pin_T4;
+ sd_dq[24] : LOCATION = Pin_T2;
+ sd_dq[25] : LOCATION = Pin_T3;
+ sd_dq[26] : LOCATION = Pin_U1;
+ sd_dq[27] : LOCATION = Pin_U4;
+ sd_dq[28] : LOCATION = Pin_U2;
+ sd_dq[29] : LOCATION = Pin_U3;
+ sd_dq[30] : LOCATION = Pin_V3;
+ sd_dq[31] : LOCATION = Pin_V2;
+ sd_dqm[0] : LOCATION = Pin_J2;
+ sd_dqm[1] : LOCATION = Pin_J1;
+ sd_dqm[2] : LOCATION = Pin_H4;
+ sd_dqm[3] : LOCATION = Pin_H3;
+ sd_ras_n : LOCATION = Pin_H2;
+ sd_cas_n : LOCATION = Pin_G3;
+ sd_cke : LOCATION = Pin_G7;
+ sd_cs_n : LOCATION = Pin_G6;
+ sd_we_n : LOCATION = Pin_G4;
+ p1_a21 : LOCATION = Pin_G15;
+ p1_a28 : LOCATION = Pin_H15;
+ p1_a29 : LOCATION = Pin_G18;
+ p1_a38 : LOCATION = Pin_U18;
+ p1_clkout : LOCATION = Pin_P27;
+ ttya_dcd : LOCATION = Pin_M16;
+ ttya_txd : LOCATION = Pin_M14;
+ ttya_rxd : LOCATION = Pin_K16;
+ ttya_dtr : LOCATION = Pin_M15;
+ ttya_dsr : LOCATION = Pin_M20;
+ ttya_rts : LOCATION = Pin_K19;
+ ttya_cts : LOCATION = Pin_J13;
+ ttya_ri : LOCATION = Pin_M19;
+ ttyb_txd : LOCATION = Pin_A13;
+ ttyb_rxd : LOCATION = Pin_C13;
+ s7_0[0] : LOCATION = Pin_U6;
+ s7_0[1] : LOCATION = Pin_V6;
+ s7_0[2] : LOCATION = Pin_W7;
+ s7_0[3] : LOCATION = Pin_Y7;
+ s7_0[4] : LOCATION = Pin_R7;
+ s7_0[5] : LOCATION = Pin_T8;
+ s7_0[6] : LOCATION = Pin_V7;
+ s7_0[7] : LOCATION = Pin_U7;
+ s7_1[0] : LOCATION = Pin_T5;
+ s7_1[1] : LOCATION = Pin_U5;
+ s7_1[2] : LOCATION = Pin_V5;
+ s7_1[3] : LOCATION = Pin_W5;
+ s7_1[4] : LOCATION = Pin_T6;
+ s7_1[5] : LOCATION = Pin_T7;
+ s7_1[6] : LOCATION = Pin_W6;
+ s7_1[7] : LOCATION = Pin_Y6;
+ led[0] : LOCATION = Pin_E14;
+ led[1] : LOCATION = Pin_E13;
+ led[2] : LOCATION = Pin_C14;
+ led[3] : LOCATION = Pin_D14;
+ led[4] : LOCATION = Pin_E12;
+ led[5] : LOCATION = Pin_F12;
+ led[6] : LOCATION = Pin_B3;
+ led[7] : LOCATION = Pin_B14;
+ sw[0] : LOCATION = Pin_W3;
+ sw[1] : LOCATION = Pin_Y4;
+ sw[2] : LOCATION = Pin_V4;
+ sw[3] : LOCATION = Pin_W4;
+ fse_a[0] : LOCATION = Pin_B4;
+ fse_a[1] : LOCATION = Pin_A4;
+ fse_a[2] : LOCATION = Pin_D5;
+ fse_a[3] : LOCATION = Pin_D6;
+ fse_a[4] : LOCATION = Pin_C5;
+ fse_a[5] : LOCATION = Pin_B5;
+ fse_a[6] : LOCATION = Pin_C2;
+ fse_a[7] : LOCATION = Pin_D2;
+ fse_a[8] : LOCATION = Pin_D4;
+ fse_a[9] : LOCATION = Pin_D1;
+ fse_a[10] : LOCATION = Pin_E4;
+ fse_a[11] : LOCATION = Pin_E5;
+ fse_a[12] : LOCATION = Pin_F3;
+ fse_a[13] : LOCATION = Pin_E3;
+ fse_a[14] : LOCATION = Pin_E2;
+ fse_a[15] : LOCATION = Pin_F4;
+ fse_a[16] : LOCATION = Pin_F5;
+ fse_a[17] : LOCATION = Pin_F2;
+ fse_a[18] : LOCATION = Pin_F1;
+ fse_a[19] : LOCATION = Pin_F6;
+ fse_a[20] : LOCATION = Pin_G5;
+ fse_a[21] : LOCATION = Pin_G1;
+ fse_a[22] : LOCATION = Pin_G2;
+ fse_d[0] : LOCATION = Pin_C6;
+ fse_d[1] : LOCATION = Pin_E6;
+ fse_d[2] : LOCATION = Pin_B6;
+ fse_d[3] : LOCATION = Pin_A6;
+ fse_d[4] : LOCATION = Pin_F7;
+ fse_d[5] : LOCATION = Pin_E7;
+ fse_d[6] : LOCATION = Pin_B7;
+ fse_d[7] : LOCATION = Pin_A7;
+ fse_d[8] : LOCATION = Pin_D7;
+ fse_d[9] : LOCATION = Pin_C7;
+ fse_d[10] : LOCATION = Pin_F8;
+ fse_d[11] : LOCATION = Pin_E8;
+ fse_d[12] : LOCATION = Pin_B8;
+ fse_d[13] : LOCATION = Pin_A8;
+ fse_d[14] : LOCATION = Pin_D8;
+ fse_d[15] : LOCATION = Pin_C8;
+ fse_d[16] : LOCATION = Pin_B9;
+ fse_d[17] : LOCATION = Pin_A9;
+ fse_d[18] : LOCATION = Pin_D9;
+ fse_d[19] : LOCATION = Pin_C9;
+ fse_d[20] : LOCATION = Pin_E9;
+ fse_d[21] : LOCATION = Pin_E10;
+ fse_d[22] : LOCATION = Pin_B10;
+ fse_d[23] : LOCATION = Pin_A10;
+ fse_d[24] : LOCATION = Pin_F10;
+ fse_d[25] : LOCATION = Pin_C10;
+ fse_d[26] : LOCATION = Pin_D10;
+ fse_d[27] : LOCATION = Pin_C11;
+ fse_d[28] : LOCATION = Pin_D11;
+ fse_d[29] : LOCATION = Pin_B11;
+ fse_d[30] : LOCATION = Pin_A11;
+ fse_d[31] : LOCATION = Pin_E11;
+ flash_cs_n : LOCATION = Pin_A12;
+ flash_oe_n : LOCATION = Pin_B12;
+ flash_rw_n : LOCATION = Pin_D12;
+ flash_ry_by_n : LOCATION = Pin_C12;
+ sram_be_n[0] : LOCATION = Pin_V17;
+ sram_be_n[1] : LOCATION = Pin_V16;
+ sram_be_n[2] : LOCATION = Pin_W16;
+ sram_be_n[3] : LOCATION = Pin_T16;
+ sram_cs_n : LOCATION = Pin_W17;
+ sram_oe_n : LOCATION = Pin_Y17;
+ sram_we_n : LOCATION = Pin_U16;
+ enet_ads_n : LOCATION = Pin_A14;
+ enet_aen : LOCATION = Pin_B15;
+ enet_be_n[0] : LOCATION = Pin_C16;
+ enet_be_n[1] : LOCATION = Pin_B16;
+ enet_be_n[2] : LOCATION = Pin_D16;
+ enet_be_n[3] : LOCATION = Pin_E16;
+ enet_cycle_n : LOCATION = Pin_B17;
+ enet_datacs_n : LOCATION = Pin_C15;
+ enet_intrq0 : LOCATION = Pin_D15;
+ enet_iochrdy : LOCATION = Pin_F14;
+ enet_ior_n : LOCATION = Pin_A15;
+ enet_iow_n : LOCATION = Pin_E15;
+ enet_lclk : LOCATION = Pin_C17;
+ enet_ldev_n : LOCATION = Pin_D3;
+ enet_rdyrtn_n : LOCATION = Pin_B18;
+ enet_w_r_n : LOCATION = Pin_A17;
+}
diff --git a/keyboard.v b/keyboard.v
new file mode 100644
index 0000000..a85f66a
--- /dev/null
+++ b/keyboard.v
@@ -0,0 +1,205 @@
+/*
+ * keyboard.v
+ *
+ * Controller for a PS/2 keyboard, using a T80 CPU.
+ *
+ * The Z80/T80 is quite suitable for this, as it has highly
+ * predictable timings. The frequency of the PS/2 datastream
+ * is about 15 kHz, which even a slow T80 can handle with ease.
+ * On the Cyclone, we should be able to get T80 up to 50 MHz if
+ * we need to.
+ */
+
+module keyboard (
+ clkin, // PLL input clock
+ reset_n, // Reset button
+ ps2_sel, // PS/2 port input/output select
+ ps2_kclk, // PS/2 keyboard clock
+ ps2_kdata, // PS/2 keyboard data
+ ps2_mclk, // PS/2 mouse clock
+ ps2_mdata, // PS/2 mouse data
+ led, // LEDs
+ s7_0, s7_1, // 7-segment displays
+ ttya_txd, // Serial port for debugging
+ ttya_rts // Serial port flow control
+ );
+
+ input clkin;
+ input reset_n;
+ output ps2_sel;
+ inout ps2_kclk;
+ inout ps2_kdata;
+ inout ps2_mclk;
+ inout ps2_mdata;
+ output [7:0] led;
+ output [7:0] s7_0;
+ output [7:0] s7_1;
+ output ttya_txd;
+ input ttya_rts;
+
+ // Output data
+ reg [7:0] outdata; // Output data
+ reg [7:0] outstat; // Output status (e.g. meta bits)
+ reg [10:0] tty_out; // Output serial port debug
+`define TTY_DIVISOR (50000000/115200) // 50 MHz/115200 Hz
+ reg [8:0] tty_div; // Serial port clock divider
+ reg [3:0] tty_bits; // Number of bits in the tty shift reg
+ reg [7:0] tty_test;
+ reg [7:0] tty_chars;
+
+ assign ttya_txd = tty_out[0];
+
+ hexled hexled0 (
+ .value ( tty_chars[3:0] ),
+ .s7 ( s7_0 )
+ );
+ hexled hexled1 (
+ .value ( tty_chars[7:4] ),
+ .s7 ( s7_1 )
+ );
+ assign led = outstat;
+
+ // Output control
+ reg ps2_sel_q;
+ reg ps2_kclk_q;
+ reg ps2_kdata_q;
+ reg ps2_mclk_q;
+ reg ps2_mdata_q;
+
+ assign ps2_sel = ps2_sel_q;
+ assign ps2_kclk = ps2_kclk_q ? 1'bz : 1'b0;
+ assign ps2_kdata = ps2_kdata_q ? 1'bz : 1'b0;
+ assign ps2_mclk = ps2_mclk_q ? 1'bz : 1'b0;
+ assign ps2_mdata = ps2_mdata_q ? 1'bz : 1'b0;
+
+ // CPU
+ wire cpu_m1_n;
+ wire cpu_iorq_n;
+ wire cpu_mreq_n;
+ wire cpu_rd_n;
+ wire cpu_wr_n;
+ wire cpu_rfsh_n;
+ wire cpu_halt_n;
+ wire cpu_busak_n;
+ reg cpu_wait_q;
+ wire [15:0] cpu_a;
+ reg [7:0] cpu_di;
+ wire [7:0] cpu_do;
+
+ T80se kbd_cpu (
+ .clk_n ( clkin ),
+ .clken ( ~cpu_wait_q ),
+ .reset_n ( reset_n ),
+ .wait_n ( 1 ),
+ .int_n ( 1 ),
+ .nmi_n ( 1 ),
+ .busrq_n ( 1 ),
+ .busak_n ( cpu_busak_n ),
+ .m1_n ( cpu_m1_n ),
+ .mreq_n ( cpu_mreq_n ),
+ .iorq_n ( cpu_iorq_n ),
+ .rd_n ( cpu_rd_n ),
+ .wr_n ( cpu_wr_n ),
+ .rfsh_n ( cpu_rfsh_n ),
+ .halt_n ( cpu_halt_n ),
+ .a ( cpu_a ),
+ .di ( cpu_di ),
+ .do ( cpu_do )
+ );
+
+ // Memory
+ wire [7:0] memrd;
+
+ kbdram kbdram_inst (
+ .address ( cpu_a[10:0] ),
+ .clock ( ~clkin ),
+ .data ( cpu_do ),
+ .wren ( ~cpu_mreq_n & ~cpu_wr_n ),
+ .q ( memrd )
+ );
+
+ // CPU input
+ wire [7:0] ps2rd;
+
+ assign ps2rd[7] = ( tty_bits == 0 ) && ~ttya_rts;
+ assign ps2rd[6:5] = 0;
+ assign ps2rd[4] = ps2_sel_q;
+ assign ps2rd[3] = ps2_mclk;
+ assign ps2rd[2] = ps2_mdata;
+ assign ps2rd[1] = ps2_kclk;
+ assign ps2rd[0] = ps2_kdata;
+
+ assign cpu_di =
+ cpu_rd_n ? 8'bx : // Not reading
+ ~cpu_iorq_n ? ps2rd : // Reading I/O
+ ~cpu_mreq_n ? memrd : // Reading memory
+ 8'bx; // Reading...?
+
+ reg serial_set;
+
+ always @( negedge reset_n or posedge clkin )
+ begin
+ if ( ~reset_n )
+ begin
+ ps2_sel_q <= 0;
+ ps2_mclk_q <= 1;
+ ps2_mdata_q <= 1;
+ ps2_kclk_q <= 1;
+ ps2_kdata_q <= 1;
+
+ tty_div <= `TTY_DIVISOR-1;
+ tty_out <= ~0;
+ tty_bits <= 4'd15; // Time out any (pseudo-)char being sent
+ tty_chars <= 0;
+
+ cpu_wait_q <= 0;
+ serial_set <= 0;
+ end
+ else // clock
+ begin
+ cpu_wait_q <= 0;
+
+ if ( tty_div == 0 )
+ begin
+ tty_div <= `TTY_DIVISOR-1;
+ tty_out <= { 1'b1, tty_out[10:1] };
+ tty_bits <= tty_bits ? (tty_bits-1) : 0;
+ end
+ else
+ tty_div <= tty_div-1;
+
+ if ( ~cpu_iorq_n & ~cpu_wr_n )
+ begin
+ case ( cpu_a[1:0] )
+ 2'b00:
+ begin
+ ps2_sel_q <= cpu_do[4];
+ ps2_mclk_q <= cpu_do[3];
+ ps2_mdata_q <= cpu_do[2];
+ ps2_kclk_q <= cpu_do[1];
+ ps2_kdata_q <= cpu_do[0];
+ end
+ 2'b01:
+ begin
+ tty_chars <= tty_chars+1;
+ tty_out[10:1] <= { 1'b1, cpu_do, 1'b0 };
+ tty_bits <= 4'd10;
+ serial_set <= 1;
+ end
+ 2'b10:
+ begin
+ outdata <= cpu_do;
+ end
+ 2'b11:
+ begin
+ outstat <= cpu_do;
+ end
+ endcase // case( cpu_a[1:0] )
+ end // if ( ~cpu_iorq_n & ~cpu_wr_n )
+ else
+ serial_set <= 0;
+
+ end // clock
+ end // always
+
+endmodule // keyboard