summaryrefslogtreecommitdiffstats
path: root/cfstream.v
blob: 2160d61d78f7577594c8a04d197af9164cb8f8ed (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
/* ----------------------------------------------------------------------- *
 *   
 *   Copyright 2003-2007 H. Peter Anvin - All Rights Reserved
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
 *   Bostom MA 02111-1307, USA; either version 2 of the License, or
 *   (at your option) any later version; incorporated herein by reference.
 *
 * ----------------------------------------------------------------------- */

module cfstream(
		clk,		// 2-20 MHz
		reset_n,
		
		cf_a,
		cf_d,
		cf_bsy_n,
		cf_wait_n,
		cf_ce1_n,
		cf_ce2_n,
		cf_oe_n,
		cf_we_n,
		cf_reg_n,

		q,
		data_ready_n,
		rdreq,

		bsy_time,
		fill
		);

   input         clk;
   input	 reset_n;
   output [10:0] cf_a;
   inout  [15:0] cf_d;
   input 	 cf_bsy_n;
   input 	 cf_wait_n;
   output 	 cf_ce1_n, cf_ce2_n;
   output 	 cf_oe_n;
   output 	 cf_we_n;
   output 	 cf_reg_n;

   output [31:0] q;
   output 	 data_ready_n;
   input 	 rdreq;

   output [7:0]  bsy_time;
   output [7:0]  fill;

   reg [10:0] 	 cf_a = 0;
   reg           cf_oe_n = 1;
   reg           cf_we_n = 1;

   reg [27:0] 	 lba = 0;
   reg [6:0] 	 wordix;	// 128 words @ 32 bits/sector

   reg [31:0] 	 cf_data;
   reg 	         wrreq;
   wire 	 fifo_full;
   wire 	 fifo_almost_full;
   
   reg		 cf_wait_q;
   
   // Megafunction FIFO
   wire [12:0] 	 fifo_usedw;
   assign 	 fill = fifo_usedw[12:5];
   
   cffifo cffifo_inst (
		       .data ( cf_data ),
		       .wrreq ( wrreq ),
		       .rdreq ( rdreq ),
		       .clock ( clk ),
		       .q ( q ),
		       .full ( fifo_full ),
		       .empty ( data_ready_n ),
		       .almost_full ( fifo_almost_full ), // Less than 256 words free
		       .usedw ( fifo_usedw )
		       );
   
`define FSM_IDLE	4'h0
`define FSM_SEND_23	4'h1
`define FSM_WAIT_23     4'h2
`define FSM_SEND_45     4'h3
`define FSM_WAIT_45     4'h4
`define FSM_SEND_67     4'h5
`define FSM_WAIT_67     4'h6
`define FSM_WAIT_BSY    4'h7
`define FSM_WAIT_RDY    4'h8
`define FSM_GET_DATA_0	4'hC
`define FSM_WAIT_DATA_0	4'hD
`define FSM_GET_DATA_1	4'hE
`define FSM_WAIT_DATA_1	4'hF

   reg [3:0] 	 state;

   reg [15:0] 	 out_d;
   reg           drive_d;
   assign        cf_d    = drive_d ? out_d : 16'bz;

   assign 	 cf_reg_n = 1;    // Common memory
   assign 	 cf_ce1_n = 0;	  // 16-bit Common Memory
   assign 	 cf_ce2_n = 0;	  // 16-bit Common Memory

   reg [23:0] 	 bsy_ctr;
   reg [7:0] 	 bsy_time_q = 0;
   assign 	 bsy_time = bsy_time_q;
   
   always @(negedge reset_n or posedge clk)
     if ( ~reset_n )
       begin
	  cf_a       <= 0;
	  lba        <= 0;
	  state      <= `FSM_IDLE;
	  drive_d    <= 0;
	  cf_we_n    <= 1;
	  cf_oe_n    <= 1;
	  bsy_time_q <= 0;
       end
     else
       begin
	  wrreq <= 0;
	  cf_wait_q <= cf_wait_n;
	  
	  case (state)
	    `FSM_IDLE:
	      begin
		 cf_a        	<= 11'h002;
		 out_d 		<= 16'bx;
		 drive_d   	<= 0;
		 cf_we_n	<= 1;
		 cf_oe_n      	<= 1;
		 
		 if ( ~fifo_almost_full & cf_bsy_n & cf_wait_n )
		   state		<= `FSM_SEND_23;
	      end
	    
	    `FSM_SEND_23:
	      begin
		 out_d[7:0]	<= 8'h01;
		 out_d[15:8] 	<= lba[7:0];
		 drive_d     	<= 1;
		 cf_we_n      	<= 0;
		 cf_oe_n      	<= 1;
		 cf_wait_q      <= 0;
		 state       	<= `FSM_WAIT_23;
	      end
	    
	    `FSM_WAIT_23:
	      begin
		 if ( cf_wait_q )
		   begin
		      cf_a      <= 11'h004;
		      state	<= `FSM_SEND_45;
		      cf_we_n	<= 1;
		   end
	    end
	    
	    `FSM_SEND_45:
	      begin
		 out_d       	<= lba[23:8];
		 drive_d     	<= 1;
		 cf_we_n      	<= 0;
		 cf_oe_n      	<= 1;
		 cf_wait_q      <= 0;
		 state       	<= `FSM_WAIT_45;
	      end
	    
	    `FSM_WAIT_45:
	      begin
		 if ( cf_wait_q )
		   begin
		      cf_a	<= 11'h006;
		      state	<= `FSM_SEND_67;
		      cf_we_n	<= 1;
		   end
	      end
	    
	    `FSM_SEND_67:
	      begin
		 out_d[3:0]  	<= lba[27:24];
		 out_d[7:4]  	<= 4'hE;
		 out_d[15:8] 	<= 8'h20;
		 drive_d     	<= 1;
		 cf_we_n      	<= 0;
		 cf_oe_n     	<= 1;
		 cf_wait_q      <= 0;
		 state       	<= `FSM_WAIT_67;
		 
		 lba		<= lba + 1;
	      end
	    
	    `FSM_WAIT_67:
	      begin
		 bsy_ctr	<= 0;
		 
		 if ( cf_wait_q )
		   begin
		      cf_a	<= 11'h000;
		      state	<= cf_bsy_n ? `FSM_WAIT_BSY : `FSM_WAIT_RDY;
		      cf_we_n	<= 1;
		      drive_d	<= 0;
		   end
		 wordix     	<= 0;
	      end
	    
	    `FSM_WAIT_BSY:
	      begin
		 bsy_ctr	<= bsy_ctr + 1;
		 if ( ~cf_bsy_n )
	      	   state 	<= `FSM_WAIT_RDY;
	      end
	  
	  `FSM_WAIT_RDY:
	    begin
	       bsy_ctr		<= bsy_ctr + 1;
	       if ( cf_bsy_n )
	      	 state 		<= `FSM_GET_DATA_0;
	    end
	  
	    `FSM_GET_DATA_0:
	      begin
		 if ( bsy_time_q < bsy_ctr[23:16] )
		   bsy_time_q	<= bsy_ctr[23:16];
		 
		 cf_a      	<= 11'h000;
		 drive_d   	<= 0;
		 cf_we_n    	<= 1;
		 cf_oe_n    	<= 0;
		 cf_wait_q      <= 0;
		 state     	<= `FSM_WAIT_DATA_0;
	      end

	    `FSM_WAIT_DATA_0:
	      begin
		 if ( cf_wait_q )
		   begin
		      cf_oe_n	<= 1;
		      cf_data[15:0]   <= cf_d;
		      state	<= `FSM_GET_DATA_1;
		   end
	      end
	    
	    `FSM_GET_DATA_1:
	      begin
		 if ( bsy_time_q < bsy_ctr[23:16] )
		   bsy_time_q	<= bsy_ctr[23:16];
		 
		 cf_a      	<= 11'h000;
		 drive_d   	<= 0;
		 cf_we_n    	<= 1;
		 cf_oe_n    	<= 0;
		 cf_wait_q      <= 0;
		 state     	<= `FSM_WAIT_DATA_1;
	      end

	    `FSM_WAIT_DATA_1:
	      begin
		 if ( cf_wait_q )
		   begin
		      cf_oe_n	<= 1;
		      cf_data[31:16] <= cf_d;
		      wrreq 	<= 1;
		      state	<= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA_0;
		      wordix 	<= wordix + 1;
		   end
	      end
	    
	    default:
	      begin
		 cf_a   	<= 11'bx;
		 out_d		<= 16'bx;
		 drive_d  	<= 1'bx;
		 cf_we_n 	<= 1'bx;
		 cf_oe_n 	<= 1'bx;
		 state  	<= 4'bx;
	    end
	  endcase
       end // else: !if( ~reset_n )
endmodule