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/* $Id$ */
/* ----------------------------------------------------------------------- *
 *   
 *   Copyright 2003-2007 H. Peter Anvin - All Rights Reserved
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
 *   Bostom MA 02111-1307, USA; either version 2 of the License, or
 *   (at your option) any later version; incorporated herein by reference.
 *
 * ----------------------------------------------------------------------- */

/*
 * cfplayer.v
 * 
 * Top-level for sound-playing mechanism
 * 
 * Plays raw CD-format music written to CompactFlash (without partition
 * table or filesystem)
 */

module cfplayer (
		 clkin,
		 reset_n,
		 
		 cf_power,
		 cf_a,
                 cf_d,
                 cf_rdy,
                 cf_wait_n,
                 cf_ce1_n,
                 cf_ce2_n,
                 cf_oe_n,
                 cf_we_n,
                 cf_reg_n,

		 audio_l,
		 audio_r,

		 led,
		 s7_0,
		 s7_1,
		 );
   
   input         clkin;
   input	 reset_n;
   
   output	 cf_power;
   output [10:0] cf_a;
   inout [15:0]  cf_d;
   input 	 cf_rdy;
   input 	 cf_wait_n;
   output 	 cf_ce1_n;
   output 	 cf_ce2_n;
   output 	 cf_oe_n;
   output 	 cf_we_n;
   output 	 cf_reg_n;
   
   output 	 audio_l;
   output 	 audio_r;

   output [7:0]  led;
   output [7:0]  s7_0;
   output [7:0]  s7_1;

   wire [31:0] 	 audio_q;
   wire 	 data_ready_n;
   reg [15:0] 	 audio_data_l = 0;
   reg [15:0] 	 audio_data_r = 0;
   reg 		 rdreq;

   wire 	 audio_strobe;
   reg 		 audio_strobe1;
   
   wire 	 audio_clk;
   wire 	 cf_clk;

   wire [7:0] 	 s7_val;

   assign	 cf_power = 1;
   
   assign 	 led[0] = ~cf_rdy;
   assign 	 led[1] = ~cf_wait_n;
   assign 	 led[2] = audio_data_l[15];
   assign 	 led[3] = audio_data_r[15];
   assign 	 led[4] = audio_l;
   assign 	 led[5] = audio_r;
   assign 	 led[6] = ~audio_strobe;
   assign 	 led[7] = data_ready_n;

   // Primary PLL for design
   pll1	pll1_inst (
		   .inclk0 ( clkin ),	// 50 MHz clkin
		   .pllena ( 1 ),	// PLL enable
		   .areset ( 0 ),	// PLL reset
		   .c0 ( audio_clk ), 	// Audio clock - 200 MHz
		   .c1 ( cf_clk )       // CompactFlash clock - 12.5 MHz
	);

   // CompactFlash read unit
   assign 	 cf_power = 1'b1;       // Enable power to the CF card
   
   cfstream cfstream_inst (
			   .reset_n ( reset_n ),
			   .clk ( cf_clk ),
			   .cf_a ( cf_a ),
			   .cf_d ( cf_d ),
			   .cf_bsy_n ( cf_rdy ),
			   .cf_wait_n ( cf_wait_n ),
			   .cf_ce1_n ( cf_ce1_n ),
			   .cf_ce2_n ( cf_ce2_n ),
			   .cf_oe_n ( cf_oe_n ),
			   .cf_we_n ( cf_we_n ),
			   .cf_reg_n ( cf_reg_n ),
			   .q ( audio_q ),
			   .data_ready_n ( data_ready_n ),
			   .rdreq ( rdreq ),
			   .bsy_time ( ),
			   .fill ( s7_val )
			   );

   // We need to advance the FIFO exactly one datum for each
   // time the audio core latches a datum.
   always @( posedge cf_clk )
     begin
	rdreq <= ( audio_strobe & ~audio_strobe1 & ~data_ready_n );
	audio_strobe1 <= audio_strobe;

	if ( rdreq )
	  begin
	     // Careful here - get the endianism, signedness and
	     // LSB truncation right
	     audio_data_l[15:8] <= audio_q[7:0];
	     audio_data_l[7:0]  <= audio_q[15:8];
	     audio_data_r[15:8] <= audio_q[23:16];
	     audio_data_r[7:0]  <= audio_q[31:24];
	  end
     end

   assign s7_1[7] = 1;
   hexled hexled1 (
		  .value( s7_val[7:4] ),
		  .s7 ( s7_1[6:0] )
		  );
   
   assign s7_0[7] = 1;
   hexled hexled0 (
		  .value( s7_val[3:0] ),
		  .s7 ( s7_0[6:0] )
		  );
   
   sound sound_l (
		  .reset_n ( reset_n ),
		  .clk ( audio_clk ),
		  .data ( audio_data_l ),
		  .audio ( audio_l ),
		  .audio_clk ( audio_strobe ),
		  );
   sound sound_r (
		  .reset_n ( reset_n ),
		  .clk ( audio_clk ),
		  .data ( audio_data_r ),
		  .audio ( audio_r ),
		  .audio_clk ( ),
		  );

endmodule // cfplayer