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authorH. Peter Anvin <hpa@zytor.com>2007-01-27 23:13:13 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2007-01-27 23:13:13 (GMT)
commitea1a29a2f145cc5baf1fc28ad05a2f72b495cfdd (patch)
treec4b67e79b3d21d1fb7c360d9112cebc07070d2f4
parent6d32cfdaf51adc9f9f83b462eeb00810d6515c79 (diff)
downloadcfplayer-ea1a29a2f145cc5baf1fc28ad05a2f72b495cfdd.zip
cfplayer-ea1a29a2f145cc5baf1fc28ad05a2f72b495cfdd.tar.gz
cfplayer-ea1a29a2f145cc5baf1fc28ad05a2f72b495cfdd.tar.bz2
cfplayer-ea1a29a2f145cc5baf1fc28ad05a2f72b495cfdd.tar.xz
Do stereo sound
-rw-r--r--README50
-rw-r--r--cffifo.bsf78
-rw-r--r--cffifo.v185
-rw-r--r--cffifo_bb.v145
-rw-r--r--cffifo_inst.v11
-rw-r--r--cfplayer.csf842
-rw-r--r--cfplayer.v17
-rw-r--r--cfstream.v59
-rw-r--r--sound.v9
9 files changed, 797 insertions, 599 deletions
diff --git a/README b/README
new file mode 100644
index 0000000..fc950ab
--- /dev/null
+++ b/README
@@ -0,0 +1,50 @@
+This is a project for the Altera NIOS Development Kit, Cyclone
+Edition, with an AleaREP Lancelot daughtercard (see
+http://www.fpga.nl/). It should be easy enough to recompile for other
+cards with a CompactFlash socket and binary audio output, just
+reconfigure the pin list.
+
+It plays music recorded on the CompactFlash card to the audio out;
+currently it expects 44100 Hz 16-bit bigendian stereo sound to be
+recorded; this is standard raw CD data.
+
+There has been talk of an MP3 decoder on opencores.org; that could be
+added too, of course.
+
+My main goal in doing this was to test out the abilities of a digital
+DAC. The Lancelot card only has a single bit audio output per
+channel, connected to a low-pass filter with a 3 dB cutoff of only
+about 10 kHz. The sound coming out of this design isn't stellar, but
+it's definitely much better than you'd think.
+
+Version 1 used a 12-bit PWM DAC, version 2 and later use an
+underclocked 16-bit delta-sigma DAC. The latter is significantly
+better, even though it is only clocked at 200 MHz (for proper 16-bit
+resolution, a clock frequency of about 2.9 GHz would be required.)
+Even that would not really help given the low cutoff of the low-pass
+filter on this board.
+
+Versions 1-3 were mono due to underrun problems. This turned out to
+be a very silly problem -- cf_power was left floating, which resulted
+in the CF card running out of power, depending on the access rate...
+
+On a chip with DSP blocks it might be possible to get better
+high-frequency response by applying a preemphasis filter; I haven't
+explored that since my FPGA is a Cyclone (EP1C20) and doesn't have DSP
+blocks. It also would increase the resource requirements hugely --
+this design currently takes less than 400 LE.
+
+The meaning of the LEDs are as follows:
+
+D0 - CF card RDY#
+D1 - CF card WAIT#
+D2 - MSB of left channel
+D3 - MSB of right channel
+D4 - Left channel bitstream (intensity-modulated with amplitude)
+D5 - Right channel bitstream (intensity-modulated with amplitude)
+D6 - Data request
+D7 - FIFO loaded
+
+7seg - FIFO fill level (00 = empty, FF = full)
+
+
diff --git a/cffifo.bsf b/cffifo.bsf
index 6b36dbb..44d3b56 100644
--- a/cffifo.bsf
+++ b/cffifo.bsf
@@ -4,95 +4,97 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
-Copyright (C) 1991-2003 Altera Corporation
-Any megafunction design, and related netlist (encrypted or decrypted),
-support information, device programming or simulation file, and any other
-associated documentation or information provided by Altera or a partner
-under Altera's Megafunction Partnership Program may be used only
-to program PLD devices (but not masked PLD devices) from Altera. Any
-other use of such megafunction design, netlist, support information,
-device programming or simulation file, or any other related documentation
-or information is prohibited for any other purpose, including, but not
-limited to modification, reverse engineering, de-compiling, or use with
-any other silicon devices, unless such use is explicitly licensed under
-a separate agreement with Altera or a megafunction partner. Title to the
-intellectual property, including patents, copyrights, trademarks, trade
-secrets, or maskworks, embodied in any such megafunction design, netlist,
-support information, device programming or simulation file, or any other
-related documentation or information provided by Altera or a megafunction
-partner, remains with Altera, the megafunction partner, or their respective
-licensors. No other licenses, including any licenses needed under any third
-party's intellectual property, are provided herein.
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
- (rect 0 0 160 152)
- (text "cffifo" (rect 67 1 95 17)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 136 24 148)(font "Arial" ))
+ (rect 0 0 160 160)
+ (text "cffifo" (rect 67 1 97 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 144 25 156)(font "Arial" ))
(port
(pt 0 32)
(input)
- (text "data[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
- (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+ (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+ (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 56)
(input)
- (text "wrreq" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
- (text "rdreq" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 96)
(input)
- (text "clock" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 160 32)
(output)
- (text "q[15..0]" (rect 0 0 39 14)(font "Arial" (font_size 8)))
- (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+ (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(port
(pt 160 56)
(output)
- (text "full" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
(line (pt 160 56)(pt 144 56)(line_width 1))
)
(port
(pt 160 72)
(output)
- (text "almost_full" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+ (text "almost_full" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 1))
)
(port
(pt 160 88)
(output)
- (text "empty" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
(line (pt 160 88)(pt 144 88)(line_width 1))
)
+ (port
+ (pt 160 104)
+ (output)
+ (text "usedw[12..0]" (rect 0 0 75 14)(font "Arial" (font_size 8)))
+ (text "usedw[12..0]" (rect 77 98 136 111)(font "Arial" (font_size 8)))
+ (line (pt 160 104)(pt 144 104)(line_width 3))
+ )
(drawing
- (text "16 bits x 8192 words" (rect 58 124 144 136)(font "Arial" ))
- (text "almost_full at 7679" (rect 64 114 144 126)(font "Arial" ))
+ (text "(ack)" (rect 51 67 72 79)(font "Arial" ))
+ (text "32 bits x 8192 words" (rect 58 132 144 144)(font "Arial" ))
+ (text "almost_full at 7936" (rect 64 122 144 134)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
- (line (pt 144 16)(pt 144 136)(line_width 1))
- (line (pt 144 136)(pt 16 136)(line_width 1))
- (line (pt 16 136)(pt 16 16)(line_width 1))
- (line (pt 16 108)(pt 144 108)(line_width 1))
+ (line (pt 144 16)(pt 144 144)(line_width 1))
+ (line (pt 144 144)(pt 16 144)(line_width 1))
+ (line (pt 16 144)(pt 16 16)(line_width 1))
+ (line (pt 16 116)(pt 144 116)(line_width 1))
(line (pt 16 90)(pt 22 96)(line_width 1))
(line (pt 22 96)(pt 16 102)(line_width 1))
)
diff --git a/cffifo.v b/cffifo.v
index 648111d..af2156f 100644
--- a/cffifo.v
+++ b/cffifo.v
@@ -7,60 +7,66 @@
// File Name: cffifo.v
// Megafunction Name(s):
// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.1 Build 201 11/27/2006 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2003 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
module cffifo (
+ clock,
data,
- wrreq,
rdreq,
- clock,
- q,
- full,
+ wrreq,
+ almost_full,
empty,
- almost_full);
+ full,
+ q,
+ usedw);
- input [15:0] data;
- input wrreq;
- input rdreq;
input clock;
- output [15:0] q;
- output full;
- output empty;
+ input [31:0] data;
+ input rdreq;
+ input wrreq;
output almost_full;
+ output empty;
+ output full;
+ output [31:0] q;
+ output [12:0] usedw;
wire sub_wire0;
- wire sub_wire1;
- wire [15:0] sub_wire2;
- wire sub_wire3;
+ wire [12:0] sub_wire1;
+ wire sub_wire2;
+ wire [31:0] sub_wire3;
+ wire sub_wire4;
wire almost_full = sub_wire0;
- wire empty = sub_wire1;
- wire [15:0] q = sub_wire2[15:0];
- wire full = sub_wire3;
+ wire [12:0] usedw = sub_wire1[12:0];
+ wire empty = sub_wire2;
+ wire [31:0] q = sub_wire3[31:0];
+ wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
@@ -68,21 +74,29 @@ module cffifo (
.wrreq (wrreq),
.data (data),
.almost_full (sub_wire0),
- .empty (sub_wire1),
- .q (sub_wire2),
- .full (sub_wire3));
+ .usedw (sub_wire1),
+ .empty (sub_wire2),
+ .q (sub_wire3),
+ .full (sub_wire4)
+ // synopsys translate_off
+ ,
+ .aclr (),
+ .almost_empty (),
+ .sclr ()
+ // synopsys translate_on
+ );
defparam
+ scfifo_component.add_ram_output_register = "ON",
+ scfifo_component.almost_full_value = 7936,
scfifo_component.intended_device_family = "Cyclone",
- scfifo_component.lpm_width = 16,
scfifo_component.lpm_numwords = 8192,
- scfifo_component.lpm_widthu = 13,
- scfifo_component.almost_full_value = 7679,
+ scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
- scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.lpm_width = 32,
+ scfifo_component.lpm_widthu = 13,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
- scfifo_component.use_eab = "ON",
- scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=AUTO";
+ scfifo_component.use_eab = "ON";
endmodule
@@ -90,59 +104,70 @@ endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
-// Retrieval info: PRIVATE: Width NUMERIC "16"
-// Retrieval info: PRIVATE: Depth NUMERIC "8192"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-// Retrieval info: PRIVATE: Full NUMERIC "1"
-// Retrieval info: PRIVATE: Empty NUMERIC "1"
-// Retrieval info: PRIVATE: UsedW NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "7679"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "513"
-// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "7936"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "512"
-// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: Optimize NUMERIC "0"
-// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "7936"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
-// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "7679"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
-// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=AUTO"
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
-// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/cffifo_bb.v b/cffifo_bb.v
index fb5e36b..2455499 100644
--- a/cffifo_bb.v
+++ b/cffifo_bb.v
@@ -1,41 +1,126 @@
-//Copyright (C) 1991-2003 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: cffifo.v
+// Megafunction Name(s):
+// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.1 Build 201 11/27/2006 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
module cffifo (
+ clock,
data,
- wrreq,
rdreq,
- clock,
- q,
- full,
+ wrreq,
+ almost_full,
empty,
- almost_full);
+ full,
+ q,
+ usedw);
- input [15:0] data;
- input wrreq;
- input rdreq;
input clock;
- output [15:0] q;
- output full;
- output empty;
+ input [31:0] data;
+ input rdreq;
+ input wrreq;
output almost_full;
+ output empty;
+ output full;
+ output [31:0] q;
+ output [12:0] usedw;
endmodule
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "513"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "7936"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "32"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "7936"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 13 0 OUTPUT NODEFVAL usedw[12..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 13 0 @usedw 0 0 13 0
+// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL cffifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/cffifo_inst.v b/cffifo_inst.v
index b66cc5e..2d9c5f8 100644
--- a/cffifo_inst.v
+++ b/cffifo_inst.v
@@ -1,10 +1,11 @@
cffifo cffifo_inst (
+ .clock ( clock_sig ),
.data ( data_sig ),
- .wrreq ( wrreq_sig ),
.rdreq ( rdreq_sig ),
- .clock ( clock_sig ),
- .q ( q_sig ),
- .full ( full_sig ),
+ .wrreq ( wrreq_sig ),
+ .almost_full ( almost_full_sig ),
.empty ( empty_sig ),
- .almost_full ( almost_full_sig )
+ .full ( full_sig ),
+ .q ( q_sig ),
+ .usedw ( usedw_sig )
);
diff --git a/cfplayer.csf b/cfplayer.csf
index 6cd51a2..5d0e764 100644
--- a/cfplayer.csf
+++ b/cfplayer.csf
@@ -1,421 +1,421 @@
-COMPILER_SETTINGS
-{
- DRC_FANOUT_EXCEEDING = 30;
- DRC_REPORT_FANOUT_EXCEEDING = OFF;
- DRC_TOP_FANOUT = 50;
- DRC_REPORT_TOP_FANOUT = OFF;
- RUN_DRC_DURING_COMPILATION = OFF;
- ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
- ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
- ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
- ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
- ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
- ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH = OFF;
- SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
- MERGE_HEX_FILE = OFF;
- INITIAL_PLACEMENT_CONFIGURATION = 1;
- FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
- FAMILY = Cyclone;
- DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
- DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
- DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
- DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
- DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
- DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
- DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
- DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
- DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
- DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
- DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
- DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
- DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
- DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
- DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
- DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
- DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
- DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
- DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
- DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
- DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
- DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
- STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
- PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
- PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
- STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
- FAST_FIT_COMPILATION = OFF;
- SIGNALPROBE_AUTO_ASSIGN = 0;
- SIGNALPROBE_COMPILATION = OFF;
- SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
- RUN_FITTER_IN_SIGNALPROBE_MODE = OFF;
- OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
- OPTIMIZE_TIMING = NORMAL_COMPILATION;
- COMPILATION_LEVEL = FULL;
- SAVE_DISK_SPACE = OFF;
- SPEED_DISK_USAGE_TRADEOFF = NORMAL;
- LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
- SIGNALPROBE_ALLOW_OVERUSE = OFF;
- FOCUS_ENTITY_NAME = |cfplayer;
- ROUTING_BACK_ANNOTATION_MODE = OFF;
- INC_PLC_MODE = OFF;
-}
-DEFAULT_DEVICE_OPTIONS
-{
- GENERATE_CONFIG_HEXOUT_FILE = OFF;
- GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
- GENERATE_CONFIG_JBC_FILE = OFF;
- GENERATE_CONFIG_JAM_FILE = OFF;
- GENERATE_CONFIG_ISC_FILE = OFF;
- GENERATE_CONFIG_SVF_FILE = OFF;
- GENERATE_JBC_FILE_COMPRESSED = ON;
- GENERATE_JBC_FILE = OFF;
- GENERATE_JAM_FILE = OFF;
- GENERATE_ISC_FILE = OFF;
- GENERATE_SVF_FILE = OFF;
- RESERVE_PIN = "AS INPUT TRI-STATED";
- RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
- HEXOUT_FILE_COUNT_DIRECTION = UP;
- HEXOUT_FILE_START_ADDRESS = 0;
- GENERATE_HEX_FILE = OFF;
- GENERATE_RBF_FILE = OFF;
- GENERATE_TTF_FILE = OFF;
- RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
- RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
- RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
- RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
- RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
- RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
- DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
- AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
- EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
- FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
- MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
- STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
- APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
- STRATIX_CONFIGURATION_DEVICE = EPC2;
- CYCLONE_CONFIGURATION_DEVICE = EPC2;
- FLEX10K_CONFIGURATION_DEVICE = EPC2;
- FLEX6K_CONFIGURATION_DEVICE = EPC1;
- MERCURY_CONFIGURATION_DEVICE = EPC2;
- EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
- APEX20K_CONFIGURATION_DEVICE = EPC2;
- USE_CONFIGURATION_DEVICE = ON;
- ENABLE_INIT_DONE_OUTPUT = OFF;
- FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
- ENABLE_DEVICE_WIDE_OE = OFF;
- ENABLE_DEVICE_WIDE_RESET = OFF;
- RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
- AUTO_RESTART_CONFIGURATION = OFF;
- ENABLE_VREFB_PIN = OFF;
- ENABLE_VREFA_PIN = OFF;
- SECURITY_BIT = OFF;
- USER_START_UP_CLOCK = OFF;
- APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
- STRATIX_UPDATE_MODE = STANDARD;
- USE_CHECKSUM_AS_USERCODE = OFF;
- MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
- MAX7000_JTAG_USER_CODE = FFFFFFFF;
- FLEX10K_JTAG_USER_CODE = 7F;
- MERCURY_JTAG_USER_CODE = FFFFFFFF;
- APEX20K_JTAG_USER_CODE = FFFFFFFF;
- STRATIX_JTAG_USER_CODE = FFFFFFFF;
- RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
- FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
- FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
- ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
- MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
- ENABLE_JTAG_BST_SUPPORT = OFF;
- CLOCK_DIVISOR = 1;
- CLOCK_FREQUENCY = "10 MHZ";
- CLOCK_SOURCE = INTERNAL;
- COMPRESSION_MODE = OFF;
- ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
-}
-AUTO_SLD_HUB_ENTITY
-{
- AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
- HUB_INSTANCE_NAME = sld_hub_inst;
- HUB_ENTITY_NAME = sld_hub;
-}
-CHIP(cfplayer)
-{
- DEVICE = EP1C20F400C7;
- DEVICE_FILTER_PACKAGE = ANY;
- DEVICE_FILTER_PIN_COUNT = ANY;
- DEVICE_FILTER_SPEED_GRADE = ANY;
- clkin : LOCATION = Pin_K5;
- proto1_clkout : LOCATION = Pin_K6;
- proto2_clkout : LOCATION = Pin_K14;
- pld_clkout : LOCATION = Pin_L8;
- pld_clkfb : LOCATION = Pin_L14;
- sd_clk : LOCATION = Pin_L13;
- reset_n : LOCATION = Pin_C4;
- vga_r[0] : LOCATION = Pin_U12;
- vga_r[1] : LOCATION = Pin_V12;
- vga_r[2] : LOCATION = Pin_T13;
- vga_r[3] : LOCATION = Pin_R13;
- vga_r[4] : LOCATION = Pin_Y13;
- vga_r[5] : LOCATION = Pin_W13;
- vga_r[6] : LOCATION = Pin_U13;
- vga_r[7] : LOCATION = Pin_V13;
- vga_g[0] : LOCATION = Pin_T15;
- vga_g[1] : LOCATION = Pin_W15;
- vga_g[2] : LOCATION = Pin_Y15;
- vga_g[3] : LOCATION = Pin_U15;
- vga_g[4] : LOCATION = Pin_V15;
- vga_g[5] : LOCATION = Pin_V14;
- vga_g[6] : LOCATION = Pin_U14;
- vga_g[7] : LOCATION = Pin_Y14;
- vga_b[0] : LOCATION = Pin_T12;
- vga_b[1] : LOCATION = Pin_T11;
- vga_b[2] : LOCATION = Pin_W12;
- vga_b[4] : LOCATION = Pin_Y12;
- vga_b[3] : LOCATION = Pin_W8;
- vga_b[5] : LOCATION = Pin_Y8;
- vga_b[6] : LOCATION = Pin_V9;
- vga_b[7] : LOCATION = Pin_U9;
- vga_hs : LOCATION = Pin_T9;
- vga_vs : LOCATION = Pin_R9;
- vga_blank_n : LOCATION = Pin_R14;
- vga_sync_n : LOCATION = Pin_T14;
- vga_sync_t : LOCATION = Pin_W14;
- vga_m1 : LOCATION = Pin_V11;
- vga_m2 : LOCATION = Pin_U11;
- audio_l : LOCATION = Pin_W9;
- audio_r : LOCATION = Pin_U10;
- ps2_sel : LOCATION = Pin_W10;
- ps2_kclk : LOCATION = Pin_Y10;
- ps2_kdata : LOCATION = Pin_V10;
- ps2_mclk : LOCATION = Pin_T10;
- ps2_mdata : LOCATION = Pin_Y9;
- cf_power : LOCATION = Pin_M13;
- cf_d[3] : LOCATION = Pin_F18;
- cf_d[4] : LOCATION = Pin_E17;
- cf_d[5] : LOCATION = Pin_D17;
- cf_d[6] : LOCATION = Pin_D18;
- cf_d[7] : LOCATION = Pin_C18;
- cf_ce1_n : LOCATION = Pin_H20;
- cf_a[10] : LOCATION = Pin_J15;
- cf_oe_n : LOCATION = Pin_D13;
- cf_a[9] : LOCATION = Pin_J20;
- cf_a[8] : LOCATION = Pin_H14;
- cf_a[7] : LOCATION = Pin_J14;
- cf_a[6] : LOCATION = Pin_J17;
- cf_a[5] : LOCATION = Pin_J18;
- cf_a[4] : LOCATION = Pin_K15;
- cf_a[3] : LOCATION = Pin_W18;
- cf_a[2] : LOCATION = Pin_H19;
- cf_a[1] : LOCATION = Pin_H18;
- cf_a[0] : LOCATION = Pin_H17;
- cf_d[0] : LOCATION = Pin_F20;
- cf_d[1] : LOCATION = Pin_F15;
- cf_d[2] : LOCATION = Pin_E19;
- cf_wp : LOCATION = Pin_H16;
- cf_cd1_n : LOCATION = Pin_B13;
- cf_d[11] : LOCATION = Pin_F17;
- cf_d[12] : LOCATION = Pin_E18;
- cf_d[13] : LOCATION = Pin_F16;
- cf_d[14] : LOCATION = Pin_F19;
- cf_d[15] : LOCATION = Pin_G16;
- cf_ce2_n : LOCATION = Pin_U19;
- cf_iord_n : LOCATION = Pin_G19;
- cf_iowr_n : LOCATION = Pin_G20;
- cf_we_n : LOCATION = Pin_V18;
- cf_rdy : LOCATION = Pin_G17;
- cf_wait_n : LOCATION = Pin_G14;
- cf_inpack_n : LOCATION = Pin_V19;
- cf_reg_n : LOCATION = Pin_U20;
- cf_bvd2 : LOCATION = Pin_J16;
- cf_bvd1 : LOCATION = Pin_J19;
- cf_d[8] : LOCATION = Pin_C19;
- cf_d[9] : LOCATION = Pin_D19;
- cf_d[10] : LOCATION = Pin_D20;
- sd_a[0] : LOCATION = Pin_M2;
- sd_a[1] : LOCATION = Pin_M1;
- sd_a[2] : LOCATION = Pin_M6;
- sd_a[3] : LOCATION = Pin_M4;
- sd_a[4] : LOCATION = Pin_J8;
- sd_a[5] : LOCATION = Pin_J7;
- sd_a[6] : LOCATION = Pin_J6;
- sd_a[7] : LOCATION = Pin_J5;
- sd_a[8] : LOCATION = Pin_J4;
- sd_a[9] : LOCATION = Pin_J3;
- sd_a[10] : LOCATION = Pin_H6;
- sd_a[11] : LOCATION = Pin_H5;
- sd_ba[0] : LOCATION = Pin_H7;
- sd_ba[1] : LOCATION = Pin_H1;
- sd_dq[0] : LOCATION = Pin_M5;
- sd_dq[1] : LOCATION = Pin_M3;
- sd_dq[2] : LOCATION = Pin_M7;
- sd_dq[3] : LOCATION = Pin_N6;
- sd_dq[4] : LOCATION = Pin_N1;
- sd_dq[5] : LOCATION = Pin_N2;
- sd_dq[6] : LOCATION = Pin_N4;
- sd_dq[7] : LOCATION = Pin_N3;
- sd_dq[8] : LOCATION = Pin_N5;
- sd_dq[9] : LOCATION = Pin_N7;
- sd_dq[10] : LOCATION = Pin_P7;
- sd_dq[11] : LOCATION = Pin_P2;
- sd_dq[12] : LOCATION = Pin_P1;
- sd_dq[13] : LOCATION = Pin_P6;
- sd_dq[14] : LOCATION = Pin_P5;
- sd_dq[15] : LOCATION = Pin_P3;
- sd_dq[16] : LOCATION = Pin_P4;
- sd_dq[17] : LOCATION = Pin_R1;
- sd_dq[18] : LOCATION = Pin_R2;
- sd_dq[19] : LOCATION = Pin_R6;
- sd_dq[20] : LOCATION = Pin_R5;
- sd_dq[21] : LOCATION = Pin_R3;
- sd_dq[22] : LOCATION = Pin_R4;
- sd_dq[23] : LOCATION = Pin_T4;
- sd_dq[24] : LOCATION = Pin_T2;
- sd_dq[25] : LOCATION = Pin_T3;
- sd_dq[26] : LOCATION = Pin_U1;
- sd_dq[27] : LOCATION = Pin_U4;
- sd_dq[28] : LOCATION = Pin_U2;
- sd_dq[29] : LOCATION = Pin_U3;
- sd_dq[30] : LOCATION = Pin_V3;
- sd_dq[31] : LOCATION = Pin_V2;
- sd_dqm[0] : LOCATION = Pin_J2;
- sd_dqm[1] : LOCATION = Pin_J1;
- sd_dqm[2] : LOCATION = Pin_H4;
- sd_dqm[3] : LOCATION = Pin_H3;
- sd_ras_n : LOCATION = Pin_H2;
- sd_cas_n : LOCATION = Pin_G3;
- sd_cke : LOCATION = Pin_G7;
- sd_cs_n : LOCATION = Pin_G6;
- sd_we_n : LOCATION = Pin_G4;
- p1_a21 : LOCATION = Pin_G15;
- p1_a28 : LOCATION = Pin_H15;
- p1_a29 : LOCATION = Pin_G18;
- p1_a38 : LOCATION = Pin_U18;
- p1_clkout : LOCATION = Pin_P27;
- ttya_dcd : LOCATION = Pin_M16;
- ttya_txd : LOCATION = Pin_M14;
- ttya_rxd : LOCATION = Pin_K16;
- ttya_dtr : LOCATION = Pin_M15;
- ttya_dsr : LOCATION = Pin_M20;
- ttya_rts : LOCATION = Pin_K19;
- ttya_cts : LOCATION = Pin_J13;
- ttya_ri : LOCATION = Pin_M19;
- ttyb_txd : LOCATION = Pin_A13;
- ttyb_rxd : LOCATION = Pin_C13;
- s7_0[0] : LOCATION = Pin_U6;
- s7_0[1] : LOCATION = Pin_V6;
- s7_0[2] : LOCATION = Pin_W7;
- s7_0[3] : LOCATION = Pin_Y7;
- s7_0[4] : LOCATION = Pin_R7;
- s7_0[5] : LOCATION = Pin_T8;
- s7_0[6] : LOCATION = Pin_V7;
- s7_0[7] : LOCATION = Pin_U7;
- s7_1[0] : LOCATION = Pin_T5;
- s7_1[1] : LOCATION = Pin_U5;
- s7_1[2] : LOCATION = Pin_V5;
- s7_1[3] : LOCATION = Pin_W5;
- s7_1[4] : LOCATION = Pin_T6;
- s7_1[5] : LOCATION = Pin_T7;
- s7_1[6] : LOCATION = Pin_W6;
- s7_1[7] : LOCATION = Pin_Y6;
- led[0] : LOCATION = Pin_E14;
- led[1] : LOCATION = Pin_E13;
- led[2] : LOCATION = Pin_C14;
- led[3] : LOCATION = Pin_D14;
- led[4] : LOCATION = Pin_E12;
- led[5] : LOCATION = Pin_F12;
- led[6] : LOCATION = Pin_B3;
- led[7] : LOCATION = Pin_B14;
- sw[0] : LOCATION = Pin_W3;
- sw[1] : LOCATION = Pin_Y4;
- sw[2] : LOCATION = Pin_V4;
- sw[3] : LOCATION = Pin_W4;
- fse_a[0] : LOCATION = Pin_B4;
- fse_a[1] : LOCATION = Pin_A4;
- fse_a[2] : LOCATION = Pin_D5;
- fse_a[3] : LOCATION = Pin_D6;
- fse_a[4] : LOCATION = Pin_C5;
- fse_a[5] : LOCATION = Pin_B5;
- fse_a[6] : LOCATION = Pin_C2;
- fse_a[7] : LOCATION = Pin_D2;
- fse_a[8] : LOCATION = Pin_D4;
- fse_a[9] : LOCATION = Pin_D1;
- fse_a[10] : LOCATION = Pin_E4;
- fse_a[11] : LOCATION = Pin_E5;
- fse_a[12] : LOCATION = Pin_F3;
- fse_a[13] : LOCATION = Pin_E3;
- fse_a[14] : LOCATION = Pin_E2;
- fse_a[15] : LOCATION = Pin_F4;
- fse_a[16] : LOCATION = Pin_F5;
- fse_a[17] : LOCATION = Pin_F2;
- fse_a[18] : LOCATION = Pin_F1;
- fse_a[19] : LOCATION = Pin_F6;
- fse_a[20] : LOCATION = Pin_G5;
- fse_a[21] : LOCATION = Pin_G1;
- fse_a[22] : LOCATION = Pin_G2;
- fse_d[0] : LOCATION = Pin_C6;
- fse_d[1] : LOCATION = Pin_E6;
- fse_d[2] : LOCATION = Pin_B6;
- fse_d[3] : LOCATION = Pin_A6;
- fse_d[4] : LOCATION = Pin_F7;
- fse_d[5] : LOCATION = Pin_E7;
- fse_d[6] : LOCATION = Pin_B7;
- fse_d[7] : LOCATION = Pin_A7;
- fse_d[8] : LOCATION = Pin_D7;
- fse_d[9] : LOCATION = Pin_C7;
- fse_d[10] : LOCATION = Pin_F8;
- fse_d[11] : LOCATION = Pin_E8;
- fse_d[12] : LOCATION = Pin_B8;
- fse_d[13] : LOCATION = Pin_A8;
- fse_d[14] : LOCATION = Pin_D8;
- fse_d[15] : LOCATION = Pin_C8;
- fse_d[16] : LOCATION = Pin_B9;
- fse_d[17] : LOCATION = Pin_A9;
- fse_d[18] : LOCATION = Pin_D9;
- fse_d[19] : LOCATION = Pin_C9;
- fse_d[20] : LOCATION = Pin_E9;
- fse_d[21] : LOCATION = Pin_E10;
- fse_d[22] : LOCATION = Pin_B10;
- fse_d[23] : LOCATION = Pin_A10;
- fse_d[24] : LOCATION = Pin_F10;
- fse_d[25] : LOCATION = Pin_C10;
- fse_d[26] : LOCATION = Pin_D10;
- fse_d[27] : LOCATION = Pin_C11;
- fse_d[28] : LOCATION = Pin_D11;
- fse_d[29] : LOCATION = Pin_B11;
- fse_d[30] : LOCATION = Pin_A11;
- fse_d[31] : LOCATION = Pin_E11;
- flash_cs_n : LOCATION = Pin_A12;
- flash_oe_n : LOCATION = Pin_B12;
- flash_rw_n : LOCATION = Pin_D12;
- flash_ry_by_n : LOCATION = Pin_C12;
- sram_be_n[0] : LOCATION = Pin_V17;
- sram_be_n[1] : LOCATION = Pin_V16;
- sram_be_n[2] : LOCATION = Pin_W16;
- sram_be_n[3] : LOCATION = Pin_T16;
- sram_cs_n : LOCATION = Pin_W17;
- sram_oe_n : LOCATION = Pin_Y17;
- sram_we_n : LOCATION = Pin_U16;
- enet_ads_n : LOCATION = Pin_A14;
- enet_aen : LOCATION = Pin_B15;
- enet_be_n[0] : LOCATION = Pin_C16;
- enet_be_n[1] : LOCATION = Pin_B16;
- enet_be_n[2] : LOCATION = Pin_D16;
- enet_be_n[3] : LOCATION = Pin_E16;
- enet_cycle_n : LOCATION = Pin_B17;
- enet_datacs_n : LOCATION = Pin_C15;
- enet_intrq0 : LOCATION = Pin_D15;
- enet_iochrdy : LOCATION = Pin_F14;
- enet_ior_n : LOCATION = Pin_A15;
- enet_iow_n : LOCATION = Pin_E15;
- enet_lclk : LOCATION = Pin_C17;
- enet_ldev_n : LOCATION = Pin_D3;
- enet_rdyrtn_n : LOCATION = Pin_B18;
- enet_w_r_n : LOCATION = Pin_A17;
-}
+COMPILER_SETTINGS
+{
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ INITIAL_PLACEMENT_CONFIGURATION = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_AUTO_ASSIGN = 0;
+ SIGNALPROBE_COMPILATION = OFF;
+ SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
+ RUN_FITTER_IN_SIGNALPROBE_MODE = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = NORMAL_COMPILATION;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = OFF;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |cfplayer;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CLOCK_DIVISOR = 1;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = sld_hub_inst;
+ HUB_ENTITY_NAME = sld_hub;
+}
+CHIP(cfplayer)
+{
+ DEVICE = EP1C20F400C7;
+ DEVICE_FILTER_PACKAGE = ANY;
+ DEVICE_FILTER_PIN_COUNT = ANY;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ clkin : LOCATION = Pin_K5;
+ proto1_clkout : LOCATION = Pin_K6;
+ proto2_clkout : LOCATION = Pin_K14;
+ pld_clkout : LOCATION = Pin_L8;
+ pld_clkfb : LOCATION = Pin_L14;
+ sd_clk : LOCATION = Pin_L13;
+ reset_n : LOCATION = Pin_C4;
+ vga_r[0] : LOCATION = Pin_U12;
+ vga_r[1] : LOCATION = Pin_V12;
+ vga_r[2] : LOCATION = Pin_T13;
+ vga_r[3] : LOCATION = Pin_R13;
+ vga_r[4] : LOCATION = Pin_Y13;
+ vga_r[5] : LOCATION = Pin_W13;
+ vga_r[6] : LOCATION = Pin_U13;
+ vga_r[7] : LOCATION = Pin_V13;
+ vga_g[0] : LOCATION = Pin_T15;
+ vga_g[1] : LOCATION = Pin_W15;
+ vga_g[2] : LOCATION = Pin_Y15;
+ vga_g[3] : LOCATION = Pin_U15;
+ vga_g[4] : LOCATION = Pin_V15;
+ vga_g[5] : LOCATION = Pin_V14;
+ vga_g[6] : LOCATION = Pin_U14;
+ vga_g[7] : LOCATION = Pin_Y14;
+ vga_b[0] : LOCATION = Pin_T12;
+ vga_b[1] : LOCATION = Pin_T11;
+ vga_b[2] : LOCATION = Pin_W12;
+ vga_b[4] : LOCATION = Pin_Y12;
+ vga_b[3] : LOCATION = Pin_W8;
+ vga_b[5] : LOCATION = Pin_Y8;
+ vga_b[6] : LOCATION = Pin_V9;
+ vga_b[7] : LOCATION = Pin_U9;
+ vga_hs : LOCATION = Pin_T9;
+ vga_vs : LOCATION = Pin_R9;
+ vga_blank_n : LOCATION = Pin_R14;
+ vga_sync_n : LOCATION = Pin_T14;
+ vga_sync_t : LOCATION = Pin_W14;
+ vga_m1 : LOCATION = Pin_V11;
+ vga_m2 : LOCATION = Pin_U11;
+ audio_l : LOCATION = Pin_W9;
+ audio_r : LOCATION = Pin_U10;
+ ps2_sel : LOCATION = Pin_W10;
+ ps2_kclk : LOCATION = Pin_Y10;
+ ps2_kdata : LOCATION = Pin_V10;
+ ps2_mclk : LOCATION = Pin_T10;
+ ps2_mdata : LOCATION = Pin_Y9;
+ cf_power : LOCATION = Pin_M13;
+ cf_d[3] : LOCATION = Pin_F18;
+ cf_d[4] : LOCATION = Pin_E17;
+ cf_d[5] : LOCATION = Pin_D17;
+ cf_d[6] : LOCATION = Pin_D18;
+ cf_d[7] : LOCATION = Pin_C18;
+ cf_ce1_n : LOCATION = Pin_H20;
+ cf_a[10] : LOCATION = Pin_J15;
+ cf_oe_n : LOCATION = Pin_D13;
+ cf_a[9] : LOCATION = Pin_J20;
+ cf_a[8] : LOCATION = Pin_H14;
+ cf_a[7] : LOCATION = Pin_J14;
+ cf_a[6] : LOCATION = Pin_J17;
+ cf_a[5] : LOCATION = Pin_J18;
+ cf_a[4] : LOCATION = Pin_K15;
+ cf_a[3] : LOCATION = Pin_W18;
+ cf_a[2] : LOCATION = Pin_H19;
+ cf_a[1] : LOCATION = Pin_H18;
+ cf_a[0] : LOCATION = Pin_H17;
+ cf_d[0] : LOCATION = Pin_F20;
+ cf_d[1] : LOCATION = Pin_F15;
+ cf_d[2] : LOCATION = Pin_E19;
+ cf_wp : LOCATION = Pin_H16;
+ cf_cd1_n : LOCATION = Pin_B13;
+ cf_d[11] : LOCATION = Pin_F17;
+ cf_d[12] : LOCATION = Pin_E18;
+ cf_d[13] : LOCATION = Pin_F16;
+ cf_d[14] : LOCATION = Pin_F19;
+ cf_d[15] : LOCATION = Pin_G16;
+ cf_ce2_n : LOCATION = Pin_U19;
+ cf_iord_n : LOCATION = Pin_G19;
+ cf_iowr_n : LOCATION = Pin_G20;
+ cf_we_n : LOCATION = Pin_V18;
+ cf_rdy : LOCATION = Pin_G17;
+ cf_wait_n : LOCATION = Pin_G14;
+ cf_inpack_n : LOCATION = Pin_V19;
+ cf_reg_n : LOCATION = Pin_U20;
+ cf_bvd2 : LOCATION = Pin_J16;
+ cf_bvd1 : LOCATION = Pin_J19;
+ cf_d[8] : LOCATION = Pin_C19;
+ cf_d[9] : LOCATION = Pin_D19;
+ cf_d[10] : LOCATION = Pin_D20;
+ sd_a[0] : LOCATION = Pin_M2;
+ sd_a[1] : LOCATION = Pin_M1;
+ sd_a[2] : LOCATION = Pin_M6;
+ sd_a[3] : LOCATION = Pin_M4;
+ sd_a[4] : LOCATION = Pin_J8;
+ sd_a[5] : LOCATION = Pin_J7;
+ sd_a[6] : LOCATION = Pin_J6;
+ sd_a[7] : LOCATION = Pin_J5;
+ sd_a[8] : LOCATION = Pin_J4;
+ sd_a[9] : LOCATION = Pin_J3;
+ sd_a[10] : LOCATION = Pin_H6;
+ sd_a[11] : LOCATION = Pin_H5;
+ sd_ba[0] : LOCATION = Pin_H7;
+ sd_ba[1] : LOCATION = Pin_H1;
+ sd_dq[0] : LOCATION = Pin_M5;
+ sd_dq[1] : LOCATION = Pin_M3;
+ sd_dq[2] : LOCATION = Pin_M7;
+ sd_dq[3] : LOCATION = Pin_N6;
+ sd_dq[4] : LOCATION = Pin_N1;
+ sd_dq[5] : LOCATION = Pin_N2;
+ sd_dq[6] : LOCATION = Pin_N4;
+ sd_dq[7] : LOCATION = Pin_N3;
+ sd_dq[8] : LOCATION = Pin_N5;
+ sd_dq[9] : LOCATION = Pin_N7;
+ sd_dq[10] : LOCATION = Pin_P7;
+ sd_dq[11] : LOCATION = Pin_P2;
+ sd_dq[12] : LOCATION = Pin_P1;
+ sd_dq[13] : LOCATION = Pin_P6;
+ sd_dq[14] : LOCATION = Pin_P5;
+ sd_dq[15] : LOCATION = Pin_P3;
+ sd_dq[16] : LOCATION = Pin_P4;
+ sd_dq[17] : LOCATION = Pin_R1;
+ sd_dq[18] : LOCATION = Pin_R2;
+ sd_dq[19] : LOCATION = Pin_R6;
+ sd_dq[20] : LOCATION = Pin_R5;
+ sd_dq[21] : LOCATION = Pin_R3;
+ sd_dq[22] : LOCATION = Pin_R4;
+ sd_dq[23] : LOCATION = Pin_T4;
+ sd_dq[24] : LOCATION = Pin_T2;
+ sd_dq[25] : LOCATION = Pin_T3;
+ sd_dq[26] : LOCATION = Pin_U1;
+ sd_dq[27] : LOCATION = Pin_U4;
+ sd_dq[28] : LOCATION = Pin_U2;
+ sd_dq[29] : LOCATION = Pin_U3;
+ sd_dq[30] : LOCATION = Pin_V3;
+ sd_dq[31] : LOCATION = Pin_V2;
+ sd_dqm[0] : LOCATION = Pin_J2;
+ sd_dqm[1] : LOCATION = Pin_J1;
+ sd_dqm[2] : LOCATION = Pin_H4;
+ sd_dqm[3] : LOCATION = Pin_H3;
+ sd_ras_n : LOCATION = Pin_H2;
+ sd_cas_n : LOCATION = Pin_G3;
+ sd_cke : LOCATION = Pin_G7;
+ sd_cs_n : LOCATION = Pin_G6;
+ sd_we_n : LOCATION = Pin_G4;
+ p1_a21 : LOCATION = Pin_G15;
+ p1_a28 : LOCATION = Pin_H15;
+ p1_a29 : LOCATION = Pin_G18;
+ p1_a38 : LOCATION = Pin_U18;
+ p1_clkout : LOCATION = Pin_P27;
+ ttya_dcd : LOCATION = Pin_M16;
+ ttya_txd : LOCATION = Pin_M14;
+ ttya_rxd : LOCATION = Pin_K16;
+ ttya_dtr : LOCATION = Pin_M15;
+ ttya_dsr : LOCATION = Pin_M20;
+ ttya_rts : LOCATION = Pin_K19;
+ ttya_cts : LOCATION = Pin_J13;
+ ttya_ri : LOCATION = Pin_M19;
+ ttyb_txd : LOCATION = Pin_A13;
+ ttyb_rxd : LOCATION = Pin_C13;
+ s7_0[0] : LOCATION = Pin_U6;
+ s7_0[1] : LOCATION = Pin_V6;
+ s7_0[2] : LOCATION = Pin_W7;
+ s7_0[3] : LOCATION = Pin_Y7;
+ s7_0[4] : LOCATION = Pin_R7;
+ s7_0[5] : LOCATION = Pin_T8;
+ s7_0[6] : LOCATION = Pin_V7;
+ s7_0[7] : LOCATION = Pin_U7;
+ s7_1[0] : LOCATION = Pin_T5;
+ s7_1[1] : LOCATION = Pin_U5;
+ s7_1[2] : LOCATION = Pin_V5;
+ s7_1[3] : LOCATION = Pin_W5;
+ s7_1[4] : LOCATION = Pin_T6;
+ s7_1[5] : LOCATION = Pin_T7;
+ s7_1[6] : LOCATION = Pin_W6;
+ s7_1[7] : LOCATION = Pin_Y6;
+ led[0] : LOCATION = Pin_E14;
+ led[1] : LOCATION = Pin_E13;
+ led[2] : LOCATION = Pin_C14;
+ led[3] : LOCATION = Pin_D14;
+ led[4] : LOCATION = Pin_E12;
+ led[5] : LOCATION = Pin_F12;
+ led[6] : LOCATION = Pin_B3;
+ led[7] : LOCATION = Pin_B14;
+ sw[0] : LOCATION = Pin_W3;
+ sw[1] : LOCATION = Pin_Y4;
+ sw[2] : LOCATION = Pin_V4;
+ sw[3] : LOCATION = Pin_W4;
+ fse_a[0] : LOCATION = Pin_B4;
+ fse_a[1] : LOCATION = Pin_A4;
+ fse_a[2] : LOCATION = Pin_D5;
+ fse_a[3] : LOCATION = Pin_D6;
+ fse_a[4] : LOCATION = Pin_C5;
+ fse_a[5] : LOCATION = Pin_B5;
+ fse_a[6] : LOCATION = Pin_C2;
+ fse_a[7] : LOCATION = Pin_D2;
+ fse_a[8] : LOCATION = Pin_D4;
+ fse_a[9] : LOCATION = Pin_D1;
+ fse_a[10] : LOCATION = Pin_E4;
+ fse_a[11] : LOCATION = Pin_E5;
+ fse_a[12] : LOCATION = Pin_F3;
+ fse_a[13] : LOCATION = Pin_E3;
+ fse_a[14] : LOCATION = Pin_E2;
+ fse_a[15] : LOCATION = Pin_F4;
+ fse_a[16] : LOCATION = Pin_F5;
+ fse_a[17] : LOCATION = Pin_F2;
+ fse_a[18] : LOCATION = Pin_F1;
+ fse_a[19] : LOCATION = Pin_F6;
+ fse_a[20] : LOCATION = Pin_G5;
+ fse_a[21] : LOCATION = Pin_G1;
+ fse_a[22] : LOCATION = Pin_G2;
+ fse_d[0] : LOCATION = Pin_C6;
+ fse_d[1] : LOCATION = Pin_E6;
+ fse_d[2] : LOCATION = Pin_B6;
+ fse_d[3] : LOCATION = Pin_A6;
+ fse_d[4] : LOCATION = Pin_F7;
+ fse_d[5] : LOCATION = Pin_E7;
+ fse_d[6] : LOCATION = Pin_B7;
+ fse_d[7] : LOCATION = Pin_A7;
+ fse_d[8] : LOCATION = Pin_D7;
+ fse_d[9] : LOCATION = Pin_C7;
+ fse_d[10] : LOCATION = Pin_F8;
+ fse_d[11] : LOCATION = Pin_E8;
+ fse_d[12] : LOCATION = Pin_B8;
+ fse_d[13] : LOCATION = Pin_A8;
+ fse_d[14] : LOCATION = Pin_D8;
+ fse_d[15] : LOCATION = Pin_C8;
+ fse_d[16] : LOCATION = Pin_B9;
+ fse_d[17] : LOCATION = Pin_A9;
+ fse_d[18] : LOCATION = Pin_D9;
+ fse_d[19] : LOCATION = Pin_C9;
+ fse_d[20] : LOCATION = Pin_E9;
+ fse_d[21] : LOCATION = Pin_E10;
+ fse_d[22] : LOCATION = Pin_B10;
+ fse_d[23] : LOCATION = Pin_A10;
+ fse_d[24] : LOCATION = Pin_F10;
+ fse_d[25] : LOCATION = Pin_C10;
+ fse_d[26] : LOCATION = Pin_D10;
+ fse_d[27] : LOCATION = Pin_C11;
+ fse_d[28] : LOCATION = Pin_D11;
+ fse_d[29] : LOCATION = Pin_B11;
+ fse_d[30] : LOCATION = Pin_A11;
+ fse_d[31] : LOCATION = Pin_E11;
+ flash_cs_n : LOCATION = Pin_A12;
+ flash_oe_n : LOCATION = Pin_B12;
+ flash_rw_n : LOCATION = Pin_D12;
+ flash_ry_by_n : LOCATION = Pin_C12;
+ sram_be_n[0] : LOCATION = Pin_V17;
+ sram_be_n[1] : LOCATION = Pin_V16;
+ sram_be_n[2] : LOCATION = Pin_W16;
+ sram_be_n[3] : LOCATION = Pin_T16;
+ sram_cs_n : LOCATION = Pin_W17;
+ sram_oe_n : LOCATION = Pin_Y17;
+ sram_we_n : LOCATION = Pin_U16;
+ enet_ads_n : LOCATION = Pin_A14;
+ enet_aen : LOCATION = Pin_B15;
+ enet_be_n[0] : LOCATION = Pin_C16;
+ enet_be_n[1] : LOCATION = Pin_B16;
+ enet_be_n[2] : LOCATION = Pin_D16;
+ enet_be_n[3] : LOCATION = Pin_E16;
+ enet_cycle_n : LOCATION = Pin_B17;
+ enet_datacs_n : LOCATION = Pin_C15;
+ enet_intrq0 : LOCATION = Pin_D15;
+ enet_iochrdy : LOCATION = Pin_F14;
+ enet_ior_n : LOCATION = Pin_A15;
+ enet_iow_n : LOCATION = Pin_E15;
+ enet_lclk : LOCATION = Pin_C17;
+ enet_ldev_n : LOCATION = Pin_D3;
+ enet_rdyrtn_n : LOCATION = Pin_B18;
+ enet_w_r_n : LOCATION = Pin_A17;
+}
diff --git a/cfplayer.v b/cfplayer.v
index 6a7e285..7a97821 100644
--- a/cfplayer.v
+++ b/cfplayer.v
@@ -1,7 +1,7 @@
/* $Id$ */
/* ----------------------------------------------------------------------- *
*
- * Copyright 2003-2004 H. Peter Anvin - All Rights Reserved
+ * Copyright 2003-2007 H. Peter Anvin - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -64,7 +64,7 @@ module cfplayer (
output [7:0] s7_0;
output [7:0] s7_1;
- wire [15:0] audio_q;
+ wire [31:0] audio_q;
wire data_ready_n;
reg [15:0] audio_data_l = 0;
reg [15:0] audio_data_r = 0;
@@ -99,6 +99,8 @@ module cfplayer (
);
// CompactFlash read unit
+ assign cf_power = 1'b1; // Enable power to the CF card
+
cfstream cfstream_inst (
.reset_n ( reset_n ),
.clk ( cf_clk ),
@@ -114,7 +116,8 @@ module cfplayer (
.q ( audio_q ),
.data_ready_n ( data_ready_n ),
.rdreq ( rdreq ),
- .bsy_time ( s7_val )
+ .bsy_time ( ),
+ .fill ( s7_val )
);
// We need to advance the FIFO exactly one datum for each
@@ -128,12 +131,12 @@ module cfplayer (
begin
// Careful here - get the endianism, signedness and
// LSB truncation right
- audio_data_l[15] <= ~audio_q[7]; // Signed data
+ audio_data_l[15] <= ~audio_q[7]; // Signed data
audio_data_l[14:8] <= audio_q[6:0];
audio_data_l[7:0] <= audio_q[15:8];
- audio_data_r[15] <= ~audio_q[7]; // Signed data
- audio_data_r[14:8] <= audio_q[6:0];
- audio_data_r[7:0] <= audio_q[15:8];
+ audio_data_r[15] <= ~audio_q[23]; // Signed data
+ audio_data_r[14:8] <= audio_q[22:16];
+ audio_data_r[7:0] <= audio_q[31:24];
end
end
diff --git a/cfstream.v b/cfstream.v
index 1978d91..3747ed5 100644
--- a/cfstream.v
+++ b/cfstream.v
@@ -1,6 +1,6 @@
/* ----------------------------------------------------------------------- *
*
- * Copyright 2003 H. Peter Anvin - All Rights Reserved
+ * Copyright 2003-2007 H. Peter Anvin - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -28,7 +28,8 @@ module cfstream(
data_ready_n,
rdreq,
- bsy_time
+ bsy_time,
+ fill
);
input clk;
@@ -42,20 +43,21 @@ module cfstream(
output cf_we_n;
output cf_reg_n;
- output [15:0] q;
+ output [31:0] q;
output data_ready_n;
input rdreq;
output [7:0] bsy_time;
+ output [7:0] fill;
reg [10:0] cf_a = 0;
reg cf_oe_n = 1;
reg cf_we_n = 1;
reg [27:0] lba = 0;
- reg [7:0] wordix; // 256 words @ 16 bits/sector
+ reg [6:0] wordix; // 128 words @ 32 bits/sector
- reg [15:0] cf_data;
+ reg [31:0] cf_data;
reg wrreq;
wire fifo_full;
wire fifo_almost_full;
@@ -63,6 +65,9 @@ module cfstream(
reg cf_wait_q;
// Megafunction FIFO
+ wire [12:0] fifo_usedw;
+ assign fill = fifo_usedw[12:5];
+
cffifo cffifo_inst (
.data ( cf_data ),
.wrreq ( wrreq ),
@@ -71,7 +76,8 @@ module cfstream(
.q ( q ),
.full ( fifo_full ),
.empty ( data_ready_n ),
- .almost_full ( fifo_almost_full ) // Less than 128 words free
+ .almost_full ( fifo_almost_full ), // Less than 256 words free
+ .usedw ( fifo_usedw )
);
`define FSM_IDLE 4'h0
@@ -83,8 +89,10 @@ module cfstream(
`define FSM_WAIT_67 4'h6
`define FSM_WAIT_BSY 4'h7
`define FSM_WAIT_RDY 4'h8
-`define FSM_GET_DATA 4'h9
-`define FSM_WAIT_DATA 4'hA
+`define FSM_GET_DATA_0 4'hC
+`define FSM_WAIT_DATA_0 4'hD
+`define FSM_GET_DATA_1 4'hE
+`define FSM_WAIT_DATA_1 4'hF
reg [3:0] state;
@@ -209,10 +217,33 @@ module cfstream(
begin
bsy_ctr <= bsy_ctr + 1;
if ( cf_bsy_n )
- state <= `FSM_GET_DATA;
+ state <= `FSM_GET_DATA_0;
end
- `FSM_GET_DATA:
+ `FSM_GET_DATA_0:
+ begin
+ if ( bsy_time_q < bsy_ctr[23:16] )
+ bsy_time_q <= bsy_ctr[23:16];
+
+ cf_a <= 11'h000;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 0;
+ cf_wait_q <= 0;
+ state <= `FSM_WAIT_DATA_0;
+ end
+
+ `FSM_WAIT_DATA_0:
+ begin
+ if ( cf_wait_q )
+ begin
+ cf_oe_n <= 1;
+ cf_data[15:0] <= cf_d;
+ state <= `FSM_GET_DATA_1;
+ end
+ end
+
+ `FSM_GET_DATA_1:
begin
if ( bsy_time_q < bsy_ctr[23:16] )
bsy_time_q <= bsy_ctr[23:16];
@@ -222,17 +253,17 @@ module cfstream(
cf_we_n <= 1;
cf_oe_n <= 0;
cf_wait_q <= 0;
- state <= `FSM_WAIT_DATA;
+ state <= `FSM_WAIT_DATA_1;
end
- `FSM_WAIT_DATA:
+ `FSM_WAIT_DATA_1:
begin
if ( cf_wait_q )
begin
cf_oe_n <= 1;
- cf_data <= cf_d;
+ cf_data[31:16] <= cf_d;
wrreq <= 1;
- state <= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA;
+ state <= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA_0;
wordix <= wordix + 1;
end
end
diff --git a/sound.v b/sound.v
index eb5bf3d..26ab133 100644
--- a/sound.v
+++ b/sound.v
@@ -9,9 +9,8 @@
* This is a delta-sigma DAC, assuming an external low pass filter.
*/
-`define BITS 16
-`define MSB (`BITS-1)
-`define DBITS (`BITS+1)
+`define MSB (BITS-1)
+`define DBITS (BITS+1)
module sound(
clk,
@@ -22,6 +21,8 @@ module sound(
audio_clk
);
+ parameter BITS = 16;
+
input clk;
input [`MSB:0] data_l;
input [`MSB:0] data_r;
@@ -73,7 +74,7 @@ module sound(
begin
if ( pulse_ctr == 0 )
begin
- pulse_ctr <= 4535-1; // 44100 Hz sample rate
+ pulse_ctr <= 4535-1; // 200 MHz/44100 Hz sample rate
data_latch_l <= data_l;
data_latch_r <= data_r;
end