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authorH. Peter Anvin <hpa@zytor.com>2007-01-28 02:35:55 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2007-01-28 02:35:55 (GMT)
commit9ed8f035574e352526135d28eb19aeefe5f7a6b0 (patch)
tree89bd2d5c78f30b81c4eaea3487d52a8852c0d873
parent4728fa9df1b888aaaf86b6e7a098538f9d05c936 (diff)
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Make resettable
-rw-r--r--sound.v74
1 files changed, 42 insertions, 32 deletions
diff --git a/sound.v b/sound.v
index 1267bd4..1cebbc3 100644
--- a/sound.v
+++ b/sound.v
@@ -11,23 +11,27 @@
*/
`define MSB (BITS-1)
-`define DBITS (BITS+1)
+`define XBITS 3
+`define DBITS (BITS+`XBITS)
module sound(
- clk,
- data,
- audio,
- audio_clk,
- );
+ reset_n,
+ clk,
+ data,
+ audio,
+ audio_clk,
+ );
parameter BITS = 16;
+ input reset_n;
input clk;
input [`MSB:0] data;
output audio;
output audio_clk;
reg [`MSB:0] data_latch;
+ wire [`DBITS:0] xdata; // Expanded data
wire [`DBITS:0] delta2_add;
wire [`DBITS:0] delta_add;
@@ -40,43 +44,49 @@ module sound(
wire [`DBITS:0] delta;
- reg out_latch;
-
- reg [11:0] pulse_ctr = 0;
+ reg out_latch;
+ reg [11:0] pulse_ctr = 0;
// Note: the input is expected unsigned. For signed input, invert
// bit `MSB.
+ assign xdata[`DBITS:BITS] = 0;
+ assign xdata[`MSB:0] = data_latch;
- assign delta2_add = { 2'b0, data_latch } + delta;
+ assign delta2_add = xdata + delta;
assign sigma2_add = delta2_add + sigma2_latch;
assign delta_add = sigma2_add + delta;
assign sigma_add = delta_add + sigma_latch;
- assign delta[`DBITS] = sigma_latch[`DBITS];
- assign delta[`DBITS-1] = sigma_latch[`DBITS];
- assign delta[`DBITS-2:0] = 0;
+ assign delta[`DBITS:BITS] = {`XBITS{sigma_latch[`DBITS]}};
+ assign delta[`MSB:0] = 0;
- always @(posedge clk)
- begin
- if ( pulse_ctr == 0 )
- begin
- // 2268 is the oversampling ratio (100 MHz/44100 Hz)
- pulse_ctr <= 2268-1;
- data_latch <= data;
- end
- else
- begin
- pulse_ctr <= pulse_ctr-1;
- end
+ always @(negedge reset_n or posedge clk)
+ if (~reset_n)
+ begin
+ pulse_ctr <= 0;
+ out_latch <= 1'b0;
+ sigma_latch <= 0;
+ sigma2_latch <= 0;
+ end
+ else
+ begin
+ if ( pulse_ctr == 0 )
+ begin
+ // 2268 is the oversampling ratio (100 MHz/44100 Hz)
+ pulse_ctr <= 2268-1;
+ data_latch <= data;
+ end
+ else
+ begin
+ pulse_ctr <= pulse_ctr-1;
+ end
- out_latch <= sigma_latch[`DBITS];
- sigma_latch <= sigma_add;
- sigma2_latch <= sigma2_add;
- end
+ out_latch <= sigma_latch[`DBITS];
+ sigma_latch <= sigma_add;
+ sigma2_latch <= sigma2_add;
+ end
- // Definitely *not* a 50% duty cycle; goes high immediately after
- // the data item has been latched
+ assign audio = out_latch;
assign audio_clk = pulse_ctr[11];
- assign audio = out_latch;
endmodule // sound