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authorH. Peter Anvin <hpa@zytor.com>2004-09-23 06:02:00 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2004-09-23 06:02:00 (GMT)
commit6d32cfdaf51adc9f9f83b462eeb00810d6515c79 (patch)
treec228fd517433f6ccd81f36b221e526dde8daf4c5
parent148439557dbb402ef8c9d95a454d0bfa164646b9 (diff)
downloadcfplayer-6d32cfdaf51adc9f9f83b462eeb00810d6515c79.zip
cfplayer-6d32cfdaf51adc9f9f83b462eeb00810d6515c79.tar.gz
cfplayer-6d32cfdaf51adc9f9f83b462eeb00810d6515c79.tar.bz2
cfplayer-6d32cfdaf51adc9f9f83b462eeb00810d6515c79.tar.xz
Latch WAIT# in one place, and add an additional cycle to the minimumcfplayer-3
pulse duration. Add support for the reset button. Drive cf_power high. Upgrade to Quartus 4.1.
-rw-r--r--cfplayer.csf3
-rwxr-xr-xcfplayer.qpf29
-rw-r--r--cfplayer.quartus22
-rw-r--r--cfplayer.v69
-rw-r--r--cfstream.v271
-rw-r--r--hexled.v72
-rw-r--r--pll1.bsf19
-rw-r--r--pll1.v79
-rw-r--r--pll1_bb.v143
-rw-r--r--pll1_inst.v7
10 files changed, 486 insertions, 228 deletions
diff --git a/cfplayer.csf b/cfplayer.csf
index 2988506..6cd51a2 100644
--- a/cfplayer.csf
+++ b/cfplayer.csf
@@ -157,6 +157,7 @@ CHIP(cfplayer)
pld_clkout : LOCATION = Pin_L8;
pld_clkfb : LOCATION = Pin_L14;
sd_clk : LOCATION = Pin_L13;
+ reset_n : LOCATION = Pin_C4;
vga_r[0] : LOCATION = Pin_U12;
vga_r[1] : LOCATION = Pin_V12;
vga_r[2] : LOCATION = Pin_T13;
@@ -195,6 +196,7 @@ CHIP(cfplayer)
ps2_kdata : LOCATION = Pin_V10;
ps2_mclk : LOCATION = Pin_T10;
ps2_mdata : LOCATION = Pin_Y9;
+ cf_power : LOCATION = Pin_M13;
cf_d[3] : LOCATION = Pin_F18;
cf_d[4] : LOCATION = Pin_E17;
cf_d[5] : LOCATION = Pin_D17;
@@ -291,7 +293,6 @@ CHIP(cfplayer)
sd_cke : LOCATION = Pin_G7;
sd_cs_n : LOCATION = Pin_G6;
sd_we_n : LOCATION = Pin_G4;
- p1_a17 : LOCATION = Pin_F20;
p1_a21 : LOCATION = Pin_G15;
p1_a28 : LOCATION = Pin_H15;
p1_a29 : LOCATION = Pin_G18;
diff --git a/cfplayer.qpf b/cfplayer.qpf
new file mode 100755
index 0000000..a5a6250
--- /dev/null
+++ b/cfplayer.qpf
@@ -0,0 +1,29 @@
+# Copyright (C) 1991-2004 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+
+QUARTUS_VERSION = "4.1"
+DATE = "22:58:25 September 22, 2004"
+
+
+# Revisions
+
+PROJECT_REVISION = "cfplayer"
diff --git a/cfplayer.quartus b/cfplayer.quartus
deleted file mode 100644
index 42847a7..0000000
--- a/cfplayer.quartus
+++ /dev/null
@@ -1,22 +0,0 @@
-FILES
-{
- VERILOG_FILE = cfplayer.v;
- VERILOG_FILE = cfstream.v;
- VERILOG_FILE = sound.v;
- VERILOG_FILE = cffifo.v;
- VERILOG_FILE = pll1.v;
- CDF_FILE = Chain1.cdf;
-}
-COMPILER_SETTINGS_LIST
-{
- COMPILER_SETTINGS = cfplayer;
-}
-SIMULATOR_SETTINGS_LIST
-{
- SIMULATOR_SETTINGS = cfplayer;
-}
-SOFTWARE_SETTINGS_LIST
-{
- SOFTWARE_SETTINGS = Debug;
- SOFTWARE_SETTINGS = Release;
-}
diff --git a/cfplayer.v b/cfplayer.v
index 4c76a8d..6a7e285 100644
--- a/cfplayer.v
+++ b/cfplayer.v
@@ -1,7 +1,7 @@
/* $Id$ */
/* ----------------------------------------------------------------------- *
*
- * Copyright 2003 H. Peter Anvin - All Rights Reserved
+ * Copyright 2003-2004 H. Peter Anvin - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,7 +22,9 @@
module cfplayer (
clkin,
+ reset_n,
+ cf_power,
cf_a,
cf_d,
cf_rdy,
@@ -42,7 +44,9 @@ module cfplayer (
);
input clkin;
+ input reset_n;
+ output cf_power;
output [10:0] cf_a;
inout [15:0] cf_d;
input cf_rdy;
@@ -73,14 +77,16 @@ module cfplayer (
wire cf_clk;
wire [7:0] s7_val;
+
+ assign cf_power = 1;
- assign led[0] = cf_rdy;
- assign led[1] = cf_wait_n;
- assign led[2] = audio_data_l[11];
- assign led[3] = audio_data_r[11];
+ assign led[0] = ~cf_rdy;
+ assign led[1] = ~cf_wait_n;
+ assign led[2] = audio_data_l[15];
+ assign led[3] = audio_data_r[15];
assign led[4] = audio_l;
assign led[5] = audio_r;
- assign led[6] = audio_strobe;
+ assign led[6] = ~audio_strobe;
assign led[7] = data_ready_n;
// Primary PLL for design
@@ -94,6 +100,7 @@ module cfplayer (
// CompactFlash read unit
cfstream cfstream_inst (
+ .reset_n ( reset_n ),
.clk ( cf_clk ),
.cf_a ( cf_a ),
.cf_d ( cf_d ),
@@ -130,45 +137,17 @@ module cfplayer (
end
end
- always @( s7_val )
- begin
- case ( s7_val[7:4] )
- 4'h0: s7_1 = ~8'b00111111;
- 4'h1: s7_1 = ~8'b00000110;
- 4'h2: s7_1 = ~8'b01011011;
- 4'h3: s7_1 = ~8'b01001111;
- 4'h4: s7_1 = ~8'b01100110;
- 4'h5: s7_1 = ~8'b01101101;
- 4'h6: s7_1 = ~8'b01111101;
- 4'h7: s7_1 = ~8'b00000111;
- 4'h8: s7_1 = ~8'b01111111;
- 4'h9: s7_1 = ~8'b01101111;
- 4'hA: s7_1 = ~8'b01110111;
- 4'hB: s7_1 = ~8'b01111100;
- 4'hC: s7_1 = ~8'b00111001;
- 4'hD: s7_1 = ~8'b01011110;
- 4'hE: s7_1 = ~8'b01111001;
- 4'hF: s7_1 = ~8'b01110001;
- endcase
- case ( s7_val[3:0] )
- 4'h0: s7_0 = ~8'b00111111;
- 4'h1: s7_0 = ~8'b00000110;
- 4'h2: s7_0 = ~8'b01011011;
- 4'h3: s7_0 = ~8'b01001111;
- 4'h4: s7_0 = ~8'b01100110;
- 4'h5: s7_0 = ~8'b01101101;
- 4'h6: s7_0 = ~8'b01111101;
- 4'h7: s7_0 = ~8'b00000111;
- 4'h8: s7_0 = ~8'b01111111;
- 4'h9: s7_0 = ~8'b01101111;
- 4'hA: s7_0 = ~8'b01110111;
- 4'hB: s7_0 = ~8'b01111100;
- 4'hC: s7_0 = ~8'b00111001;
- 4'hD: s7_0 = ~8'b01011110;
- 4'hE: s7_0 = ~8'b01111001;
- 4'hF: s7_0 = ~8'b01110001;
- endcase
- end
+ assign s7_1[7] = 1;
+ hexled hexled1 (
+ .value( s7_val[7:4] ),
+ .s7 ( s7_1[6:0] )
+ );
+
+ assign s7_0[7] = 1;
+ hexled hexled0 (
+ .value( s7_val[3:0] ),
+ .s7 ( s7_0[6:0] )
+ );
sound sound_inst (
.clk ( audio_clk ),
diff --git a/cfstream.v b/cfstream.v
index a733c70..1978d91 100644
--- a/cfstream.v
+++ b/cfstream.v
@@ -12,6 +12,7 @@
module cfstream(
clk, // 2-20 MHz
+ reset_n,
cf_a,
cf_d,
@@ -31,6 +32,7 @@ module cfstream(
);
input clk;
+ input reset_n;
output [10:0] cf_a;
inout [15:0] cf_d;
input cf_bsy_n;
@@ -45,7 +47,11 @@ module cfstream(
input rdreq;
output [7:0] bsy_time;
-
+
+ reg [10:0] cf_a = 0;
+ reg cf_oe_n = 1;
+ reg cf_we_n = 1;
+
reg [27:0] lba = 0;
reg [7:0] wordix; // 256 words @ 16 bits/sector
@@ -53,7 +59,9 @@ module cfstream(
reg wrreq;
wire fifo_full;
wire fifo_almost_full;
-
+
+ reg cf_wait_q;
+
// Megafunction FIFO
cffifo cffifo_inst (
.data ( cf_data ),
@@ -92,95 +100,110 @@ module cfstream(
reg [7:0] bsy_time_q = 0;
assign bsy_time = bsy_time_q;
- always @(posedge clk)
- begin
- wrreq <= 0;
-
- case (state)
- `FSM_IDLE:
- begin
- cf_a <= 11'h002;
- out_d <= 16'bx;
- drive_d <= 0;
- cf_we_n <= 1;
- cf_oe_n <= 1;
-
- if ( !fifo_almost_full )
- state <= `FSM_SEND_23;
- end
+ always @(negedge reset_n or posedge clk)
+ if ( ~reset_n )
+ begin
+ cf_a <= 0;
+ lba <= 0;
+ state <= `FSM_IDLE;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 1;
+ bsy_time_q <= 0;
+ end
+ else
+ begin
+ wrreq <= 0;
+ cf_wait_q <= cf_wait_n;
- `FSM_SEND_23:
- begin
- out_d[7:0] <= 8'h01;
- out_d[15:8] <= lba[7:0];
- drive_d <= 1;
- cf_we_n <= 0;
- cf_oe_n <= 1;
- state <= `FSM_WAIT_23;
- end
-
- `FSM_WAIT_23:
- begin
- if ( cf_wait_n )
- begin
- cf_a <= 11'h004;
- state <= `FSM_SEND_45;
- cf_we_n <= 1;
- end
- end
-
- `FSM_SEND_45:
- begin
- out_d <= lba[23:8];
- drive_d <= 1;
- cf_we_n <= 0;
- cf_oe_n <= 1;
- state <= `FSM_WAIT_45;
- end
-
- `FSM_WAIT_45:
- begin
- if ( cf_wait_n )
- begin
- cf_a <= 11'h006;
- state <= `FSM_SEND_67;
- cf_we_n <= 1;
- end
- end
-
- `FSM_SEND_67:
- begin
- out_d[3:0] <= lba[27:24];
- out_d[7:4] <= 4'hE;
- out_d[15:8] <= 8'h20;
- drive_d <= 1;
- cf_we_n <= 0;
- cf_oe_n <= 1;
- state <= `FSM_WAIT_67;
-
- lba <= lba + 1;
- end
-
- `FSM_WAIT_67:
- begin
- bsy_ctr <= 0;
-
- if ( cf_wait_n )
- begin
- cf_a <= 11'h000;
- state <= cf_bsy_n ? `FSM_WAIT_BSY : `FSM_WAIT_RDY;
- cf_we_n <= 1;
- drive_d <= 0;
- end
- wordix <= 0;
- end
-
- `FSM_WAIT_BSY:
- begin
- bsy_ctr <= bsy_ctr + 1;
- if ( !cf_bsy_n )
- state <= `FSM_WAIT_RDY;
+ case (state)
+ `FSM_IDLE:
+ begin
+ cf_a <= 11'h002;
+ out_d <= 16'bx;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 1;
+
+ if ( !fifo_almost_full )
+ state <= `FSM_SEND_23;
+ end
+
+ `FSM_SEND_23:
+ begin
+ out_d[7:0] <= 8'h01;
+ out_d[15:8] <= lba[7:0];
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ cf_wait_q <= 0;
+ state <= `FSM_WAIT_23;
+ end
+
+ `FSM_WAIT_23:
+ begin
+ if ( cf_wait_q )
+ begin
+ cf_a <= 11'h004;
+ state <= `FSM_SEND_45;
+ cf_we_n <= 1;
+ end
end
+
+ `FSM_SEND_45:
+ begin
+ out_d <= lba[23:8];
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ cf_wait_q <= 0;
+ state <= `FSM_WAIT_45;
+ end
+
+ `FSM_WAIT_45:
+ begin
+ if ( cf_wait_q )
+ begin
+ cf_a <= 11'h006;
+ state <= `FSM_SEND_67;
+ cf_we_n <= 1;
+ end
+ end
+
+ `FSM_SEND_67:
+ begin
+ out_d[3:0] <= lba[27:24];
+ out_d[7:4] <= 4'hE;
+ out_d[15:8] <= 8'h20;
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ cf_wait_q <= 0;
+ state <= `FSM_WAIT_67;
+
+ lba <= lba + 1;
+ end
+
+ `FSM_WAIT_67:
+ begin
+ bsy_ctr <= 0;
+
+ if ( cf_wait_q )
+ begin
+ cf_a <= 11'h000;
+ state <= cf_bsy_n ? `FSM_WAIT_BSY : `FSM_WAIT_RDY;
+ cf_we_n <= 1;
+ drive_d <= 0;
+ end
+ wordix <= 0;
+ end
+
+ `FSM_WAIT_BSY:
+ begin
+ bsy_ctr <= bsy_ctr + 1;
+ if ( !cf_bsy_n )
+ state <= `FSM_WAIT_RDY;
+ end
`FSM_WAIT_RDY:
begin
@@ -189,40 +212,40 @@ module cfstream(
state <= `FSM_GET_DATA;
end
- `FSM_GET_DATA:
- begin
- if ( bsy_time_q < bsy_ctr[23:16] )
- bsy_time_q <= bsy_ctr[23:16];
-
- cf_a <= 11'h000;
- drive_d <= 0;
- cf_we_n <= 1;
- cf_oe_n <= 0;
- state <= `FSM_WAIT_DATA;
- end
-
- `FSM_WAIT_DATA:
- begin
- if ( cf_wait_n )
- begin
- cf_oe_n <= 1;
- cf_data <= cf_d;
- wrreq <= 1;
- state <= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA;
- wordix <= wordix + 1;
- end
+ `FSM_GET_DATA:
+ begin
+ if ( bsy_time_q < bsy_ctr[23:16] )
+ bsy_time_q <= bsy_ctr[23:16];
+
+ cf_a <= 11'h000;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 0;
+ cf_wait_q <= 0;
+ state <= `FSM_WAIT_DATA;
+ end
+
+ `FSM_WAIT_DATA:
+ begin
+ if ( cf_wait_q )
+ begin
+ cf_oe_n <= 1;
+ cf_data <= cf_d;
+ wrreq <= 1;
+ state <= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA;
+ wordix <= wordix + 1;
+ end
+ end
+
+ default:
+ begin
+ cf_a <= 11'bx;
+ out_d <= 16'bx;
+ drive_d <= 1'bx;
+ cf_we_n <= 1'bx;
+ cf_oe_n <= 1'bx;
+ state <= 4'bx;
end
-
- default:
- begin
- cf_a <= 11'bx;
- out_d <= 16'bx;
- drive_d <= 1'bx;
- cf_we_n <= 1'bx;
- cf_oe_n <= 1'bx;
- state <= 4'bx;
- end
- endcase
- end // always @ (posedge clk)
-
+ endcase
+ end // else: !if( ~reset_n )
endmodule
diff --git a/hexled.v b/hexled.v
new file mode 100644
index 0000000..1c25a59
--- /dev/null
+++ b/hexled.v
@@ -0,0 +1,72 @@
+module hexled (
+ value,
+ s7
+ );
+
+ input [3:0] value;
+ output [6:0] s7;
+ reg [6:0] s7;
+
+ always @( value )
+ begin
+ case ( value )
+ 4'h0: s7 = ~7'b0111111;
+ 4'h1: s7 = ~7'b0000110;
+ 4'h2: s7 = ~7'b1011011;
+ 4'h3: s7 = ~7'b1001111;
+ 4'h4: s7 = ~7'b1100110;
+ 4'h5: s7 = ~7'b1101101;
+ 4'h6: s7 = ~7'b1111101;
+ 4'h7: s7 = ~7'b0000111;
+ 4'h8: s7 = ~7'b1111111;
+ 4'h9: s7 = ~7'b1101111;
+ 4'hA: s7 = ~7'b1110111;
+ 4'hB: s7 = ~7'b1111100;
+ 4'hC: s7 = ~7'b0111001;
+ 4'hD: s7 = ~7'b1011110;
+ 4'hE: s7 = ~7'b1111001;
+ 4'hF: s7 = ~7'b1110001;
+ endcase
+ end
+endmodule // hexled
+
+module hexledx (
+ value,
+ blank,
+ minus,
+ s7
+ );
+
+ input [3:0] value;
+ input blank;
+ input minus;
+ output [6:0] s7;
+ reg [6:0] s7;
+
+ always @( value or blank or minus )
+ begin
+ if ( blank )
+ s7 = ~7'b0000000;
+ else if ( minus )
+ s7 = ~7'b1000000;
+ else case ( value )
+ 4'h0: s7 = ~7'b0111111;
+ 4'h1: s7 = ~7'b0000110;
+ 4'h2: s7 = ~7'b1011011;
+ 4'h3: s7 = ~7'b1001111;
+ 4'h4: s7 = ~7'b1100110;
+ 4'h5: s7 = ~7'b1101101;
+ 4'h6: s7 = ~7'b1111101;
+ 4'h7: s7 = ~7'b0000111;
+ 4'h8: s7 = ~7'b1111111;
+ 4'h9: s7 = ~7'b1101111;
+ 4'hA: s7 = ~7'b1110111;
+ 4'hB: s7 = ~7'b1111100;
+ 4'hC: s7 = ~7'b0111001;
+ 4'hD: s7 = ~7'b1011110;
+ 4'hE: s7 = ~7'b1111001;
+ 4'hF: s7 = ~7'b1110001;
+ endcase
+ end
+endmodule // hexledx
+
diff --git a/pll1.bsf b/pll1.bsf
index d2a9f85..7d6ef94 100644
--- a/pll1.bsf
+++ b/pll1.bsf
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
-Copyright (C) 1991-2003 Altera Corporation
+Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
@@ -27,45 +27,46 @@ party's intellectual property, are provided herein.
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 280 176)
- (text "pll1" (rect 140 0 162 16)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 160 24 172)(font "Arial" ))
+ (text "pll1" (rect 140 0 163 16)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 160 25 172)(font "Arial" ))
(port
(pt 0 64)
(input)
- (text "inclk0" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 48 64)(line_width 1))
)
(port
(pt 0 80)
(input)
- (text "pllena" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "pllena" (rect 0 0 33 14)(font "Arial" (font_size 8)))
(text "pllena" (rect 4 67 34 80)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 48 80)(line_width 1))
)
(port
(pt 0 96)
(input)
- (text "areset" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 83 32 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 48 96)(line_width 1))
)
(port
(pt 280 64)
(output)
- (text "c0" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 265 51 276 64)(font "Arial" (font_size 8)))
(line (pt 280 64)(pt 248 64)(line_width 1))
)
(port
(pt 280 80)
(output)
- (text "c1" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 265 67 276 80)(font "Arial" (font_size 8)))
(line (pt 280 80)(pt 248 80)(line_width 1))
)
(drawing
- (text "inclk0 frequency: 50.000 MHz" (rect 58 59 183 71)(font "Arial" ))
+ (text "Cyclone" (rect 237 161 272 173)(font "Arial" ))
+ (text "inclk0 frequency: 75.000 MHz" (rect 58 59 183 71)(font "Arial" ))
(text "Operation Mode: Normal" (rect 58 73 159 85)(font "Arial" ))
(text "Clk " (rect 59 96 76 108)(font "Arial" ))
(text "Ratio" (rect 81 96 103 108)(font "Arial" ))
diff --git a/pll1.v b/pll1.v
index eca47a8..eb3ec2b 100644
--- a/pll1.v
+++ b/pll1.v
@@ -10,10 +10,12 @@
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
// ************************************************************
-//Copyright (C) 1991-2003 Altera Corporation
+//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
@@ -34,6 +36,9 @@
//party's intellectual property, are provided herein.
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
module pll1 (
inclk0,
pllena,
@@ -60,19 +65,45 @@ module pll1 (
.inclk (sub_wire4),
.pllena (pllena),
.areset (areset),
- .clk (sub_wire0));
+ .clk (sub_wire0)
+ // synopsys translate_off
+ ,
+ .clkswitch (),
+ .extclkena (),
+ .scandataout (),
+ .pfdena (),
+ .locked (),
+ .clkena (),
+ .clkbad (),
+ .activeclock (),
+ .scanclk (),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .clkloss (),
+ .scandata (),
+ .scanread (),
+ .scandone (),
+ .scanaclr (),
+ .sclkout0 (),
+ .sclkout1 (),
+ .scanwrite (),
+ .fbin ()
+ // synopsys translate_on
+ );
defparam
altpll_component.clk1_divide_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 4,
- altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.inclk0_input_frequency = 13333,
altpll_component.clk0_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.pll_type = "AUTO",
altpll_component.clk1_multiply_by = 1,
altpll_component.clk0_time_delay = "0",
+ altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk1_time_delay = "0",
@@ -86,35 +117,39 @@ endmodule
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: JUMP2PAGE0 STRING "General/Modes"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: JUMP2PAGE1 STRING "General/Modes"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: JUMP2PAGE2 STRING "General/Modes"
-// Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
@@ -125,47 +160,46 @@ endmodule
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: TIME_SHIFT6 STRING "0.00000000"
-// Retrieval info: PRIVATE: STICKY_CLK6 STRING "0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: USE_CLK6 STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "525.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "75.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: JUMP2PAGE STRING "Clock switchover"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
-// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
@@ -173,12 +207,13 @@ endmodule
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "13333"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
@@ -196,3 +231,9 @@ endmodule
// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
diff --git a/pll1_bb.v b/pll1_bb.v
index 0c9f171..650e8d0 100644
--- a/pll1_bb.v
+++ b/pll1_bb.v
@@ -1,4 +1,20 @@
-//Copyright (C) 1991-2003 Altera Corporation
+// megafunction wizard: %ALTPLL%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll1.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 4.1 Build 207 08/26/2004 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
@@ -33,3 +49,128 @@ module pll1 (
endmodule
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "525.000"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "75.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
+// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "13333"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE FALSE
diff --git a/pll1_inst.v b/pll1_inst.v
deleted file mode 100644
index 979c931..0000000
--- a/pll1_inst.v
+++ /dev/null
@@ -1,7 +0,0 @@
-pll1 pll1_inst (
- .inclk0 ( inclk0_sig ),
- .pllena ( pllena_sig ),
- .areset ( areset_sig ),
- .c0 ( c0_sig ),
- .c1 ( c1_sig )
- );