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authorH. Peter Anvin <hpa@zytor.com>2007-01-28 00:34:07 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2007-01-28 00:34:07 (GMT)
commit5ffb6f0c83535b44a8e1689a4da66d3a8358c718 (patch)
tree1e29da265fbe76a0b2e5096f38cdc2c102e90dc3
parent34626e39ca18763947c58d5b034fc36a07328bf6 (diff)
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Second-order delta-sigma DAC; each instance serves once channel (duh!)
-rw-r--r--cfplayer.v15
-rw-r--r--sound.v96
2 files changed, 38 insertions, 73 deletions
diff --git a/cfplayer.v b/cfplayer.v
index 7a97821..e4b4b21 100644
--- a/cfplayer.v
+++ b/cfplayer.v
@@ -152,14 +152,17 @@ module cfplayer (
.s7 ( s7_0[6:0] )
);
- sound sound_inst (
+ sound sound_l (
.clk ( audio_clk ),
- // Careful here -- remember CD data is bigendian
- .data_l ( audio_data_l ),
- .data_r ( audio_data_r ),
- .audio_l ( audio_l ),
- .audio_r ( audio_r ),
+ .data ( audio_data_l ),
+ .audio ( audio_l ),
.audio_clk ( audio_strobe ),
);
+ sound sound_r (
+ .clk ( audio_clk ),
+ .data ( audio_data_r ),
+ .audio ( audio_r ),
+ .audio_clk ( ),
+ );
endmodule // cfplayer
diff --git a/sound.v b/sound.v
index 7aace0b..1267bd4 100644
--- a/sound.v
+++ b/sound.v
@@ -8,9 +8,6 @@
*
* This is a second-order delta-sigma DAC, assuming an external
* low pass filter.
- *
- * FIX: This should be broken into modules for each channel. It's
- * ridiculous to have the channels explicit in the code.
*/
`define MSB (BITS-1)
@@ -18,103 +15,68 @@
module sound(
clk,
- data_l,
- data_r,
- audio_l,
- audio_r,
- audio_clk
+ data,
+ audio,
+ audio_clk,
);
parameter BITS = 16;
- input clk;
- input [`MSB:0] data_l;
- input [`MSB:0] data_r;
- output audio_l;
- output audio_r;
- output audio_clk;
-
- reg [`MSB:0] data_latch_l;
- reg [`MSB:0] data_latch_r;
+ input clk;
+ input [`MSB:0] data;
+ output audio;
+ output audio_clk;
- wire [`DBITS:0] delta2_add_l;
- wire [`DBITS:0] delta2_add_r;
- wire [`DBITS:0] delta_add_l;
- wire [`DBITS:0] delta_add_r;
+ reg [`MSB:0] data_latch;
- wire [`DBITS:0] sigma2_add_l;
- wire [`DBITS:0] sigma2_add_r;
- wire [`DBITS:0] sigma_add_l;
- wire [`DBITS:0] sigma_add_r;
+ wire [`DBITS:0] delta2_add;
+ wire [`DBITS:0] delta_add;
- reg [`DBITS:0] sigma2_latch_l;
- reg [`DBITS:0] sigma2_latch_r;
+ wire [`DBITS:0] sigma2_add;
+ wire [`DBITS:0] sigma_add;
- reg [`DBITS:0] sigma_latch_l;
- reg [`DBITS:0] sigma_latch_r;
+ reg [`DBITS:0] sigma2_latch;
+ reg [`DBITS:0] sigma_latch;
- wire [`DBITS:0] delta_l;
- wire [`DBITS:0] delta_r;
+ wire [`DBITS:0] delta;
- reg out_latch_l;
- reg out_latch_r;
+ reg out_latch;
- reg [11:0] pulse_ctr;
+ reg [11:0] pulse_ctr = 0;
- // This gives about 12-bit sound at 44100 Hz. A high sample rate will
- // help avoid actually making the sampling frequency audible.
- // The low-pass filter on the Lancelot has its knee at 10 kHz, and
- // (being a first-order filter) drops off at 3 dB/octave.
-
// Note: the input is expected unsigned. For signed input, invert
// bit `MSB.
- assign delta2_add_l = { 2'b0, data_latch_l } + delta_l;
- assign sigma2_add_l = delta2_add_l + sigma2_latch_l;
+ assign delta2_add = { 2'b0, data_latch } + delta;
+ assign sigma2_add = delta2_add + sigma2_latch;
- assign delta_add_l = sigma2_add_l + delta_l;
- assign sigma_add_l = delta_add_l + sigma_latch_l;
- assign delta_l[`DBITS] = sigma_latch_l[`DBITS];
- assign delta_l[`DBITS-1] = sigma_latch_l[`DBITS];
- assign delta_l[`DBITS-2:0] = 0;
+ assign delta_add = sigma2_add + delta;
+ assign sigma_add = delta_add + sigma_latch;
+ assign delta[`DBITS] = sigma_latch[`DBITS];
+ assign delta[`DBITS-1] = sigma_latch[`DBITS];
+ assign delta[`DBITS-2:0] = 0;
- assign delta2_add_r = { 2'b0, data_latch_r } + delta_r;
- assign sigma2_add_r = delta2_add_r + sigma2_latch_r;
-
- assign delta_add_r = sigma2_add_r + delta_r;
- assign sigma_add_r = delta_add_r + sigma_latch_r;
- assign delta_r[`DBITS] = sigma_latch_r[`DBITS];
- assign delta_r[`DBITS-1] = sigma_latch_r[`DBITS];
- assign delta_r[`DBITS-2:0] = 0;
-
always @(posedge clk)
begin
if ( pulse_ctr == 0 )
begin
// 2268 is the oversampling ratio (100 MHz/44100 Hz)
pulse_ctr <= 2268-1;
- data_latch_l <= data_l;
- data_latch_r <= data_r;
+ data_latch <= data;
end
else
begin
pulse_ctr <= pulse_ctr-1;
end
- out_latch_l <= sigma_latch_l[`DBITS];
- sigma_latch_l <= sigma_add_l;
- sigma2_latch_l <= sigma2_add_l;
-
- out_latch_r <= sigma_latch_r[`DBITS];
- sigma_latch_r <= sigma_add_r;
- sigma2_latch_r <= sigma2_add_r;
+ out_latch <= sigma_latch[`DBITS];
+ sigma_latch <= sigma_add;
+ sigma2_latch <= sigma2_add;
end
// Definitely *not* a 50% duty cycle; goes high immediately after
// the data item has been latched
assign audio_clk = pulse_ctr[11];
-
- assign audio_l = out_latch_l;
- assign audio_r = out_latch_r;
+ assign audio = out_latch;
endmodule // sound