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authorH. Peter Anvin <hpa@zytor.com>2007-01-30 06:33:10 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2007-01-30 06:33:10 (GMT)
commit4d4b4a6a5d9acd59473cedbf55e6ba7955334783 (patch)
tree157bb308e0efe3149f351b84734057a381765d3e
parent9539b9494bec0462eb576d33ca353616252a2204 (diff)
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Switch to signed numbers inside the DAC (easier to verify in a
computational model); we need at least 4 spare bits for the second-order DAC.
-rw-r--r--cfplayer.v6
-rw-r--r--sound.v20
2 files changed, 12 insertions, 14 deletions
diff --git a/cfplayer.v b/cfplayer.v
index df117a3..19794ae 100644
--- a/cfplayer.v
+++ b/cfplayer.v
@@ -131,11 +131,9 @@ module cfplayer (
begin
// Careful here - get the endianism, signedness and
// LSB truncation right
- audio_data_l[15] <= ~audio_q[7]; // Signed data
- audio_data_l[14:8] <= audio_q[6:0];
+ audio_data_l[15:8] <= audio_q[7:0];
audio_data_l[7:0] <= audio_q[15:8];
- audio_data_r[15] <= ~audio_q[23]; // Signed data
- audio_data_r[14:8] <= audio_q[22:16];
+ audio_data_r[15:8] <= audio_q[23:16];
audio_data_r[7:0] <= audio_q[31:24];
end
end
diff --git a/sound.v b/sound.v
index 1cebbc3..b26338a 100644
--- a/sound.v
+++ b/sound.v
@@ -11,8 +11,8 @@
*/
`define MSB (BITS-1)
-`define XBITS 3
-`define DBITS (BITS+`XBITS)
+`define XBITS 4 // Additional bits of precision
+`define DBITS (`MSB+`XBITS)
module sound(
reset_n,
@@ -44,12 +44,11 @@ module sound(
wire [`DBITS:0] delta;
- reg out_latch;
reg [11:0] pulse_ctr = 0;
- // Note: the input is expected unsigned. For signed input, invert
- // bit `MSB.
- assign xdata[`DBITS:BITS] = 0;
+ // Note: the input is expected *signed*. For unsigned input, invert
+ // bit `MSB. This is a change from previous code.
+ assign xdata[`DBITS:BITS] = {`XBITS{data_latch[`MSB]}};
assign xdata[`MSB:0] = data_latch;
assign delta2_add = xdata + delta;
@@ -57,14 +56,16 @@ module sound(
assign delta_add = sigma2_add + delta;
assign sigma_add = delta_add + sigma_latch;
+
+ // delta is -32768 if sigma_latch is negative, otherwise 32768
assign delta[`DBITS:BITS] = {`XBITS{sigma_latch[`DBITS]}};
- assign delta[`MSB:0] = 0;
+ assign delta[`MSB] = 1'b1;
+ assign delta[`MSB-1:0] = 0;
always @(negedge reset_n or posedge clk)
if (~reset_n)
begin
pulse_ctr <= 0;
- out_latch <= 1'b0;
sigma_latch <= 0;
sigma2_latch <= 0;
end
@@ -81,12 +82,11 @@ module sound(
pulse_ctr <= pulse_ctr-1;
end
- out_latch <= sigma_latch[`DBITS];
sigma_latch <= sigma_add;
sigma2_latch <= sigma2_add;
end
- assign audio = out_latch;
+ assign audio = sigma_latch[`DBITS];
assign audio_clk = pulse_ctr[11];
endmodule // sound