summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2003-07-10 04:04:10 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2003-07-10 04:04:10 (GMT)
commit2418a7bd1c30780d6237b5c31a13b5d7d474138d (patch)
tree155b2eb86c231f630d2d75d588f3847afba9e854
downloadcfplayer-2418a7bd1c30780d6237b5c31a13b5d7d474138d.zip
cfplayer-2418a7bd1c30780d6237b5c31a13b5d7d474138d.tar.gz
cfplayer-2418a7bd1c30780d6237b5c31a13b5d7d474138d.tar.bz2
cfplayer-2418a7bd1c30780d6237b5c31a13b5d7d474138d.tar.xz
CompactFlash -> sound player
-rw-r--r--cffifo.bsf99
-rw-r--r--cffifo.cmp34
-rw-r--r--cffifo.inc35
-rw-r--r--cffifo.v148
-rw-r--r--cffifo_bb.v41
-rw-r--r--cffifo_inst.v10
-rw-r--r--cfplayer.csf418
-rw-r--r--cfplayer.quartus22
-rw-r--r--cfplayer.v185
-rw-r--r--cfstream.v228
-rw-r--r--pll1.bsf104
-rw-r--r--pll1.cmp31
-rw-r--r--pll1.inc32
-rw-r--r--pll1.v198
-rw-r--r--pll1_bb.v35
-rw-r--r--pll1_inst.v7
-rw-r--r--sinewave.c27
-rw-r--r--sound.v62
18 files changed, 1716 insertions, 0 deletions
diff --git a/cffifo.bsf b/cffifo.bsf
new file mode 100644
index 0000000..6b36dbb
--- /dev/null
+++ b/cffifo.bsf
@@ -0,0 +1,99 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 152)
+ (text "cffifo" (rect 67 1 95 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 136 24 148)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[15..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+ (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "rdreq" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 66 44 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "clock" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "clock" (rect 26 90 49 103)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 160 32)
+ (output)
+ (text "q[15..0]" (rect 0 0 39 14)(font "Arial" (font_size 8)))
+ (text "q[15..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+ (line (pt 160 32)(pt 144 32)(line_width 3))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "full" (rect 0 0 15 14)(font "Arial" (font_size 8)))
+ (text "full" (rect 127 50 142 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 72)
+ (output)
+ (text "almost_full" (rect 0 0 56 14)(font "Arial" (font_size 8)))
+ (text "almost_full" (rect 90 66 142 79)(font "Arial" (font_size 8)))
+ (line (pt 160 72)(pt 144 72)(line_width 1))
+ )
+ (port
+ (pt 160 88)
+ (output)
+ (text "empty" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "empty" (rect 112 82 141 95)(font "Arial" (font_size 8)))
+ (line (pt 160 88)(pt 144 88)(line_width 1))
+ )
+ (drawing
+ (text "16 bits x 8192 words" (rect 58 124 144 136)(font "Arial" ))
+ (text "almost_full at 7679" (rect 64 114 144 126)(font "Arial" ))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 136)(line_width 1))
+ (line (pt 144 136)(pt 16 136)(line_width 1))
+ (line (pt 16 136)(pt 16 16)(line_width 1))
+ (line (pt 16 108)(pt 144 108)(line_width 1))
+ (line (pt 16 90)(pt 22 96)(line_width 1))
+ (line (pt 22 96)(pt 16 102)(line_width 1))
+ )
+)
diff --git a/cffifo.cmp b/cffifo.cmp
new file mode 100644
index 0000000..0f1eb6e
--- /dev/null
+++ b/cffifo.cmp
@@ -0,0 +1,34 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component cffifo
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ wrreq : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ full : OUT STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ almost_full : OUT STD_LOGIC
+ );
+end component;
diff --git a/cffifo.inc b/cffifo.inc
new file mode 100644
index 0000000..abdbae8
--- /dev/null
+++ b/cffifo.inc
@@ -0,0 +1,35 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION cffifo
+(
+ data[15..0],
+ wrreq,
+ rdreq,
+ clock
+)
+
+RETURNS (
+ q[15..0],
+ full,
+ empty,
+ almost_full
+);
diff --git a/cffifo.v b/cffifo.v
new file mode 100644
index 0000000..648111d
--- /dev/null
+++ b/cffifo.v
@@ -0,0 +1,148 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: cffifo.v
+// Megafunction Name(s):
+// scfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module cffifo (
+ data,
+ wrreq,
+ rdreq,
+ clock,
+ q,
+ full,
+ empty,
+ almost_full);
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input clock;
+ output [15:0] q;
+ output full;
+ output empty;
+ output almost_full;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire [15:0] sub_wire2;
+ wire sub_wire3;
+ wire almost_full = sub_wire0;
+ wire empty = sub_wire1;
+ wire [15:0] q = sub_wire2[15:0];
+ wire full = sub_wire3;
+
+ scfifo scfifo_component (
+ .rdreq (rdreq),
+ .clock (clock),
+ .wrreq (wrreq),
+ .data (data),
+ .almost_full (sub_wire0),
+ .empty (sub_wire1),
+ .q (sub_wire2),
+ .full (sub_wire3));
+ defparam
+ scfifo_component.intended_device_family = "Cyclone",
+ scfifo_component.lpm_width = 16,
+ scfifo_component.lpm_numwords = 8192,
+ scfifo_component.lpm_widthu = 13,
+ scfifo_component.almost_full_value = 7679,
+ scfifo_component.lpm_type = "scfifo",
+ scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.overflow_checking = "ON",
+ scfifo_component.underflow_checking = "ON",
+ scfifo_component.use_eab = "ON",
+ scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=AUTO";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "8192"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "7679"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "513"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "512"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8192"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
+// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "7679"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=AUTO"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
diff --git a/cffifo_bb.v b/cffifo_bb.v
new file mode 100644
index 0000000..fb5e36b
--- /dev/null
+++ b/cffifo_bb.v
@@ -0,0 +1,41 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module cffifo (
+ data,
+ wrreq,
+ rdreq,
+ clock,
+ q,
+ full,
+ empty,
+ almost_full);
+
+ input [15:0] data;
+ input wrreq;
+ input rdreq;
+ input clock;
+ output [15:0] q;
+ output full;
+ output empty;
+ output almost_full;
+
+endmodule
+
diff --git a/cffifo_inst.v b/cffifo_inst.v
new file mode 100644
index 0000000..b66cc5e
--- /dev/null
+++ b/cffifo_inst.v
@@ -0,0 +1,10 @@
+cffifo cffifo_inst (
+ .data ( data_sig ),
+ .wrreq ( wrreq_sig ),
+ .rdreq ( rdreq_sig ),
+ .clock ( clock_sig ),
+ .q ( q_sig ),
+ .full ( full_sig ),
+ .empty ( empty_sig ),
+ .almost_full ( almost_full_sig )
+ );
diff --git a/cfplayer.csf b/cfplayer.csf
new file mode 100644
index 0000000..0027536
--- /dev/null
+++ b/cfplayer.csf
@@ -0,0 +1,418 @@
+COMPILER_SETTINGS
+{
+ DRC_FANOUT_EXCEEDING = 30;
+ DRC_REPORT_FANOUT_EXCEEDING = OFF;
+ DRC_TOP_FANOUT = 50;
+ DRC_REPORT_TOP_FANOUT = OFF;
+ RUN_DRC_DURING_COMPILATION = OFF;
+ ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION = OFF;
+ ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
+ ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
+ ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
+ ADV_NETLIST_OPT_FIT_LE_DUPLICATION_WITH_LUT_RESYNTH = OFF;
+ SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
+ MERGE_HEX_FILE = OFF;
+ INITIAL_PLACEMENT_CONFIGURATION = 1;
+ FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
+ FAMILY = Cyclone;
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
+ DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
+ DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
+ DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
+ DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
+ DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
+ DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
+ DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
+ DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
+ DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
+ STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
+ PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
+ STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
+ FAST_FIT_COMPILATION = OFF;
+ SIGNALPROBE_AUTO_ASSIGN = 0;
+ SIGNALPROBE_COMPILATION = OFF;
+ SIGNALPROBE_ROUTING = ALL_SIGNAL_PROBE;
+ RUN_FITTER_IN_SIGNALPROBE_MODE = OFF;
+ OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
+ OPTIMIZE_TIMING = NORMAL_COMPILATION;
+ COMPILATION_LEVEL = FULL;
+ SAVE_DISK_SPACE = ON;
+ SPEED_DISK_USAGE_TRADEOFF = NORMAL;
+ LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
+ SIGNALPROBE_ALLOW_OVERUSE = OFF;
+ FOCUS_ENTITY_NAME = |cfplayer;
+}
+DEFAULT_DEVICE_OPTIONS
+{
+ GENERATE_CONFIG_HEXOUT_FILE = OFF;
+ GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
+ GENERATE_CONFIG_JBC_FILE = OFF;
+ GENERATE_CONFIG_JAM_FILE = OFF;
+ GENERATE_CONFIG_ISC_FILE = OFF;
+ GENERATE_CONFIG_SVF_FILE = OFF;
+ GENERATE_JBC_FILE_COMPRESSED = ON;
+ GENERATE_JBC_FILE = OFF;
+ GENERATE_JAM_FILE = OFF;
+ GENERATE_ISC_FILE = OFF;
+ GENERATE_SVF_FILE = OFF;
+ RESERVE_PIN = "AS INPUT TRI-STATED";
+ RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
+ HEXOUT_FILE_COUNT_DIRECTION = UP;
+ HEXOUT_FILE_START_ADDRESS = 0;
+ GENERATE_HEX_FILE = OFF;
+ GENERATE_RBF_FILE = OFF;
+ GENERATE_TTF_FILE = OFF;
+ RESERVE_NCSO_AFTER_CONFIGURATION = OFF;
+ RESERVE_ASDO_AFTER_CONFIGURATION = OFF;
+ RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
+ RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
+ RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
+ RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
+ DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
+ AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
+ EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
+ FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_CONFIGURATION_DEVICE = EPC2;
+ CYCLONE_CONFIGURATION_DEVICE = EPC2;
+ FLEX10K_CONFIGURATION_DEVICE = EPC2;
+ FLEX6K_CONFIGURATION_DEVICE = EPC1;
+ MERCURY_CONFIGURATION_DEVICE = EPC2;
+ EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
+ APEX20K_CONFIGURATION_DEVICE = EPC2;
+ USE_CONFIGURATION_DEVICE = ON;
+ ENABLE_INIT_DONE_OUTPUT = OFF;
+ FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+ ENABLE_DEVICE_WIDE_OE = OFF;
+ ENABLE_DEVICE_WIDE_RESET = OFF;
+ RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
+ AUTO_RESTART_CONFIGURATION = OFF;
+ ENABLE_VREFB_PIN = OFF;
+ ENABLE_VREFA_PIN = OFF;
+ SECURITY_BIT = OFF;
+ USER_START_UP_CLOCK = OFF;
+ APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
+ STRATIX_UPDATE_MODE = STANDARD;
+ USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
+ MAX7000_JTAG_USER_CODE = FFFFFFFF;
+ FLEX10K_JTAG_USER_CODE = 7F;
+ MERCURY_JTAG_USER_CODE = FFFFFFFF;
+ APEX20K_JTAG_USER_CODE = FFFFFFFF;
+ STRATIX_JTAG_USER_CODE = FFFFFFFF;
+ RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
+ FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
+ ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
+ MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
+ ENABLE_JTAG_BST_SUPPORT = OFF;
+ CLOCK_DIVISOR = 1;
+ CLOCK_FREQUENCY = "10 MHZ";
+ CLOCK_SOURCE = INTERNAL;
+ COMPRESSION_MODE = OFF;
+ ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
+}
+AUTO_SLD_HUB_ENTITY
+{
+ AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
+ HUB_INSTANCE_NAME = sld_hub_inst;
+ HUB_ENTITY_NAME = sld_hub;
+}
+CHIP(cfplayer)
+{
+ DEVICE = EP1C20F400C7;
+ DEVICE_FILTER_PACKAGE = ANY;
+ DEVICE_FILTER_PIN_COUNT = ANY;
+ DEVICE_FILTER_SPEED_GRADE = ANY;
+ clkin : LOCATION = Pin_K5;
+ proto1_clkout : LOCATION = Pin_K6;
+ proto2_clkout : LOCATION = Pin_K14;
+ pld_clkout : LOCATION = Pin_L8;
+ pld_clkfb : LOCATION = Pin_L14;
+ sd_clk : LOCATION = Pin_L13;
+ vga_r[0] : LOCATION = Pin_U12;
+ vga_r[1] : LOCATION = Pin_V12;
+ vga_r[2] : LOCATION = Pin_T13;
+ vga_r[3] : LOCATION = Pin_R13;
+ vga_r[4] : LOCATION = Pin_Y13;
+ vga_r[5] : LOCATION = Pin_W13;
+ vga_r[6] : LOCATION = Pin_U13;
+ vga_r[7] : LOCATION = Pin_V13;
+ vga_g[0] : LOCATION = Pin_T15;
+ vga_g[1] : LOCATION = Pin_W15;
+ vga_g[2] : LOCATION = Pin_Y15;
+ vga_g[3] : LOCATION = Pin_U15;
+ vga_g[4] : LOCATION = Pin_V15;
+ vga_g[5] : LOCATION = Pin_V14;
+ vga_g[6] : LOCATION = Pin_U14;
+ vga_g[7] : LOCATION = Pin_Y14;
+ vga_b[0] : LOCATION = Pin_T12;
+ vga_b[1] : LOCATION = Pin_T11;
+ vga_b[2] : LOCATION = Pin_W12;
+ vga_b[4] : LOCATION = Pin_Y12;
+ vga_b[3] : LOCATION = Pin_W8;
+ vga_b[5] : LOCATION = Pin_Y8;
+ vga_b[6] : LOCATION = Pin_V9;
+ vga_b[7] : LOCATION = Pin_U9;
+ vga_hs : LOCATION = Pin_T9;
+ vga_vs : LOCATION = Pin_R9;
+ vga_blank_n : LOCATION = Pin_R14;
+ vga_sync_n : LOCATION = Pin_T14;
+ vga_sync_t : LOCATION = Pin_W14;
+ vga_m1 : LOCATION = Pin_V11;
+ vga_m2 : LOCATION = Pin_U11;
+ audio_l : LOCATION = Pin_W9;
+ audio_r : LOCATION = Pin_U10;
+ ps2_sel : LOCATION = Pin_W10;
+ ps2_kclk : LOCATION = Pin_Y10;
+ ps2_kdata : LOCATION = Pin_V10;
+ ps2_mclk : LOCATION = Pin_T10;
+ ps2_mdata : LOCATION = Pin_Y9;
+ cf_d[3] : LOCATION = Pin_F18;
+ cf_d[4] : LOCATION = Pin_E17;
+ cf_d[5] : LOCATION = Pin_D17;
+ cf_d[6] : LOCATION = Pin_D18;
+ cf_d[7] : LOCATION = Pin_C18;
+ cf_ce1_n : LOCATION = Pin_H20;
+ cf_a[10] : LOCATION = Pin_J15;
+ cf_oe_n : LOCATION = Pin_D13;
+ cf_a[9] : LOCATION = Pin_J20;
+ cf_a[8] : LOCATION = Pin_H14;
+ cf_a[7] : LOCATION = Pin_J14;
+ cf_a[6] : LOCATION = Pin_J17;
+ cf_a[5] : LOCATION = Pin_J18;
+ cf_a[4] : LOCATION = Pin_K15;
+ cf_a[3] : LOCATION = Pin_W18;
+ cf_a[2] : LOCATION = Pin_H19;
+ cf_a[1] : LOCATION = Pin_H18;
+ cf_a[0] : LOCATION = Pin_H17;
+ cf_d[0] : LOCATION = Pin_F20;
+ cf_d[1] : LOCATION = Pin_F15;
+ cf_d[2] : LOCATION = Pin_E19;
+ cf_wp : LOCATION = Pin_H16;
+ cf_cd1_n : LOCATION = Pin_B13;
+ cf_d[11] : LOCATION = Pin_F17;
+ cf_d[12] : LOCATION = Pin_E18;
+ cf_d[13] : LOCATION = Pin_F16;
+ cf_d[14] : LOCATION = Pin_F19;
+ cf_d[15] : LOCATION = Pin_G16;
+ cf_ce2_n : LOCATION = Pin_U19;
+ cf_iord_n : LOCATION = Pin_G19;
+ cf_iowr_n : LOCATION = Pin_G20;
+ cf_we_n : LOCATION = Pin_V18;
+ cf_rdy : LOCATION = Pin_G17;
+ cf_wait_n : LOCATION = Pin_G14;
+ cf_inpack_n : LOCATION = Pin_V19;
+ cf_reg_n : LOCATION = Pin_U20;
+ cf_bvd2 : LOCATION = Pin_J16;
+ cf_bvd1 : LOCATION = Pin_J19;
+ cf_d[8] : LOCATION = Pin_C19;
+ cf_d[9] : LOCATION = Pin_D19;
+ cf_d[10] : LOCATION = Pin_D20;
+ sd_a[0] : LOCATION = Pin_M2;
+ sd_a[1] : LOCATION = Pin_M1;
+ sd_a[2] : LOCATION = Pin_M6;
+ sd_a[3] : LOCATION = Pin_M4;
+ sd_a[4] : LOCATION = Pin_J8;
+ sd_a[5] : LOCATION = Pin_J7;
+ sd_a[6] : LOCATION = Pin_J6;
+ sd_a[7] : LOCATION = Pin_J5;
+ sd_a[8] : LOCATION = Pin_J4;
+ sd_a[9] : LOCATION = Pin_J3;
+ sd_a[10] : LOCATION = Pin_H6;
+ sd_a[11] : LOCATION = Pin_H5;
+ sd_ba[0] : LOCATION = Pin_H7;
+ sd_ba[1] : LOCATION = Pin_H1;
+ sd_dq[0] : LOCATION = Pin_M5;
+ sd_dq[1] : LOCATION = Pin_M3;
+ sd_dq[2] : LOCATION = Pin_M7;
+ sd_dq[3] : LOCATION = Pin_N6;
+ sd_dq[4] : LOCATION = Pin_N1;
+ sd_dq[5] : LOCATION = Pin_N2;
+ sd_dq[6] : LOCATION = Pin_N4;
+ sd_dq[7] : LOCATION = Pin_N3;
+ sd_dq[8] : LOCATION = Pin_N5;
+ sd_dq[9] : LOCATION = Pin_N7;
+ sd_dq[10] : LOCATION = Pin_P7;
+ sd_dq[11] : LOCATION = Pin_P2;
+ sd_dq[12] : LOCATION = Pin_P1;
+ sd_dq[13] : LOCATION = Pin_P6;
+ sd_dq[14] : LOCATION = Pin_P5;
+ sd_dq[15] : LOCATION = Pin_P3;
+ sd_dq[16] : LOCATION = Pin_P4;
+ sd_dq[17] : LOCATION = Pin_R1;
+ sd_dq[18] : LOCATION = Pin_R2;
+ sd_dq[19] : LOCATION = Pin_R6;
+ sd_dq[20] : LOCATION = Pin_R5;
+ sd_dq[21] : LOCATION = Pin_R3;
+ sd_dq[22] : LOCATION = Pin_R4;
+ sd_dq[23] : LOCATION = Pin_T4;
+ sd_dq[24] : LOCATION = Pin_T2;
+ sd_dq[25] : LOCATION = Pin_T3;
+ sd_dq[26] : LOCATION = Pin_U1;
+ sd_dq[27] : LOCATION = Pin_U4;
+ sd_dq[28] : LOCATION = Pin_U2;
+ sd_dq[29] : LOCATION = Pin_U3;
+ sd_dq[30] : LOCATION = Pin_V3;
+ sd_dq[31] : LOCATION = Pin_V2;
+ sd_dqm[0] : LOCATION = Pin_J2;
+ sd_dqm[1] : LOCATION = Pin_J1;
+ sd_dqm[2] : LOCATION = Pin_H4;
+ sd_dqm[3] : LOCATION = Pin_H3;
+ sd_ras_n : LOCATION = Pin_H2;
+ sd_cas_n : LOCATION = Pin_G3;
+ sd_cke : LOCATION = Pin_G7;
+ sd_cs_n : LOCATION = Pin_G6;
+ sd_we_n : LOCATION = Pin_G4;
+ p1_a17 : LOCATION = Pin_F20;
+ p1_a21 : LOCATION = Pin_G15;
+ p1_a28 : LOCATION = Pin_H15;
+ p1_a29 : LOCATION = Pin_G18;
+ p1_a38 : LOCATION = Pin_U18;
+ p1_clkout : LOCATION = Pin_P27;
+ ttya_dcd : LOCATION = Pin_M16;
+ ttya_txd : LOCATION = Pin_M14;
+ ttya_rxd : LOCATION = Pin_K16;
+ ttya_dtr : LOCATION = Pin_M15;
+ ttya_dsr : LOCATION = Pin_M20;
+ ttya_rts : LOCATION = Pin_K19;
+ ttya_cts : LOCATION = Pin_J13;
+ ttya_ri : LOCATION = Pin_M19;
+ ttyb_txd : LOCATION = Pin_A13;
+ ttyb_rxd : LOCATION = Pin_C13;
+ s7_0[0] : LOCATION = Pin_U6;
+ s7_0[1] : LOCATION = Pin_V6;
+ s7_0[2] : LOCATION = Pin_W7;
+ s7_0[3] : LOCATION = Pin_Y7;
+ s7_0[4] : LOCATION = Pin_R7;
+ s7_0[5] : LOCATION = Pin_T8;
+ s7_0[6] : LOCATION = Pin_V7;
+ s7_0[7] : LOCATION = Pin_U7;
+ s7_1[0] : LOCATION = Pin_T5;
+ s7_1[1] : LOCATION = Pin_U5;
+ s7_1[2] : LOCATION = Pin_V5;
+ s7_1[3] : LOCATION = Pin_W5;
+ s7_1[4] : LOCATION = Pin_T6;
+ s7_1[5] : LOCATION = Pin_T7;
+ s7_1[6] : LOCATION = Pin_W6;
+ s7_1[7] : LOCATION = Pin_Y6;
+ led[0] : LOCATION = Pin_E14;
+ led[1] : LOCATION = Pin_E13;
+ led[2] : LOCATION = Pin_C14;
+ led[3] : LOCATION = Pin_D14;
+ led[4] : LOCATION = Pin_E12;
+ led[5] : LOCATION = Pin_F12;
+ led[6] : LOCATION = Pin_B3;
+ led[7] : LOCATION = Pin_B14;
+ sw[0] : LOCATION = Pin_W3;
+ sw[1] : LOCATION = Pin_Y4;
+ sw[2] : LOCATION = Pin_V4;
+ sw[3] : LOCATION = Pin_W4;
+ fse_a[0] : LOCATION = Pin_B4;
+ fse_a[1] : LOCATION = Pin_A4;
+ fse_a[2] : LOCATION = Pin_D5;
+ fse_a[3] : LOCATION = Pin_D6;
+ fse_a[4] : LOCATION = Pin_C5;
+ fse_a[5] : LOCATION = Pin_B5;
+ fse_a[6] : LOCATION = Pin_C2;
+ fse_a[7] : LOCATION = Pin_D2;
+ fse_a[8] : LOCATION = Pin_D4;
+ fse_a[9] : LOCATION = Pin_D1;
+ fse_a[10] : LOCATION = Pin_E4;
+ fse_a[11] : LOCATION = Pin_E5;
+ fse_a[12] : LOCATION = Pin_F3;
+ fse_a[13] : LOCATION = Pin_E3;
+ fse_a[14] : LOCATION = Pin_E2;
+ fse_a[15] : LOCATION = Pin_F4;
+ fse_a[16] : LOCATION = Pin_F5;
+ fse_a[17] : LOCATION = Pin_F2;
+ fse_a[18] : LOCATION = Pin_F1;
+ fse_a[19] : LOCATION = Pin_F6;
+ fse_a[20] : LOCATION = Pin_G5;
+ fse_a[21] : LOCATION = Pin_G1;
+ fse_a[22] : LOCATION = Pin_G2;
+ fse_d[0] : LOCATION = Pin_C6;
+ fse_d[1] : LOCATION = Pin_E6;
+ fse_d[2] : LOCATION = Pin_B6;
+ fse_d[3] : LOCATION = Pin_A6;
+ fse_d[4] : LOCATION = Pin_F7;
+ fse_d[5] : LOCATION = Pin_E7;
+ fse_d[6] : LOCATION = Pin_B7;
+ fse_d[7] : LOCATION = Pin_A7;
+ fse_d[8] : LOCATION = Pin_D7;
+ fse_d[9] : LOCATION = Pin_C7;
+ fse_d[10] : LOCATION = Pin_F8;
+ fse_d[11] : LOCATION = Pin_E8;
+ fse_d[12] : LOCATION = Pin_B8;
+ fse_d[13] : LOCATION = Pin_A8;
+ fse_d[14] : LOCATION = Pin_D8;
+ fse_d[15] : LOCATION = Pin_C8;
+ fse_d[16] : LOCATION = Pin_B9;
+ fse_d[17] : LOCATION = Pin_A9;
+ fse_d[18] : LOCATION = Pin_D9;
+ fse_d[19] : LOCATION = Pin_C9;
+ fse_d[20] : LOCATION = Pin_E9;
+ fse_d[21] : LOCATION = Pin_E10;
+ fse_d[22] : LOCATION = Pin_B10;
+ fse_d[23] : LOCATION = Pin_A10;
+ fse_d[24] : LOCATION = Pin_F10;
+ fse_d[25] : LOCATION = Pin_C10;
+ fse_d[26] : LOCATION = Pin_D10;
+ fse_d[27] : LOCATION = Pin_C11;
+ fse_d[28] : LOCATION = Pin_D11;
+ fse_d[29] : LOCATION = Pin_B11;
+ fse_d[30] : LOCATION = Pin_A11;
+ fse_d[31] : LOCATION = Pin_E11;
+ flash_cs_n : LOCATION = Pin_A12;
+ flash_oe_n : LOCATION = Pin_B12;
+ flash_rw_n : LOCATION = Pin_D12;
+ flash_ry_by_n : LOCATION = Pin_C12;
+ sram_be_n[0] : LOCATION = Pin_V17;
+ sram_be_n[1] : LOCATION = Pin_V16;
+ sram_be_n[2] : LOCATION = Pin_W16;
+ sram_be_n[3] : LOCATION = Pin_T16;
+ sram_cs_n : LOCATION = Pin_W17;
+ sram_oe_n : LOCATION = Pin_Y17;
+ sram_we_n : LOCATION = Pin_U16;
+ enet_ads_n : LOCATION = Pin_A14;
+ enet_aen : LOCATION = Pin_B15;
+ enet_be_n[0] : LOCATION = Pin_C16;
+ enet_be_n[1] : LOCATION = Pin_B16;
+ enet_be_n[2] : LOCATION = Pin_D16;
+ enet_be_n[3] : LOCATION = Pin_E16;
+ enet_cycle_n : LOCATION = Pin_B17;
+ enet_datacs_n : LOCATION = Pin_C15;
+ enet_intrq0 : LOCATION = Pin_D15;
+ enet_iochrdy : LOCATION = Pin_F14;
+ enet_ior_n : LOCATION = Pin_A15;
+ enet_iow_n : LOCATION = Pin_E15;
+ enet_lclk : LOCATION = Pin_C17;
+ enet_ldev_n : LOCATION = Pin_D3;
+ enet_rdyrtn_n : LOCATION = Pin_B18;
+ enet_w_r_n : LOCATION = Pin_A17;
+}
diff --git a/cfplayer.quartus b/cfplayer.quartus
new file mode 100644
index 0000000..42847a7
--- /dev/null
+++ b/cfplayer.quartus
@@ -0,0 +1,22 @@
+FILES
+{
+ VERILOG_FILE = cfplayer.v;
+ VERILOG_FILE = cfstream.v;
+ VERILOG_FILE = sound.v;
+ VERILOG_FILE = cffifo.v;
+ VERILOG_FILE = pll1.v;
+ CDF_FILE = Chain1.cdf;
+}
+COMPILER_SETTINGS_LIST
+{
+ COMPILER_SETTINGS = cfplayer;
+}
+SIMULATOR_SETTINGS_LIST
+{
+ SIMULATOR_SETTINGS = cfplayer;
+}
+SOFTWARE_SETTINGS_LIST
+{
+ SOFTWARE_SETTINGS = Debug;
+ SOFTWARE_SETTINGS = Release;
+}
diff --git a/cfplayer.v b/cfplayer.v
new file mode 100644
index 0000000..fd97e91
--- /dev/null
+++ b/cfplayer.v
@@ -0,0 +1,185 @@
+/* $Id$ */
+/* ----------------------------------------------------------------------- *
+ *
+ * Copyright 2003 H. Peter Anvin - All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 53 Temple Place Ste 330,
+ * Bostom MA 02111-1307, USA; either version 2 of the License, or
+ * (at your option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * cfplayer.v
+ *
+ * Top-level for sound-playing mechanism
+ *
+ * Plays raw CD-format music written to CompactFlash (without partition
+ * table or filesystem)
+ */
+
+module cfplayer (
+ clkin,
+
+ cf_a,
+ cf_d,
+ cf_rdy,
+ cf_wait_n,
+ cf_ce1_n,
+ cf_ce2_n,
+ cf_oe_n,
+ cf_we_n,
+ cf_reg_n,
+
+ audio_l,
+ audio_r,
+
+ led,
+ s7_0,
+ s7_1,
+ );
+
+ input clkin;
+
+ output [10:0] cf_a;
+ inout [15:0] cf_d;
+ input cf_rdy;
+ input cf_wait_n;
+ output cf_ce1_n;
+ output cf_ce2_n;
+ output cf_oe_n;
+ output cf_we_n;
+ output cf_reg_n;
+
+ output audio_l;
+ output audio_r;
+
+ output [7:0] led;
+ output [7:0] s7_0;
+ output [7:0] s7_1;
+
+ wire [15:0] audio_q;
+ wire data_ready_n;
+ reg [11:0] audio_data_l = 0;
+ reg [11:0] audio_data_r = 0;
+ reg rdreq;
+
+ wire audio_strobe;
+ reg audio_strobe1;
+
+ wire audio_clk;
+ wire cf_clk;
+
+ wire [7:0] s7_val;
+
+ assign led[0] = cf_rdy;
+ assign led[1] = cf_wait_n;
+ assign led[2] = audio_data_l[11];
+ assign led[3] = audio_data_r[11];
+ assign led[4] = audio_l;
+ assign led[5] = audio_r;
+ assign led[6] = audio_strobe;
+ assign led[7] = data_ready_n;
+
+ // Primary PLL for design
+ pll1 pll1_inst (
+ .inclk0 ( clkin ), // 50 MHz clkin
+ .pllena ( 1 ), // PLL enable
+ .areset ( 0 ), // PLL reset
+ .c0 ( audio_clk ), // Audio clock - 200 MHz
+ .c1 ( cf_clk ) // CompactFlash clock - 12.5 MHz
+ );
+
+ // CompactFlash read unit
+ cfstream cfstream_inst (
+ .clk ( cf_clk ),
+ .cf_a ( cf_a ),
+ .cf_d ( cf_d ),
+ .cf_bsy_n ( cf_rdy ),
+ .cf_wait_n ( cf_wait_n ),
+ .cf_ce1_n ( cf_ce1_n ),
+ .cf_ce2_n ( cf_ce2_n ),
+ .cf_oe_n ( cf_oe_n ),
+ .cf_we_n ( cf_we_n ),
+ .cf_reg_n ( cf_reg_n ),
+ .q ( audio_q ),
+ .data_ready_n ( data_ready_n ),
+ .rdreq ( rdreq ),
+ .bsy_time ( s7_val )
+ );
+
+ // We need to advance the FIFO exactly one datum for each
+ // time the audio core latches a datum.
+ always @( posedge cf_clk )
+ begin
+ rdreq <= ( audio_strobe & ~audio_strobe1 & ~data_ready_n );
+ audio_strobe1 <= audio_strobe;
+
+ if ( rdreq )
+ begin
+ // Careful here - get the endianism, signedness and
+ // LSB truncation right
+ audio_data_l[11] <= ~audio_q[7]; // Signed data
+ audio_data_l[10:4] <= audio_q[6:0];
+ audio_data_l[3:0] <= audio_q[15:12];
+ audio_data_r[11] <= ~audio_q[7]; // Signed data
+ audio_data_r[10:4] <= audio_q[6:0];
+ audio_data_r[3:0] <= audio_q[15:12];
+ end
+ end
+
+ always @( s7_val )
+ begin
+ case ( s7_val[7:4] )
+ 4'h0: s7_1 = ~8'b00111111;
+ 4'h1: s7_1 = ~8'b00000110;
+ 4'h2: s7_1 = ~8'b01011011;
+ 4'h3: s7_1 = ~8'b01001111;
+ 4'h4: s7_1 = ~8'b01100110;
+ 4'h5: s7_1 = ~8'b01101101;
+ 4'h6: s7_1 = ~8'b01111101;
+ 4'h7: s7_1 = ~8'b00000111;
+ 4'h8: s7_1 = ~8'b01111111;
+ 4'h9: s7_1 = ~8'b01101111;
+ 4'hA: s7_1 = ~8'b01110111;
+ 4'hB: s7_1 = ~8'b01111100;
+ 4'hC: s7_1 = ~8'b00111001;
+ 4'hD: s7_1 = ~8'b01011110;
+ 4'hE: s7_1 = ~8'b01111001;
+ 4'hF: s7_1 = ~8'b01110001;
+ endcase
+ case ( s7_val[3:0] )
+ 4'h0: s7_0 = ~8'b00111111;
+ 4'h1: s7_0 = ~8'b00000110;
+ 4'h2: s7_0 = ~8'b01011011;
+ 4'h3: s7_0 = ~8'b01001111;
+ 4'h4: s7_0 = ~8'b01100110;
+ 4'h5: s7_0 = ~8'b01101101;
+ 4'h6: s7_0 = ~8'b01111101;
+ 4'h7: s7_0 = ~8'b00000111;
+ 4'h8: s7_0 = ~8'b01111111;
+ 4'h9: s7_0 = ~8'b01101111;
+ 4'hA: s7_0 = ~8'b01110111;
+ 4'hB: s7_0 = ~8'b01111100;
+ 4'hC: s7_0 = ~8'b00111001;
+ 4'hD: s7_0 = ~8'b01011110;
+ 4'hE: s7_0 = ~8'b01111001;
+ 4'hF: s7_0 = ~8'b01110001;
+ endcase
+ end
+
+ sound sound_inst (
+ .clk ( audio_clk ),
+ // Careful here -- remember CD data is bigendian
+ // The sound module takes 12-bit inputs; throw away
+ // 4 LSB
+ .data_l ( audio_data_l ),
+ .data_r ( audio_data_r ),
+ .audio_l ( audio_l ),
+ .audio_r ( audio_r ),
+ .audio_clk ( audio_strobe ),
+ );
+
+endmodule // cfplayer
diff --git a/cfstream.v b/cfstream.v
new file mode 100644
index 0000000..a733c70
--- /dev/null
+++ b/cfstream.v
@@ -0,0 +1,228 @@
+/* ----------------------------------------------------------------------- *
+ *
+ * Copyright 2003 H. Peter Anvin - All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 53 Temple Place Ste 330,
+ * Bostom MA 02111-1307, USA; either version 2 of the License, or
+ * (at your option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+module cfstream(
+ clk, // 2-20 MHz
+
+ cf_a,
+ cf_d,
+ cf_bsy_n,
+ cf_wait_n,
+ cf_ce1_n,
+ cf_ce2_n,
+ cf_oe_n,
+ cf_we_n,
+ cf_reg_n,
+
+ q,
+ data_ready_n,
+ rdreq,
+
+ bsy_time
+ );
+
+ input clk;
+ output [10:0] cf_a;
+ inout [15:0] cf_d;
+ input cf_bsy_n;
+ input cf_wait_n;
+ output cf_ce1_n, cf_ce2_n;
+ output cf_oe_n;
+ output cf_we_n;
+ output cf_reg_n;
+
+ output [15:0] q;
+ output data_ready_n;
+ input rdreq;
+
+ output [7:0] bsy_time;
+
+ reg [27:0] lba = 0;
+ reg [7:0] wordix; // 256 words @ 16 bits/sector
+
+ reg [15:0] cf_data;
+ reg wrreq;
+ wire fifo_full;
+ wire fifo_almost_full;
+
+ // Megafunction FIFO
+ cffifo cffifo_inst (
+ .data ( cf_data ),
+ .wrreq ( wrreq ),
+ .rdreq ( rdreq ),
+ .clock ( clk ),
+ .q ( q ),
+ .full ( fifo_full ),
+ .empty ( data_ready_n ),
+ .almost_full ( fifo_almost_full ) // Less than 128 words free
+ );
+
+`define FSM_IDLE 4'h0
+`define FSM_SEND_23 4'h1
+`define FSM_WAIT_23 4'h2
+`define FSM_SEND_45 4'h3
+`define FSM_WAIT_45 4'h4
+`define FSM_SEND_67 4'h5
+`define FSM_WAIT_67 4'h6
+`define FSM_WAIT_BSY 4'h7
+`define FSM_WAIT_RDY 4'h8
+`define FSM_GET_DATA 4'h9
+`define FSM_WAIT_DATA 4'hA
+
+ reg [3:0] state;
+
+ reg [15:0] out_d;
+ reg drive_d;
+ assign cf_d = drive_d ? out_d : 16'bz;
+
+ assign cf_reg_n = 1; // Common memory
+ assign cf_ce1_n = 0; // 16-bit Common Memory
+ assign cf_ce2_n = 0; // 16-bit Common Memory
+
+ reg [23:0] bsy_ctr;
+ reg [7:0] bsy_time_q = 0;
+ assign bsy_time = bsy_time_q;
+
+ always @(posedge clk)
+ begin
+ wrreq <= 0;
+
+ case (state)
+ `FSM_IDLE:
+ begin
+ cf_a <= 11'h002;
+ out_d <= 16'bx;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 1;
+
+ if ( !fifo_almost_full )
+ state <= `FSM_SEND_23;
+ end
+
+ `FSM_SEND_23:
+ begin
+ out_d[7:0] <= 8'h01;
+ out_d[15:8] <= lba[7:0];
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ state <= `FSM_WAIT_23;
+ end
+
+ `FSM_WAIT_23:
+ begin
+ if ( cf_wait_n )
+ begin
+ cf_a <= 11'h004;
+ state <= `FSM_SEND_45;
+ cf_we_n <= 1;
+ end
+ end
+
+ `FSM_SEND_45:
+ begin
+ out_d <= lba[23:8];
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ state <= `FSM_WAIT_45;
+ end
+
+ `FSM_WAIT_45:
+ begin
+ if ( cf_wait_n )
+ begin
+ cf_a <= 11'h006;
+ state <= `FSM_SEND_67;
+ cf_we_n <= 1;
+ end
+ end
+
+ `FSM_SEND_67:
+ begin
+ out_d[3:0] <= lba[27:24];
+ out_d[7:4] <= 4'hE;
+ out_d[15:8] <= 8'h20;
+ drive_d <= 1;
+ cf_we_n <= 0;
+ cf_oe_n <= 1;
+ state <= `FSM_WAIT_67;
+
+ lba <= lba + 1;
+ end
+
+ `FSM_WAIT_67:
+ begin
+ bsy_ctr <= 0;
+
+ if ( cf_wait_n )
+ begin
+ cf_a <= 11'h000;
+ state <= cf_bsy_n ? `FSM_WAIT_BSY : `FSM_WAIT_RDY;
+ cf_we_n <= 1;
+ drive_d <= 0;
+ end
+ wordix <= 0;
+ end
+
+ `FSM_WAIT_BSY:
+ begin
+ bsy_ctr <= bsy_ctr + 1;
+ if ( !cf_bsy_n )
+ state <= `FSM_WAIT_RDY;
+ end
+
+ `FSM_WAIT_RDY:
+ begin
+ bsy_ctr <= bsy_ctr + 1;
+ if ( cf_bsy_n )
+ state <= `FSM_GET_DATA;
+ end
+
+ `FSM_GET_DATA:
+ begin
+ if ( bsy_time_q < bsy_ctr[23:16] )
+ bsy_time_q <= bsy_ctr[23:16];
+
+ cf_a <= 11'h000;
+ drive_d <= 0;
+ cf_we_n <= 1;
+ cf_oe_n <= 0;
+ state <= `FSM_WAIT_DATA;
+ end
+
+ `FSM_WAIT_DATA:
+ begin
+ if ( cf_wait_n )
+ begin
+ cf_oe_n <= 1;
+ cf_data <= cf_d;
+ wrreq <= 1;
+ state <= ( &wordix ) ? `FSM_IDLE : `FSM_GET_DATA;
+ wordix <= wordix + 1;
+ end
+ end
+
+ default:
+ begin
+ cf_a <= 11'bx;
+ out_d <= 16'bx;
+ drive_d <= 1'bx;
+ cf_we_n <= 1'bx;
+ cf_oe_n <= 1'bx;
+ state <= 4'bx;
+ end
+ endcase
+ end // always @ (posedge clk)
+
+endmodule
diff --git a/pll1.bsf b/pll1.bsf
new file mode 100644
index 0000000..d2a9f85
--- /dev/null
+++ b/pll1.bsf
@@ -0,0 +1,104 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2003 Altera Corporation
+Any megafunction design, and related netlist (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only
+to program PLD devices (but not masked PLD devices) from Altera. Any
+other use of such megafunction design, netlist, support information,
+device programming or simulation file, or any other related documentation
+or information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner. Title to the
+intellectual property, including patents, copyrights, trademarks, trade
+secrets, or maskworks, embodied in any such megafunction design, netlist,
+support information, device programming or simulation file, or any other
+related documentation or information provided by Altera or a megafunction
+partner, remains with Altera, the megafunction partner, or their respective
+licensors. No other licenses, including any licenses needed under any third
+party's intellectual property, are provided herein.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 280 176)
+ (text "pll1" (rect 140 0 162 16)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 160 24 172)(font "Arial" ))
+ (port
+ (pt 0 64)
+ (input)
+ (text "inclk0" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+ (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+ (line (pt 0 64)(pt 48 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "pllena" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "pllena" (rect 4 67 34 80)(font "Arial" (font_size 8)))
+ (line (pt 0 80)(pt 48 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "areset" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+ (text "areset" (rect 4 83 32 96)(font "Arial" (font_size 8)))
+ (line (pt 0 96)(pt 48 96)(line_width 1))
+ )
+ (port
+ (pt 280 64)
+ (output)
+ (text "c0" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c0" (rect 265 51 276 64)(font "Arial" (font_size 8)))
+ (line (pt 280 64)(pt 248 64)(line_width 1))
+ )
+ (port
+ (pt 280 80)
+ (output)
+ (text "c1" (rect 0 0 13 14)(font "Arial" (font_size 8)))
+ (text "c1" (rect 265 67 276 80)(font "Arial" (font_size 8)))
+ (line (pt 280 80)(pt 248 80)(line_width 1))
+ )
+ (drawing
+ (text "inclk0 frequency: 50.000 MHz" (rect 58 59 183 71)(font "Arial" ))
+ (text "Operation Mode: Normal" (rect 58 73 159 85)(font "Arial" ))
+ (text "Clk " (rect 59 96 76 108)(font "Arial" ))
+ (text "Ratio" (rect 81 96 103 108)(font "Arial" ))
+ (text "Ph (dg)" (rect 108 96 138 108)(font "Arial" ))
+ (text "Td (ns)" (rect 143 96 172 108)(font "Arial" ))
+ (text "DC (%)" (rect 177 96 208 108)(font "Arial" ))
+ (text "c0" (rect 62 111 72 123)(font "Arial" ))
+ (text "4/1" (rect 86 111 99 123)(font "Arial" ))
+ (text "0.00" (rect 114 111 132 123)(font "Arial" ))
+ (text "0.00" (rect 148 111 166 123)(font "Arial" ))
+ (text "50.00" (rect 181 111 204 123)(font "Arial" ))
+ (text "c1" (rect 62 126 72 138)(font "Arial" ))
+ (text "1/4" (rect 86 126 99 138)(font "Arial" ))
+ (text "0.00" (rect 114 126 132 138)(font "Arial" ))
+ (text "0.00" (rect 148 126 166 138)(font "Arial" ))
+ (text "50.00" (rect 181 126 204 138)(font "Arial" ))
+ (line (pt 0 0)(pt 281 0)(line_width 1))
+ (line (pt 281 0)(pt 281 177)(line_width 1))
+ (line (pt 0 177)(pt 281 177)(line_width 1))
+ (line (pt 0 0)(pt 0 177)(line_width 1))
+ (line (pt 56 94)(pt 210 94)(line_width 1))
+ (line (pt 56 108)(pt 210 108)(line_width 1))
+ (line (pt 56 123)(pt 210 123)(line_width 1))
+ (line (pt 56 138)(pt 210 138)(line_width 1))
+ (line (pt 56 94)(pt 56 138)(line_width 1))
+ (line (pt 78 94)(pt 78 138)(line_width 3))
+ (line (pt 105 94)(pt 105 138)(line_width 3))
+ (line (pt 140 94)(pt 140 138)(line_width 3))
+ (line (pt 174 94)(pt 174 138)(line_width 3))
+ (line (pt 209 94)(pt 209 138)(line_width 1))
+ (line (pt 48 48)(pt 248 48)(line_width 1))
+ (line (pt 248 48)(pt 248 160)(line_width 1))
+ (line (pt 48 160)(pt 248 160)(line_width 1))
+ (line (pt 48 48)(pt 48 160)(line_width 1))
+ )
+)
diff --git a/pll1.cmp b/pll1.cmp
new file mode 100644
index 0000000..352d66a
--- /dev/null
+++ b/pll1.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component pll1
+ PORT
+ (
+ inclk0 : IN STD_LOGIC := '0';
+ pllena : IN STD_LOGIC := '1';
+ areset : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC
+ );
+end component;
diff --git a/pll1.inc b/pll1.inc
new file mode 100644
index 0000000..4499f09
--- /dev/null
+++ b/pll1.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any megafunction design, and related netlist (encrypted or decrypted),
+--support information, device programming or simulation file, and any other
+--associated documentation or information provided by Altera or a partner
+--under Altera's Megafunction Partnership Program may be used only
+--to program PLD devices (but not masked PLD devices) from Altera. Any
+--other use of such megafunction design, netlist, support information,
+--device programming or simulation file, or any other related documentation
+--or information is prohibited for any other purpose, including, but not
+--limited to modification, reverse engineering, de-compiling, or use with
+--any other silicon devices, unless such use is explicitly licensed under
+--a separate agreement with Altera or a megafunction partner. Title to the
+--intellectual property, including patents, copyrights, trademarks, trade
+--secrets, or maskworks, embodied in any such megafunction design, netlist,
+--support information, device programming or simulation file, or any other
+--related documentation or information provided by Altera or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+FUNCTION pll1
+(
+ inclk0,
+ pllena,
+ areset
+)
+
+RETURNS (
+ c0,
+ c1
+);
diff --git a/pll1.v b/pll1.v
new file mode 100644
index 0000000..eca47a8
--- /dev/null
+++ b/pll1.v
@@ -0,0 +1,198 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll1.v
+// Megafunction Name(s):
+// altpll
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+// ************************************************************
+
+
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+
+module pll1 (
+ inclk0,
+ pllena,
+ areset,
+ c0,
+ c1);
+
+ input inclk0;
+ input pllena;
+ input areset;
+ output c0;
+ output c1;
+
+ wire [5:0] sub_wire0;
+ wire [0:0] sub_wire5 = 1'h0;
+ wire [1:1] sub_wire2 = sub_wire0[1:1];
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire c1 = sub_wire2;
+ wire sub_wire3 = inclk0;
+ wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+ altpll altpll_component (
+ .inclk (sub_wire4),
+ .pllena (pllena),
+ .areset (areset),
+ .clk (sub_wire0));
+ defparam
+ altpll_component.clk1_divide_by = 4,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.clk0_multiply_by = 4,
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.pll_type = "AUTO",
+ altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk0_time_delay = "0",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.clk1_time_delay = "0",
+ altpll_component.clk0_phase_shift = "0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: JUMP2PAGE0 STRING "General/Modes"
+// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: JUMP2PAGE1 STRING "General/Modes"
+// Retrieval info: PRIVATE: TIME_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: JUMP2PAGE2 STRING "General/Modes"
+// Retrieval info: PRIVATE: USE_CLKENA6 STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: MIRROR_CLK6 STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "deg"
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
+// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: TIME_SHIFT6 STRING "0.00000000"
+// Retrieval info: PRIVATE: STICKY_CLK6 STRING "0"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "4"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: USE_CLK6 STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: JUMP2PAGE STRING "Clock switchover"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: CLK1_TIME_DELAY STRING "0"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
+// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
diff --git a/pll1_bb.v b/pll1_bb.v
new file mode 100644
index 0000000..0c9f171
--- /dev/null
+++ b/pll1_bb.v
@@ -0,0 +1,35 @@
+//Copyright (C) 1991-2003 Altera Corporation
+//Any megafunction design, and related netlist (encrypted or decrypted),
+//support information, device programming or simulation file, and any other
+//associated documentation or information provided by Altera or a partner
+//under Altera's Megafunction Partnership Program may be used only
+//to program PLD devices (but not masked PLD devices) from Altera. Any
+//other use of such megafunction design, netlist, support information,
+//device programming or simulation file, or any other related documentation
+//or information is prohibited for any other purpose, including, but not
+//limited to modification, reverse engineering, de-compiling, or use with
+//any other silicon devices, unless such use is explicitly licensed under
+//a separate agreement with Altera or a megafunction partner. Title to the
+//intellectual property, including patents, copyrights, trademarks, trade
+//secrets, or maskworks, embodied in any such megafunction design, netlist,
+//support information, device programming or simulation file, or any other
+//related documentation or information provided by Altera or a megafunction
+//partner, remains with Altera, the megafunction partner, or their respective
+//licensors. No other licenses, including any licenses needed under any third
+//party's intellectual property, are provided herein.
+
+module pll1 (
+ inclk0,
+ pllena,
+ areset,
+ c0,
+ c1);
+
+ input inclk0;
+ input pllena;
+ input areset;
+ output c0;
+ output c1;
+
+endmodule
+
diff --git a/pll1_inst.v b/pll1_inst.v
new file mode 100644
index 0000000..979c931
--- /dev/null
+++ b/pll1_inst.v
@@ -0,0 +1,7 @@
+pll1 pll1_inst (
+ .inclk0 ( inclk0_sig ),
+ .pllena ( pllena_sig ),
+ .areset ( areset_sig ),
+ .c0 ( c0_sig ),
+ .c1 ( c1_sig )
+ );
diff --git a/sinewave.c b/sinewave.c
new file mode 100644
index 0000000..6e6180f
--- /dev/null
+++ b/sinewave.c
@@ -0,0 +1,27 @@
+#include <inttypes.h>
+#include <stdio.h>
+#include <netinet/in.h>
+#include <math.h>
+#include <stdlib.h>
+
+int main(int argc, char *argv[])
+{
+ double samplerate = 44100.0;
+ double frequency = atof(argv[1]);
+ int samples = atoi(argv[2]);
+ double increment = 2*M_PI*frequency/samplerate;
+ double x = 0.0;
+ int16_t sample[2];
+
+ fprintf(stderr, "increment = %g\n", increment);
+
+ while ( samples-- ) {
+ int16_t s = htons((int16_t)(sin(x)*32767.0));
+ sample[0] = sample[1] = s;
+ fwrite(sample, 2, 2, stdout);
+
+ x = fmod(x+increment, 2*M_PI);
+ }
+
+ return 0;
+}
diff --git a/sound.v b/sound.v
new file mode 100644
index 0000000..354fd20
--- /dev/null
+++ b/sound.v
@@ -0,0 +1,62 @@
+/*
+ * sound.v
+ *
+ * Circuit to generate PDM sound using an Altera Nios board with an
+ * AleaRep Lancelot sound add-on.
+ *
+ * This module should be fed with a 200 MHz clock from the PLL.
+ */
+
+module sound(
+ clk,
+ data_l,
+ data_r,
+ audio_l,
+ audio_r,
+ audio_clk
+ );
+
+ input clk;
+ input [11:0] data_l;
+ input [11:0] data_r;
+ output audio_l;
+ output audio_r;
+ output audio_clk;
+
+ reg [12:0] pulse_ctr;
+ reg [12:0] gen_ctr_l;
+ reg [12:0] gen_ctr_r;
+
+ // This gives 12-bit sound at 44100 Hz. A high sample rate will
+ // help avoid actually making the sampling frequency audible.
+ // The low-pass filter on the Lancelot has its knee at 10 kHz, and
+ // (being a first-order filter) drops off at 3 dB/octave.
+
+ // Note: the input is expected unsigned. For signed input, invert
+ // bit 11.
+
+ always @(posedge clk)
+ begin
+ if ( pulse_ctr == 0 )
+ begin
+ pulse_ctr <= 4535-1; // 44100 Hz sample rate
+ gen_ctr_l <= data_l+256; // Really should be 218, but 256 is
+ gen_ctr_r <= data_r+256; // close enough and cheaper to add
+ end
+ else
+ begin
+ pulse_ctr <= pulse_ctr-1;
+ gen_ctr_l <= gen_ctr_l-1;
+ gen_ctr_r <= gen_ctr_r-1;
+ end
+ end
+
+ // Definitely *not* a 50% duty cycle; goes high immediately after
+ // the data item has been latched
+ assign audio_clk = pulse_ctr[12];
+
+ assign audio_l = ~gen_ctr_l[12];
+ assign audio_r = ~gen_ctr_r[12];
+
+
+endmodule // sound