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authorH. Peter Anvin <hpa@zytor.com>2003-08-29 03:47:16 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2003-08-29 03:47:16 (GMT)
commit148439557dbb402ef8c9d95a454d0bfa164646b9 (patch)
tree4c546dff8df684e6e677c88f558c4e3d81d8a0e3
parent2418a7bd1c30780d6237b5c31a13b5d7d474138d (diff)
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Use a 16-bit delta-sigma converter instead of PDM, even though it
really should be clocked faster than 200 MHz.
-rw-r--r--cfplayer.csf4
-rw-r--r--cfplayer.v18
-rw-r--r--sound.v67
3 files changed, 63 insertions, 26 deletions
diff --git a/cfplayer.csf b/cfplayer.csf
index 0027536..2988506 100644
--- a/cfplayer.csf
+++ b/cfplayer.csf
@@ -52,11 +52,13 @@ COMPILER_SETTINGS
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
OPTIMIZE_TIMING = NORMAL_COMPILATION;
COMPILATION_LEVEL = FULL;
- SAVE_DISK_SPACE = ON;
+ SAVE_DISK_SPACE = OFF;
SPEED_DISK_USAGE_TRADEOFF = NORMAL;
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
SIGNALPROBE_ALLOW_OVERUSE = OFF;
FOCUS_ENTITY_NAME = |cfplayer;
+ ROUTING_BACK_ANNOTATION_MODE = OFF;
+ INC_PLC_MODE = OFF;
}
DEFAULT_DEVICE_OPTIONS
{
diff --git a/cfplayer.v b/cfplayer.v
index fd97e91..4c76a8d 100644
--- a/cfplayer.v
+++ b/cfplayer.v
@@ -62,8 +62,8 @@ module cfplayer (
wire [15:0] audio_q;
wire data_ready_n;
- reg [11:0] audio_data_l = 0;
- reg [11:0] audio_data_r = 0;
+ reg [15:0] audio_data_l = 0;
+ reg [15:0] audio_data_r = 0;
reg rdreq;
wire audio_strobe;
@@ -121,12 +121,12 @@ module cfplayer (
begin
// Careful here - get the endianism, signedness and
// LSB truncation right
- audio_data_l[11] <= ~audio_q[7]; // Signed data
- audio_data_l[10:4] <= audio_q[6:0];
- audio_data_l[3:0] <= audio_q[15:12];
- audio_data_r[11] <= ~audio_q[7]; // Signed data
- audio_data_r[10:4] <= audio_q[6:0];
- audio_data_r[3:0] <= audio_q[15:12];
+ audio_data_l[15] <= ~audio_q[7]; // Signed data
+ audio_data_l[14:8] <= audio_q[6:0];
+ audio_data_l[7:0] <= audio_q[15:8];
+ audio_data_r[15] <= ~audio_q[7]; // Signed data
+ audio_data_r[14:8] <= audio_q[6:0];
+ audio_data_r[7:0] <= audio_q[15:8];
end
end
@@ -173,8 +173,6 @@ module cfplayer (
sound sound_inst (
.clk ( audio_clk ),
// Careful here -- remember CD data is bigendian
- // The sound module takes 12-bit inputs; throw away
- // 4 LSB
.data_l ( audio_data_l ),
.data_r ( audio_data_r ),
.audio_l ( audio_l ),
diff --git a/sound.v b/sound.v
index 354fd20..eb5bf3d 100644
--- a/sound.v
+++ b/sound.v
@@ -5,8 +5,14 @@
* AleaRep Lancelot sound add-on.
*
* This module should be fed with a 200 MHz clock from the PLL.
+ *
+ * This is a delta-sigma DAC, assuming an external low pass filter.
*/
+`define BITS 16
+`define MSB (`BITS-1)
+`define DBITS (`BITS+1)
+
module sound(
clk,
data_l,
@@ -17,46 +23,77 @@ module sound(
);
input clk;
- input [11:0] data_l;
- input [11:0] data_r;
+ input [`MSB:0] data_l;
+ input [`MSB:0] data_r;
output audio_l;
output audio_r;
output audio_clk;
+ reg [`MSB:0] data_latch_l;
+ reg [`MSB:0] data_latch_r;
+
+ wire [`DBITS:0] delta_add_l;
+ wire [`DBITS:0] delta_add_r;
+
+ wire [`DBITS:0] sigma_add_l;
+ wire [`DBITS:0] sigma_add_r;
+
+ reg [`DBITS:0] sigma_latch_l;
+ reg [`DBITS:0] sigma_latch_r;
+
+ wire [`DBITS:0] delta_l;
+ wire [`DBITS:0] delta_r;
+
+ reg out_latch_l;
+ reg out_latch_r;
+
reg [12:0] pulse_ctr;
- reg [12:0] gen_ctr_l;
- reg [12:0] gen_ctr_r;
-
- // This gives 12-bit sound at 44100 Hz. A high sample rate will
+
+ // This gives about 12-bit sound at 44100 Hz. A high sample rate will
// help avoid actually making the sampling frequency audible.
// The low-pass filter on the Lancelot has its knee at 10 kHz, and
// (being a first-order filter) drops off at 3 dB/octave.
// Note: the input is expected unsigned. For signed input, invert
- // bit 11.
-
+ // bit `MSB.
+
+ assign delta_add_l = { 2'b0, data_latch_l } + delta_l;
+ assign sigma_add_l = delta_add_l + sigma_latch_l;
+ assign delta_l[`DBITS] = sigma_latch_l[`DBITS];
+ assign delta_l[`DBITS-1] = sigma_latch_l[`DBITS];
+ assign delta_l[`DBITS-2:0] = 0;
+
+ assign delta_add_r = { 2'b0, data_latch_r } + delta_r;
+ assign sigma_add_r = delta_add_r + sigma_latch_r;
+ assign delta_r[`DBITS] = sigma_latch_r[`DBITS];
+ assign delta_r[`DBITS-1] = sigma_latch_r[`DBITS];
+ assign delta_r[`DBITS-2:0] = 0;
+
always @(posedge clk)
begin
if ( pulse_ctr == 0 )
begin
pulse_ctr <= 4535-1; // 44100 Hz sample rate
- gen_ctr_l <= data_l+256; // Really should be 218, but 256 is
- gen_ctr_r <= data_r+256; // close enough and cheaper to add
+ data_latch_l <= data_l;
+ data_latch_r <= data_r;
end
else
begin
pulse_ctr <= pulse_ctr-1;
- gen_ctr_l <= gen_ctr_l-1;
- gen_ctr_r <= gen_ctr_r-1;
end
+
+ out_latch_l <= sigma_latch_l[`DBITS];
+ sigma_latch_l <= sigma_add_l;
+
+ out_latch_r <= sigma_latch_r[`DBITS];
+ sigma_latch_r <= sigma_add_r;
end
// Definitely *not* a 50% duty cycle; goes high immediately after
// the data item has been latched
assign audio_clk = pulse_ctr[12];
- assign audio_l = ~gen_ctr_l[12];
- assign audio_r = ~gen_ctr_r[12];
-
+ assign audio_l = out_latch_l;
+ assign audio_r = out_latch_r;
endmodule // sound