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// -----------------------------------------------------------------------
//
//   Copyright 2010 H. Peter Anvin - All Rights Reserved
//
//   This program is free software; you can redistribute it and/or modify
//   it under the terms of the GNU General Public License as published by
//   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
//   Bostom MA 02111-1307, USA; either version 2 of the License, or
//   (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------

//
// AT-PS/2 keyboard/mouse interface (single pipe - use two for K+M)
//
// The AT-PS/2 interface is basically absurd.  With two lines they would
// have been much better off just using RS232 communication and getting
// bidirectional communication, but the AT designers decided to use a
// microcontroller for no obvious reason.  Hence this complex state
// machine.
//
// The following registers are implemented (similar to the serial port):
//
// R 0 - data in
// W 0 - data out
// R 1 - status:
//       bit 0 - data available in input FIFO
//       bit 1 - outbound transaction complete
//

module ps2 (
	    input         rst_n, 	// Global reset
	    input         clk,		// System clock (25 MHz)

	    inout	  ps2_clk,	// Clock line
	    inout	  ps2_dat,	// Data line

	    input         msel,		// Unit (card/chip) select, AS#
	    input         cpu_a,	// Address bit
	    input  [7:0]  cpu_do,	// CPU data out (cpu->card)
	    output [7:0]  cpu_di,	// CPU data in  (card->cpu)
	    input         cpu_r_wn,	// R/W#

	    output        irq_n		// Has data (IRQ generation)
	    );

   // Debounced inputs
   wire 	rx_clk;
   wire 	rx_dat;

   debounce #(.width(2), .count(4)) debounce
     (
      .clk	( clk ),
      .in	( { ps2_clk, ps2_dat } ),
      .out	( { rx_clk, rx_dat } ),
      .strobe	( )
      );

   // CPU strobes
   wire         cpu_rd  = msel & cpu_r_wn;
   wire 	cpu_wr  = msel & ~cpu_r_wn;
   wire 	cpu_rdd = cpu_rd & ~cpu_a;
   wire 	cpu_wrd = cpu_wr & ~cpu_a;

   // Edge detect
   reg 		 cpu_wrd_q;
   reg 		 cpu_rdd_q;

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       cpu_wrd_q <= 1'b0;
     else
       cpu_wrd_q <= cpu_wrd;

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       cpu_rdd_q <= 1'b0;
     else
       cpu_rdd_q <= cpu_rdd;

   // Baud rate divider
   // The baud rate should be 10.0-16.7 kHz, so we divide the 25 MHz
   // system clock with 512 to produce a quadrature strobe for a baud
   // rate of 25 MHz/(4*512) ~ 12.2 kHz (20.48 us/strobe)
   reg [8:0] 	baud_rate_ctr;
   reg 		baud_stb;

   always @(posedge clk)
     baud_rate_ctr <= baud_rate_ctr + 1'b1;

   always @(posedge clk)
     baud_stb <= &baud_rate_ctr;

   // Transmit outputs (open drain)
   reg 		tx_clk;
   reg 		tx_dat;

   assign ps2_clk = tx_clk ? 1'bz : 1'b0;
   assign ps2_dat = tx_dat ? 1'bz : 1'b0;

   // Data shift register, bit counters, state
   reg [8:0] 	tx_data;
   reg 		tx_busy;
   reg [9:0] 	rx_data;
   reg [2:0] 	wait_ctr;
   reg [3:0] 	bit_ctr;
   reg [2:0] 	state;
   reg 		rx_write_stb;

   parameter [2:0] st_idle     		= 3'h0;
   parameter [2:0] st_send_clk		= 3'h1;
   parameter [2:0] st_send_start	= 3'h2;
   parameter [2:0] st_send_bit		= 3'h3;
   parameter [2:0] st_send_waitclk	= 3'h4;
   parameter [2:0] st_recv_bit		= 3'h5;
   parameter [2:0] st_recv_waitclk	= 3'h6;

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  tx_clk       <= 1'b1;
	  tx_dat       <= 1'b1;
	  tx_data      <= 9'h1ff;
	  rx_data      <= 10'hxxx;
	  wait_ctr     <= 3'd0;
	  bit_ctr      <= 4'hx;
	  state        <= st_idle;
	  tx_busy      <= 1'b0;
	  rx_write_stb <= 1'b0;
       end
     else
       begin
	  if (cpu_wrd & ~cpu_wrd_q)
	    begin
	       tx_data <= { ~^cpu_do, cpu_do };
	       tx_busy   <= 1'b1;
	    end

	  rx_write_stb <= 1'b0;

	  if (|wait_ctr)
	    wait_ctr <= wait_ctr - baud_stb;
	  else
	    case (state)
	      st_idle:
		begin
		   bit_ctr <= 4'd11;
		   if (tx_busy)
		     begin
			state    <= st_send_clk;
			wait_ctr <= 3'd7;
			tx_clk   <= 1'b0;
		     end
		   else if (~rx_clk)
		     begin
			state   <= st_recv_bit;
		     end
		end // case: st_idle

	      st_send_clk:
		begin
		   tx_dat   <= 1'b0;
		   wait_ctr <= 3'd1;
		   state    <= st_send_start;
		end

	      st_send_start:
		begin
		   tx_clk   <= 1'b1;
		   wait_ctr <= 3'd1;
		   state    <= st_send_bit;
		end

	      st_send_bit:
		begin
		   if (~rx_clk)
		     begin
			tx_dat  <= tx_data[0];
			tx_data <= { 1'b1, tx_data[8:1] };
			bit_ctr <= bit_ctr - 1'b1;
			state   <= st_send_waitclk;
		     end
		end

	      st_send_waitclk:
		begin
		   if (rx_clk)
		     begin
			tx_busy <= |bit_ctr;
			state   <= |bit_ctr ? st_send_bit : st_idle;
		     end
		end

	      st_recv_bit:
		begin
		   if (~rx_clk)
		     begin
			rx_data <= { rx_dat, rx_data[9:1] };
			bit_ctr <= bit_ctr - 1'b1;
			state   <= st_recv_waitclk;
		     end
		end

	      st_recv_waitclk:
		begin
		   if (rx_clk)
		     begin
			rx_write_stb <= ~|bit_ctr;
			state <= |bit_ctr ? st_recv_bit : st_idle;
		     end
		end
	    endcase // case (state)
       end // else: !if(~rst_n)

   // Control register
   wire 	 rx_clear = cpu_wr & cpu_a & cpu_do[0];

   // Status register
   wire 	 rx_empty;
   wire [7:0] 	 rx_cpu_data;
   wire [7:0] 	 status = { 6'b0, tx_busy, ~rx_empty };
   assign 	 cpu_di = cpu_rd ? (cpu_a ? status : rx_cpu_data) : 8'hFF;

   // IRQ output
   reg 		 irq_q;
   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       irq_q <= 1'b0;
     else
       irq_q <= ~rx_empty;

   assign 	 irq_n = ~irq_q;

   //
   // Receive FIFO
   //
   bytefifo ps2rxfifo
     (
      .clock		( clk ),
      .data		( rx_data[7:0] ),
      .wrreq		( rx_write_stb ),
      .sclr		( ~rst_n | rx_clear ),
      .almost_full	( ),
      .empty		( rx_empty ),
      .full		( ),
      .rdreq		( cpu_rdd & ~cpu_rdd_q ),
      .q		( rx_cpu_data ),
      .usedw		( )
      );

endmodule // ps2