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authorH. Peter Anvin <hpa@zytor.com>2011-11-10 03:29:06 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:50 (GMT)
commitf638c86f1920342b053b75ab85034f26e0841625 (patch)
treef165a1a9b06fc68336bf680ebd41cb83fb7e1bec
parentfbd238e0d06d975c04b1f7749bb4b81837287222 (diff)
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display: switch to 640x480 mode (square pixels, 60 Hz)
Switch to standard VGA 640x480 mode with square pixels.
-rw-r--r--display.v26
1 files changed, 14 insertions, 12 deletions
diff --git a/display.v b/display.v
index 18422e8..f221341 100644
--- a/display.v
+++ b/display.v
@@ -27,11 +27,13 @@ module display (
);
//
- // 640x400 70 Hz using a standard VGA monitor in 400 line mode
+ // 640x480 60 Hz using a standard VGA monitor in 480 line mode
//
// 31.78 us horizontal lines, 449 total lines:
// We use a pixel clock of 25 MHz (nominal would be 25.175 MHz); the
- // error is 0.7%.
+ // error is 0.7% -- tolerance is supposed to be 0.5%, but it's close
+ // enough (we could drop 6-8 pixels from the horizontal refresh to
+ // match better if this is an issue.)
//
// Horizontal:
// 16 pixels back porch
@@ -45,10 +47,10 @@ module display (
// for any one line as soon as the horizontal blank
//
// Vertical:
- // 400 lines active
- // 12 lines back porch
+ // 480 lines active
+ // 10 lines back porch
// 2 lines vsync
- // 35 lines front porch
+ // 33 lines front porch
//
parameter hsync_minus = 1'b1; // -hsync
parameter vsync_minus = 1'b0; // +vsync
@@ -58,10 +60,10 @@ module display (
parameter [10:0] h_syncstart = -96-48;
parameter [10:0] h_syncend = -48;
- parameter [8:0] v_active = 9'd400;
- parameter [8:0] v_syncstart = v_active + 12;
- parameter [8:0] v_syncend = v_syncstart + 2;
- parameter [8:0] v_total = v_syncend + 35;
+ parameter [9:0] v_active = 10'd480;
+ parameter [9:0] v_syncstart = v_active + 10;
+ parameter [9:0] v_syncend = v_syncstart + 2;
+ parameter [9:0] v_total = v_syncend + 33;
reg [25:0] ctl_row0start;
reg [25:0] ctl_rowNstart;
@@ -83,9 +85,9 @@ module display (
assign vga_b = b;
assign vga_hs = hsync;
assign vga_vs = vsync;
-
+
reg [10:0] xctr;
- reg [8:0] yctr;
+ reg [9:0] yctr;
reg [1:0] xseq; // Sequencer for per-horizontal-line events
reg [7:0] pixel;
@@ -151,7 +153,7 @@ module display (
5'b00111: cpu_di_out = { 14'b0, ctl_mode };
5'b01000: cpu_di_out = { 7'b0, ctl_dacxor };
5'b01001: cpu_di_out = { {5{xctr[10]}}, xctr };
- 5'b01010: cpu_di_out = { 7'b0, yctr };
+ 5'b01010: cpu_di_out = { 6'b0, yctr };
5'b1xxxx: cpu_di_out = cpu_di_ramdac;
default: cpu_di_out = 16'hxxxx;
endcase