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authorH. Peter Anvin <hpa@zytor.com>2011-11-10 02:58:21 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:50 (GMT)
commitee82ba1459bb3b6729752e38d403053693522806 (patch)
tree3d24aa6929f04a1f11911e65c73a89a493c85923
parent58475d8f4e971cac7bfced09a3d9cfff846502ea (diff)
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Snapshot of moving frame buffer to SDRAM
Move the frame buffer into SDRAM. This is still not quite working correctly.
-rw-r--r--data/sysrom/include/ioreg.h5
-rw-r--r--data/sysrom/start.asm6
-rw-r--r--data/sysrom/sysstart.c15
-rw-r--r--de1/de1.qsf420
-rw-r--r--de1/de1.v37
-rw-r--r--display.v113
-rw-r--r--mega/vdufifo.v185
-rw-r--r--sdram.v118
8 files changed, 783 insertions, 116 deletions
diff --git a/data/sysrom/include/ioreg.h b/data/sysrom/include/ioreg.h
index 9b00834..034843d 100644
--- a/data/sysrom/include/ioreg.h
+++ b/data/sysrom/include/ioreg.h
@@ -57,11 +57,6 @@ static __inline__ void writel(uint32_t __val, volatile uint32_t *__ptr)
#endif
/*
- * Video frame buffer
- */
-#define IO_FRAMEBUF IO_VOID(0xffe00000)
-
-/*
* System control
*/
#define IO_SYS_CTL IO_WORD(0xfff00000)
diff --git a/data/sysrom/start.asm b/data/sysrom/start.asm
index e30c036..2d5152b 100644
--- a/data/sysrom/start.asm
+++ b/data/sysrom/start.asm
@@ -54,9 +54,9 @@ bss_clear_loop:
/* Test RAM by writing patterns and reading back */
move.l #0xdeadbeef, %d1
move.l %d1, (%a0)
- move.l (%a0)+, %d2
- move.l %d2, (%a0)
- move.l (%a0)+, %d2
+ move.l (%a0), %d2
+ eor.l %d1, %d2
+ move.l %d2, (IO_SYS_7SEG)
jmp (sys_start)
diff --git a/data/sysrom/sysstart.c b/data/sysrom/sysstart.c
index 48c5e7e..79fc9e8 100644
--- a/data/sysrom/sysstart.c
+++ b/data/sysrom/sysstart.c
@@ -190,18 +190,21 @@ static void irq_init(void)
cpu_set_spl(0);
}
+uint8_t __framebuf[2*400*640];
+
static void picture(void)
{
volatile uint8_t *ptr, *aptr, *bptr;
unsigned int x, y, i, j;
+ size_t p;
- ptr = IO_FRAMEBUF;
+ ptr = __framebuf;
printf("Initializing frame buffer image @ %p\n", ptr);
for (y = 0; y < 400; y++)
for (x = 0; x < 640; x++)
*ptr++ = x+y;
- ptr = IO_FRAMEBUF;
+ ptr = __framebuf;
printf("Reading back framebuffer image @ %p\n", ptr);
for (y = 0; y < 400; y++) {
for (x = 0; x < 640; x++) {
@@ -215,7 +218,7 @@ static void picture(void)
}
printf("Drawing test frame picture at %p\n", ptr);
- writel(640*400*8, IO_VIDEO_ROW0START);
+ writel(((size_t)__framebuf + 640*400) << 3, IO_VIDEO_ROW0START);
memset((void *)ptr, 0, 256000); /* Clear picture 1 */
for (i = 0; i < 100; i++) {
unsigned int ofs = i*2;
@@ -235,8 +238,10 @@ static void picture(void)
printf("Soft-scrolling the picture...\n");
/* Soft-scroll the new picture in */
- for (i = 0; i <= 640*400*8; i += 640*8) {
- writel(i, IO_VIDEO_ROW0START);
+ p = ((size_t)__framebuf) << 3;
+ for (i = 0; i <= 400; i++) {
+ writel(p, IO_VIDEO_ROW0START);
+ p += (640 << 3);
for (j = 0; j < 10000; j++)
asm volatile("" : : "r" (j));
diff --git a/de1/de1.qsf b/de1/de1.qsf
index 8a6c68c..d00c78e 100644
--- a/de1/de1.qsf
+++ b/de1/de1.qsf
@@ -433,7 +433,7 @@ set_global_assignment -name GENERATE_JAM_FILE ON
# SignalTap II Assignments
# ========================
-set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name ENABLE_SIGNALTAP ON
# LogicLock Region Assignments
# ============================
@@ -533,11 +533,11 @@ set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id clock_27
set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[0]
set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[1]
set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id clock_24
-set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
-set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1]
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
+set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1]
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
@@ -546,7 +546,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name PARALLEL_SYNTHESIS ON
set_global_assignment -name POWER_USE_TA_VALUE 30
-set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
@@ -557,6 +557,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_g
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_r
set_global_assignment -name MISC_FILE de1.dpf
+set_global_assignment -name VERILOG_FILE ../mega/vdufifo.v
set_global_assignment -name VERILOG_FILE ../enc28j60.v
set_global_assignment -name VERILOG_FILE ../debounce.v
set_global_assignment -name VERILOG_FILE ../display.v
@@ -586,4 +587,409 @@ set_global_assignment -name VERILOG_FILE de1.v
set_global_assignment -name SDC_FILE de1.sdc
set_global_assignment -name VERILOG_FILE i2c.v
set_global_assignment -name VERILOG_FILE sound.v
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram:sdram|dram_clk" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to boot_mode -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to boot_mode -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "display:display|vdu_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "display:display|vdu_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "display:display|vdu_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "display:display|vdu_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "display:display|vdu_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "display:display|vdu_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "display:display|vdu_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "display:display|vdu_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "display:display|vdu_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "display:display|vdu_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "display:display|vdu_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "display:display|vdu_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "display:display|vdu_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "display:display|vdu_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "display:display|vdu_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "display:display|vdu_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "display:display|vdu_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "display:display|vdu_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "display:display|vdu_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "display:display|vdu_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "display:display|vdu_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "display:display|vdu_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "display:display|vdu_ack" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "display:display|vdu_cnt[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "display:display|vdu_cnt[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "display:display|vdu_cnt[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "display:display|vdu_cnt[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "display:display|vdu_cnt[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "display:display|vdu_cnt[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "display:display|vdu_cnt[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "display:display|vdu_d[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "display:display|vdu_d[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "display:display|vdu_d[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "display:display|vdu_d[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "display:display|vdu_d[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "display:display|vdu_d[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "display:display|vdu_d[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "display:display|vdu_d[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "display:display|vdu_d[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "display:display|vdu_d[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "display:display|vdu_d[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "display:display|vdu_d[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "display:display|vdu_d[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "display:display|vdu_d[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "display:display|vdu_d[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "display:display|vdu_d[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "display:display|vdu_start" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to dram_a[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to dram_a[10] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to dram_a[11] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to dram_a[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to dram_a[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to dram_a[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to dram_a[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to dram_a[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to dram_a[6] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to dram_a[7] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to dram_a[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to dram_a[9] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to dram_ba[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to dram_ba[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to dram_cas_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to dram_cke -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to dram_cs_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to dram_dq[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to dram_dq[10] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to dram_dq[11] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to dram_dq[12] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to dram_dq[13] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to dram_dq[14] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to dram_dq[15] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to dram_dq[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to dram_dq[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to dram_dq[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to dram_dq[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to dram_dq[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to dram_dq[6] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to dram_dq[7] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to dram_dq[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to dram_dq[9] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to dram_dqm[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to dram_dqm[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to dram_ras_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to dram_we_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to rst_ctr[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "sdram:sdram|cpu_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "sdram:sdram|cpu_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "sdram:sdram|cpu_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "sdram:sdram|cpu_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "sdram:sdram|cpu_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "sdram:sdram|cpu_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "sdram:sdram|cpu_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "sdram:sdram|cpu_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "sdram:sdram|cpu_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "sdram:sdram|cpu_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "sdram:sdram|cpu_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "sdram:sdram|cpu_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "sdram:sdram|cpu_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "sdram:sdram|cpu_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "sdram:sdram|cpu_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "sdram:sdram|cpu_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "sdram:sdram|cpu_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "sdram:sdram|cpu_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "sdram:sdram|cpu_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "sdram:sdram|cpu_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "sdram:sdram|cpu_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "sdram:sdram|cpu_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "sdram:sdram|cpu_wait_f" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "sdram:sdram|sdram_q[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "sdram:sdram|sdram_q[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "sdram:sdram|sdram_q[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "sdram:sdram|sdram_q[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram:sdram|sdram_q[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram:sdram|sdram_q[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram:sdram|sdram_q[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram:sdram|sdram_q[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram:sdram|sdram_q[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram:sdram|sdram_q[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram:sdram|sdram_q[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram:sdram|sdram_q[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram:sdram|sdram_q[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram:sdram|sdram_q[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram:sdram|sdram_q[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram:sdram|sdram_q[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram:sdram|sdram_q_s[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram:sdram|sdram_q_s[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram:sdram|sdram_q_s[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram:sdram|sdram_q_s[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "sdram:sdram|sdram_q_s[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "sdram:sdram|sdram_q_s[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "sdram:sdram|sdram_q_s[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "sdram:sdram|sdram_q_s[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "sdram:sdram|sdram_q_s[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "sdram:sdram|sdram_q_s[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "sdram:sdram|sdram_q_s[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "sdram:sdram|sdram_q_s[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "sdram:sdram|sdram_q_s[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "sdram:sdram|sdram_q_s[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "sdram:sdram|sdram_q_s[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "sdram:sdram|sdram_q_s[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "sdram:sdram|state.st_cpu_act" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "sdram:sdram|state.st_cpu_rd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "sdram:sdram|state.st_cpu_rd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "sdram:sdram|state.st_cpu_rd_pre" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "sdram:sdram|state.st_cpu_wr_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "sdram:sdram|state.st_idle" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "sdram:sdram|state.st_mrs" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "sdram:sdram|state.st_reset" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "sdram:sdram|state.st_rfsh" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "sdram:sdram|state.st_rfsh1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "sdram:sdram|state.st_rfsh2" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "sdram:sdram|state.st_vdu_act" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "sdram:sdram|state.st_vdu_rd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "sdram:sdram|state.st_vdu_rd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "sdram:sdram|vdu_a_ctr[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "sdram:sdram|vdu_a_ctr[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "sdram:sdram|vdu_a_ctr[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "sdram:sdram|vdu_a_ctr[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "sdram:sdram|vdu_a_ctr[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "sdram:sdram|vdu_a_ctr[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "sdram:sdram|vdu_a_ctr[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "sdram:sdram|vdu_a_ctr[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "sdram:sdram|vdu_a_ctr[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "sdram:sdram|vdu_a_ctr[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "sdram:sdram|vdu_a_ctr[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "sdram:sdram|vdu_a_ctr[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "sdram:sdram|vdu_a_ctr[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram:sdram|vdu_a_ctr[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "sdram:sdram|vdu_a_ctr[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "sdram:sdram|vdu_a_ctr[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "sdram:sdram|vdu_a_ctr[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "sdram:sdram|vdu_a_ctr[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "sdram:sdram|vdu_a_ctr[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "sdram:sdram|vdu_a_ctr[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "sdram:sdram|vdu_ctr[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "sdram:sdram|vdu_ctr[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "sdram:sdram|vdu_ctr[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "sdram:sdram|vdu_ctr[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "sdram:sdram|vdu_ctr[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "sdram:sdram|vdu_ctr[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "sdram:sdram|vdu_ctr[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "sdram:sdram|vdu_rdy" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "sdram:sdram|vdu_skip[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "sdram:sdram|vdu_skip[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "display:display|vdu_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "display:display|vdu_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "display:display|vdu_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "display:display|vdu_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "display:display|vdu_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "display:display|vdu_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "display:display|vdu_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "display:display|vdu_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "display:display|vdu_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "display:display|vdu_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "display:display|vdu_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "display:display|vdu_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "display:display|vdu_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "display:display|vdu_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "display:display|vdu_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "display:display|vdu_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "display:display|vdu_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "display:display|vdu_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "display:display|vdu_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "display:display|vdu_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "display:display|vdu_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "display:display|vdu_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "display:display|vdu_ack" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "display:display|vdu_cnt[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "display:display|vdu_cnt[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "display:display|vdu_cnt[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "display:display|vdu_cnt[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "display:display|vdu_cnt[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "display:display|vdu_cnt[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "display:display|vdu_cnt[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "display:display|vdu_d[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "display:display|vdu_d[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "display:display|vdu_d[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "display:display|vdu_d[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "display:display|vdu_d[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "display:display|vdu_d[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "display:display|vdu_d[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "display:display|vdu_d[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "display:display|vdu_d[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "display:display|vdu_d[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "display:display|vdu_d[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "display:display|vdu_d[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "display:display|vdu_d[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "display:display|vdu_d[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "display:display|vdu_d[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "display:display|vdu_d[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "display:display|vdu_start" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to dram_a[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to dram_a[10] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to dram_a[11] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to dram_a[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to dram_a[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to dram_a[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to dram_a[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to dram_a[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to dram_a[6] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to dram_a[7] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to dram_a[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to dram_a[9] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to dram_ba[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to dram_ba[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to dram_cas_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to dram_cke -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to dram_cs_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to dram_dq[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to dram_dq[10] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to dram_dq[11] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to dram_dq[12] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to dram_dq[13] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to dram_dq[14] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to dram_dq[15] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to dram_dq[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to dram_dq[2] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to dram_dq[3] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to dram_dq[4] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to dram_dq[5] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to dram_dq[6] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to dram_dq[7] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to dram_dq[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to dram_dq[9] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to dram_dqm[0] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to dram_dqm[1] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to dram_ras_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to dram_we_n -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to rst_ctr[8] -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram:sdram|cpu_a[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram:sdram|cpu_a[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram:sdram|cpu_a[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram:sdram|cpu_a[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram:sdram|cpu_a[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram:sdram|cpu_a[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram:sdram|cpu_a[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram:sdram|cpu_a[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram:sdram|cpu_a[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram:sdram|cpu_a[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram:sdram|cpu_a[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram:sdram|cpu_a[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram:sdram|cpu_a[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram:sdram|cpu_a[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram:sdram|cpu_a[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram:sdram|cpu_a[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram:sdram|cpu_a[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram:sdram|cpu_a[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram:sdram|cpu_a[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram:sdram|cpu_a[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram:sdram|cpu_a[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram:sdram|cpu_a[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram:sdram|cpu_wait_f" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "sdram:sdram|sdram_q[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "sdram:sdram|sdram_q[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "sdram:sdram|sdram_q[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "sdram:sdram|sdram_q[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram:sdram|sdram_q[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram:sdram|sdram_q[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram:sdram|sdram_q[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram:sdram|sdram_q[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram:sdram|sdram_q[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram:sdram|sdram_q[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram:sdram|sdram_q[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram:sdram|sdram_q[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram:sdram|sdram_q[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram:sdram|sdram_q[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram:sdram|sdram_q[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram:sdram|sdram_q[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram:sdram|sdram_q_s[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram:sdram|sdram_q_s[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram:sdram|sdram_q_s[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram:sdram|sdram_q_s[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "sdram:sdram|sdram_q_s[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "sdram:sdram|sdram_q_s[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "sdram:sdram|sdram_q_s[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "sdram:sdram|sdram_q_s[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "sdram:sdram|sdram_q_s[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "sdram:sdram|sdram_q_s[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "sdram:sdram|sdram_q_s[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "sdram:sdram|sdram_q_s[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "sdram:sdram|sdram_q_s[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "sdram:sdram|sdram_q_s[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "sdram:sdram|sdram_q_s[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "sdram:sdram|sdram_q_s[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "sdram:sdram|state.st_cpu_act" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "sdram:sdram|state.st_cpu_rd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "sdram:sdram|state.st_cpu_rd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "sdram:sdram|state.st_cpu_rd_pre" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "sdram:sdram|state.st_cpu_wr_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "sdram:sdram|state.st_idle" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "sdram:sdram|state.st_mrs" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "sdram:sdram|state.st_reset" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "sdram:sdram|state.st_rfsh" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "sdram:sdram|state.st_rfsh1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "sdram:sdram|state.st_rfsh2" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "sdram:sdram|state.st_vdu_act" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "sdram:sdram|state.st_vdu_rd_cmd" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "sdram:sdram|state.st_vdu_rd_data" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "sdram:sdram|vdu_a_ctr[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "sdram:sdram|vdu_a_ctr[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "sdram:sdram|vdu_a_ctr[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "sdram:sdram|vdu_a_ctr[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "sdram:sdram|vdu_a_ctr[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "sdram:sdram|vdu_a_ctr[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "sdram:sdram|vdu_a_ctr[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "sdram:sdram|vdu_a_ctr[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "sdram:sdram|vdu_a_ctr[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "sdram:sdram|vdu_a_ctr[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "sdram:sdram|vdu_a_ctr[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "sdram:sdram|vdu_a_ctr[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "sdram:sdram|vdu_a_ctr[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram:sdram|vdu_a_ctr[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "sdram:sdram|vdu_a_ctr[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "sdram:sdram|vdu_a_ctr[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "sdram:sdram|vdu_a_ctr[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "sdram:sdram|vdu_a_ctr[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "sdram:sdram|vdu_a_ctr[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "sdram:sdram|vdu_a_ctr[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "sdram:sdram|vdu_ctr[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "sdram:sdram|vdu_ctr[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "sdram:sdram|vdu_ctr[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "sdram:sdram|vdu_ctr[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "sdram:sdram|vdu_ctr[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "sdram:sdram|vdu_ctr[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "sdram:sdram|vdu_ctr[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "sdram:sdram|vdu_rdy" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "sdram:sdram|vdu_skip[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "sdram:sdram|vdu_skip[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "sdram:sdram|vdufifo:vdufifo|wrusedw[3]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=190" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=190" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=593" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=49549" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "sdram:sdram|cpu_wait_s" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram:sdram|cpu_wait_s" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=30828" -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/de1/de1.v b/de1/de1.v
index 2d3b6b3..1cc7012 100644
--- a/de1/de1.v
+++ b/de1/de1.v
@@ -196,8 +196,7 @@ module abc8000_de1 (
wire msel_sdram = ~cpu_as_n & (~boot_mode | ~cpu_r_wn) & ~cpu_a[23];
wire msel_flash = ~cpu_as_n & ((cpu_a[23:22] == 2'b10) |
(boot_mode & cpu_r_wn & ~cpu_a[23]));
- // c00000-dfffff unused/reserved (expansion bus?)
- wire msel_video = ~cpu_as_n & (cpu_a[23:20] == 4'b1110);
+ // c00000-efffff unused/reserved (expansion bus?)
wire [15:0] msel_dev = {16{~cpu_as_n}} & cpu_a_dev;
//
@@ -397,7 +396,7 @@ module abc8000_de1 (
assign fl_ce_n = 1'b0;
assign fl_oe_n = 1'b0;
assign fl_we_n = 1'b1;
- assign fl_a = { cpu_a[21:1], fl_state[1] };
+ assign fl_a = { ~cpu_a[21], cpu_a[20:1], fl_state[1] };
assign fl_dq = 8'hzz;
always @(negedge rst_n or posedge sys_clk)
@@ -435,6 +434,13 @@ module abc8000_de1 (
assign dram_clk = ~sdram_clk; // Opposite phase to the internal clock
+ // Signals to video unit
+ wire vdu_start;
+ wire [22:1] vdu_a;
+ wire [6:0] vdu_cnt;
+ wire [15:0] vdu_d;
+ wire vdu_ack;
+
sdram sdram (
.rst_n ( rst_n ),
.sys_clk ( sys_clk ),
@@ -447,6 +453,12 @@ module abc8000_de1 (
.cpu_r_wn ( cpu_r_wn ),
.cpu_wait_n ( sdram_wait_n ),
+ .vdu_start ( vdu_start ),
+ .vdu_a ( vdu_a ),
+ .vdu_cnt ( vdu_cnt ),
+ .vdu_d ( vdu_d ),
+ .vdu_ack ( vdu_ack ),
+
.dram_clk ( sdram_clk ),
.dram_cke ( dram_cke ),
.dram_cs_n ( dram_cs_n ),
@@ -590,6 +602,13 @@ module abc8000_de1 (
assign gpio_1[25:0] = 26'hzzz_zzzz;
assign gpio_1[35:34] = 2'bzz;
+ // SRAM
+ assign sram_ce_n = 1'b1;
+ assign sram_oe_n = 1'b1;
+ assign sram_we_n = 1'b1;
+ assign sram_be_n = 2'b11;
+ assign sram_a = 18'h3_ffff;
+ assign sram_dq = 16'hffff;
// ------------------------------------------------------------------------
// Display unit
@@ -604,17 +623,15 @@ module abc8000_de1 (
.cpu_do ( cpu_do ),
.cpu_di ( video_cpu_di ),
.cpu_a ( cpu_a[18:1] ),
- .msel_fb ( msel_video ),
.msel_ctl ( msel_dev[2] ),
.cpu_be_n ( cpu_be_n ),
.cpu_r_wn ( cpu_r_wn ),
- .sram_ce_n ( sram_ce_n ),
- .sram_oe_n ( sram_oe_n ),
- .sram_we_n ( sram_we_n ),
- .sram_be_n ( sram_be_n ),
- .sram_a ( sram_a ),
- .sram_dq ( sram_dq ),
+ .vdu_start ( vdu_start ),
+ .vdu_a ( vdu_a ),
+ .vdu_cnt ( vdu_cnt ),
+ .vdu_d ( vdu_d ),
+ .vdu_ack ( vdu_ack ),
.hblank_n ( mfp_gpip_in[7] ),
.vblank_n ( mfp_gpip_in[6] ),
diff --git a/display.v b/display.v
index a85a130..59bf8ab 100644
--- a/display.v
+++ b/display.v
@@ -5,17 +5,16 @@ module display (
input [15:0] cpu_do,
output [15:0] cpu_di,
input [18:1] cpu_a,
- input msel_fb, // Frame buffer memory
input msel_ctl, // Control or RAMDAC
input [1:0] cpu_be_n,
input cpu_r_wn,
- output sram_ce_n, // SRAM CE#
- output sram_oe_n, // SRAM OE#
- output sram_we_n, // SRAM WE#
- output [1:0] sram_be_n, // SRAM UB#, LB#
- output [17:0] sram_a, // SRAM address bus
- inout [15:0] sram_dq, // SRAM data bus
+ // Signals to memory controller
+ output vdu_start, // VDU line start strobe
+ output [22:1] vdu_a, // VDU line address
+ output [6:0] vdu_cnt, // VDU strobe count
+ input [15:0] vdu_d, // VDU data out
+ output vdu_ack, // VDU data strobe
output hblank_n,
output vblank_n,
@@ -64,15 +63,14 @@ module display (
parameter [8:0] v_syncend = v_syncstart + 2;
parameter [8:0] v_total = v_syncend + 35;
- reg [21:0] ctl_row0start;
- reg [21:0] ctl_rowNstart;
- reg [21:0] ctl_rowstride;
+ reg [25:0] ctl_row0start;
+ reg [25:0] ctl_rowNstart;
+ reg [25:0] ctl_rowstride;
reg [8:0] ctl_rowN;
reg [1:0] ctl_mode;
reg [8:0] ctl_dacxor;
- reg [21:0] rowaddr;
- reg [17:0] fbaddr;
+ reg [25:0] rowaddr;
reg [3:0] r;
reg [3:0] g;
@@ -91,11 +89,9 @@ module display (
reg [1:0] xseq; // Sequencer for per-horizontal-line events
reg [7:0] pixel;
- reg [15:0] pixelbuf;
- reg pixelbuf_valid;
reg [15:0] pixeldata;
reg [3:0] pixelcnt;
-
+
wire xblank = xctr[10];
wire yblank = (yctr >= v_active);
wire blank = xblank | yblank;
@@ -120,6 +116,15 @@ module display (
assign hblank_n = ~hblank_q;
assign vblank_n = ~vblank_q;
+ // Handshaking with memory controller
+ reg vdu_ack_q;
+
+ assign vdu_ack = vdu_ack_q;
+ assign vdu_a = rowaddr[25:4];
+ assign vdu_cnt = ( ctl_mode == 2'b00 ) ? 7'd11 :
+ ( ctl_mode == 2'b01 ) ? 7'd21 :
+ ( ctl_mode == 2'b10 ) ? 7'd41 : 7'd81;
+
//
// Control register read/write
//
@@ -139,11 +144,11 @@ module display (
always @(*)
casex ( { cpu_a[15], cpu_a[4:1] } )
- 5'b00000: cpu_di_out = { 10'b0, ctl_row0start[21:16] };
+ 5'b00000: cpu_di_out = { 6'b0, ctl_row0start[25:16] };
5'b00001: cpu_di_out = ctl_row0start[15:0];
- 5'b00010: cpu_di_out = { 10'b0, ctl_rowNstart[21:16] };
+ 5'b00010: cpu_di_out = { 6'b0, ctl_rowNstart[25:16] };
5'b00011: cpu_di_out = ctl_rowNstart[15:0];
- 5'b00100: cpu_di_out = { 10'b0, ctl_rowstride[21:16] };
+ 5'b00100: cpu_di_out = { 6'b0, ctl_rowstride[25:16] };
5'b00101: cpu_di_out = ctl_rowstride[15:0];
5'b00110: cpu_di_out = { 7'b0, ctl_rowN };
5'b00111: cpu_di_out = { 14'b0, ctl_mode };
@@ -154,6 +159,8 @@ module display (
default: cpu_di_out = 16'hxxxx;
endcase
+ assign cpu_di = (msel_ctl & cpu_r_wn) ? cpu_di_out : 16'hffff;
+
always @(negedge rst_n or posedge clk)
if (~rst_n)
begin
@@ -169,7 +176,7 @@ module display (
case ( cpu_a[4:1] )
4'b0000:
begin
- if ( ~cpu_be_n[0] ) ctl_row0start[21:16] <= cpu_do[5:0];
+ if ( ~cpu_be_n[0] ) ctl_row0start[25:16] <= cpu_do[9:0];
end
4'b0001:
begin
@@ -178,7 +185,7 @@ module display (
end
4'b0010:
begin
- if ( ~cpu_be_n[0] ) ctl_rowNstart[21:16] <= cpu_do[5:0];
+ if ( ~cpu_be_n[0] ) ctl_rowNstart[25:16] <= cpu_do[9:0];
end
4'b0011:
begin
@@ -187,7 +194,7 @@ module display (
end
4'b0100:
begin
- if ( ~cpu_be_n[0] ) ctl_rowstride[21:16] <= cpu_do[5:0];
+ if ( ~cpu_be_n[0] ) ctl_rowstride[25:16] <= cpu_do[9:0];
end
4'b0101:
begin
@@ -211,46 +218,11 @@ module display (
endcase // case ( cpu_a[4:1] )
//
- // Frame buffer memory
- //
- reg cpu_done;
-
- reg [15:0] cpu_di_fb;
- wire cpu_rdreq = msel_fb & cpu_r_wn & ~cpu_done;
- // 68000 sends byte enables late in a write cycle, so hold the request
- // until they are available
- wire cpu_wrreq = msel_fb & ~cpu_r_wn & ~(&cpu_be_n) & ~cpu_done;
- wire cpu_req = cpu_rdreq | cpu_wrreq;
-
- assign sram_a = cpu_req ? cpu_a[18:1] : fbaddr;
- assign sram_dq = cpu_wrreq ? cpu_do : 16'hzzzz;
- assign sram_ce_n = 1'b0;
- assign sram_we_n = ~cpu_wrreq | ~clk;
- assign sram_oe_n = cpu_wrreq;
- assign sram_be_n = cpu_wrreq ? cpu_be_n : 2'b00;
-
- always @(negedge rst_n or posedge clk)
- if (~rst_n)
- begin
- cpu_done <= 1'b0;
- end
- else
- begin
- cpu_done <= (cpu_done | cpu_req) & msel_fb;
- if (cpu_rdreq)
- cpu_di_fb <= sram_dq;
- end
-
- assign cpu_di = msel_fb ? cpu_di_fb :
- msel_ctl ? cpu_di_out :
- 16'hffff;
-
- //
// Video generation
//
// The address of the next row
- reg [21:0] nextaddr;
+ reg [25:0] nextaddr;
always @(*)
if ( yctr == ctl_rowN )
@@ -273,9 +245,6 @@ module display (
5'b011_11: advance = (xctr[3:0] > { 3'b111, ~rowaddr[3] });
endcase // casex( { yblank, xblank, &xctr[9:4], ctl_mode } )
- // Are we adding bits from the framebuffer?
- wire bitfill = ~cpu_req & (~pixelbuf_valid | (advance & ~|pixelcnt));
-
always @(negedge rst_n or posedge clk)
if (~rst_n)
begin
@@ -285,9 +254,9 @@ module display (
rowaddr <= 22'hxxxxxx;
pixeldata <= 16'hxxxx;
- pixelbuf <= 16'hxxxx;
- pixelbuf_valid <= 1'b0;
pixelcnt <= 4'd0;
+
+ vdu_ack_q <= 1'b0;
end // if (~rst_n)
else
begin
@@ -295,8 +264,8 @@ module display (
begin
if ( ~|pixelcnt )
begin
- pixeldata <= pixelbuf;
- pixelbuf_valid <= 1'b0;
+ pixeldata <= vdu_d;
+ vdu_ack_q <= 1'b1;
case (ctl_mode)
2'b00: pixelcnt <= 4'd15;
2'b01: pixelcnt <= 4'd7;
@@ -316,13 +285,6 @@ module display (
end // else: !if( pixelcnt == 3'd0 )
end // if ( advance )
- if ( bitfill )
- begin
- pixelbuf <= sram_dq;
- pixelbuf_valid <= 1'b1;
- fbaddr <= fbaddr + 1;
- end
-
xseq[1] <= xseq[0];
if ( xctr == h_active-1 )
begin
@@ -341,17 +303,12 @@ module display (
if ( xseq[0] )
begin
rowaddr <= nextaddr;
- fbaddr <= nextaddr[21:4];
- pixelbuf_valid <= 1'b1; // Suppress advance
- end
-
- if ( xseq[1] )
- begin
- pixelbuf_valid <= 1'b0;
pixelcnt <= 4'd0;
end
end // else: !if(~rst_n)
+ assign vdu_start = xseq[1];
+
// Pixel data selector - would be so much easier in littleendian, sigh
always @(*)
case (ctl_mode)
diff --git a/mega/vdufifo.v b/mega/vdufifo.v
new file mode 100644
index 0000000..d1a29f5
--- /dev/null
+++ b/mega/vdufifo.v
@@ -0,0 +1,185 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: vdufifo.v
+// Megafunction Name(s):
+// dcfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 11.0 Build 157 04/27/2011 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2011 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module vdufifo (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ wrfull,
+ wrusedw);
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output wrfull;
+ output [3:0] wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire sub_wire0;
+ wire [15:0] sub_wire1;
+ wire sub_wire2;
+ wire [3:0] sub_wire3;
+ wire wrfull = sub_wire0;
+ wire [15:0] q = sub_wire1[15:0];
+ wire rdempty = sub_wire2;
+ wire [3:0] wrusedw = sub_wire3[3:0];
+
+ dcfifo dcfifo_component (
+ .rdclk (rdclk),
+ .wrclk (wrclk),
+ .wrreq (wrreq),
+ .aclr (aclr),
+ .data (data),
+ .rdreq (rdreq),
+ .wrfull (sub_wire0),
+ .q (sub_wire1),
+ .rdempty (sub_wire2),
+ .wrusedw (sub_wire3),
+ .rdfull (),
+ .rdusedw (),
+ .wrempty ());
+ defparam
+ dcfifo_component.intended_device_family = "Cyclone II",
+ dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
+ dcfifo_component.lpm_numwords = 16,
+ dcfifo_component.lpm_showahead = "OFF",
+ dcfifo_component.lpm_type = "dcfifo",
+ dcfifo_component.lpm_width = 16,
+ dcfifo_component.lpm_widthu = 4,
+ dcfifo_component.overflow_checking = "ON",
+ dcfifo_component.rdsync_delaypipe = 5,
+ dcfifo_component.underflow_checking = "ON",
+ dcfifo_component.use_eab = "ON",
+ dcfifo_component.write_aclr_synch = "ON",
+ dcfifo_component.wrsync_delaypipe = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "16"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "16"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL vdufifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/sdram.v b/sdram.v
index 87d57c1..2e15358 100644
--- a/sdram.v
+++ b/sdram.v
@@ -1,6 +1,6 @@
// -----------------------------------------------------------------------
//
-// Copyright 2010 H. Peter Anvin - All Rights Reserved
+// Copyright 2010-2011 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -30,6 +30,13 @@ module sdram (
input cpu_r_wn,
output cpu_wait_n,
+ // Video unit interface
+ input vdu_start, // VDU line start strobe
+ input [22:1] vdu_a, // VDU line address
+ input [6:0] vdu_cnt, // VDU strobe count
+ output [15:0] vdu_d, // VDU data out
+ input vdu_ack, // VDU data strobe
+
// SDRAM hardware interface
input dram_clk, // SDRAM clock (125 MHz)
output dram_cke, // SDRAM clock enable
@@ -74,6 +81,54 @@ module sdram (
assign dram_dq = sdram_d_en ? sdram_d : 16'hzzzz;
//
+ // VDU line FIFO
+ //
+ reg vdu_rdy; // dram_dq contains data for VDU
+ wire [3:0] vdu_used;
+
+ reg [6:0] vdu_ctr;
+ reg [1:0] vdu_skip;
+
+ reg [22:3] vdu_a_ctr;
+
+ reg [15:0] sdram_vdu_q;
+
+ // ~vdu_used gives the number of free slots in the FIFO. Because
+ // of delays in the reporting of the output count, we need to have space
+ // for two bursts: one that is started before we notice we are almost
+ // full, and one to deal with fractionals.
+ wire vdu_go = ~vdu_start & ~&vdu_used[3] & |vdu_ctr;
+
+ vdufifo vdufifo (
+ .aclr ( ~rst_n | vdu_start ),
+ .data ( sdram_vdu_q ),
+ .rdclk ( sys_clk ),
+ .rdreq ( vdu_ack ),
+ .wrclk ( dram_clk ),
+ .wrreq ( vdu_rdy & ~|vdu_skip ),
+ .q ( vdu_d ),
+ .rdempty ( ),
+ .wrfull ( ),
+ .wrusedw ( vdu_used )
+ );
+
+ // Data strobe skip counter
+ always @(negedge rst_n or posedge dram_clk)
+ if (~rst_n)
+ vdu_skip <= 2'd0;
+ else
+ begin
+ if (vdu_start)
+ vdu_skip <= vdu_a[2:1];
+ else if (vdu_rdy & |vdu_skip)
+ vdu_skip <= vdu_skip - 1'b1;
+ end
+
+ // Data input latch
+ always @(posedge dram_clk)
+ sdram_vdu_q <= dram_dq;
+
+ //
// CPU request signals and private copies of input data
//
// Note: the timing of the 68000 bus for write requests is really
@@ -92,13 +147,14 @@ module sdram (
reg cpu_done;
reg cpu_wait_f; // CPU wait in the SDRAM clock domain
+ reg cpu_wait_s; // CPU wait in the sys_clk clock domain
reg [15:0] sdram_q_s; // Output data in the sys_clk domain
reg [15:0] cpu_do_q; // Private latched copy of cpu_do
reg [1:0] cpu_be_q; // Private copy of cpu_be_n
- assign cpu_wait_n = ~cpu_wait_f;
+ assign cpu_wait_n = ~cpu_wait_s;
assign cpu_di = sdram_q_s;
always @(negedge rst_n or posedge sys_clk)
@@ -106,11 +162,13 @@ module sdram (
begin
sdram_q_s <= 16'hFFFF;
cpu_req_s <= 2'b00;
+ cpu_wait_s <= 1'b0;
end
else
begin
sdram_q_s <= cpu_rdreq ? sdram_q : 16'hFFFF;
cpu_req_s <= { cpu_req_s[0], cpu_req };
+ cpu_wait_s <= cpu_wait_f;
end
always @(negedge rst_n or posedge sys_clk)
@@ -139,17 +197,20 @@ module sdram (
else
rfsh_ctr <= rfsh_ctr + 1;
- parameter st_reset = 4'hC;
- parameter st_rfsh1 = 4'hD; // 1st refresh during initialization
- parameter st_rfsh2 = 4'hE; // 2st refresh during initialization
- parameter st_mrs = 4'hF;
- parameter st_idle = 4'h0;
+ parameter st_reset = 4'hC;
+ parameter st_rfsh1 = 4'hD; // 1st refresh during initialization
+ parameter st_rfsh2 = 4'hE; // 2st refresh during initialization
+ parameter st_mrs = 4'hF;
+ parameter st_idle = 4'h0;
parameter st_cpu_act = 4'h1;
parameter st_cpu_rd_cmd = 4'h2;
parameter st_cpu_rd_pre = 4'h3;
parameter st_cpu_rd_data = 4'h4;
parameter st_cpu_wr_cmd = 4'h6;
- parameter st_rfsh = 4'h8;
+ parameter st_rfsh = 4'h7;
+ parameter st_vdu_act = 4'h8;
+ parameter st_vdu_rd_cmd = 4'h9;
+ parameter st_vdu_rd_data = 4'hA;
//
// Careful with the timing here... there is one cycle between
@@ -170,6 +231,9 @@ module sdram (
state <= st_reset;
cpu_wait_f <= 1'b0;
cpu_done <= 1'b1;
+ vdu_rdy <= 1'b0;
+ vdu_a_ctr <= 20'hx_xxxx;
+ vdu_ctr <= 5'd0;
end
else
begin
@@ -186,6 +250,12 @@ module sdram (
cpu_wait_f <= cpu_wait_f | (cpu_done &
(cpu_rdreq | (cpu_wrreq & (&cpu_req_s))));
+ if (vdu_start)
+ begin
+ vdu_a_ctr <= vdu_a[22:3];
+ vdu_ctr <= vdu_cnt;
+ end
+
if (|nop_ctr)
begin
sdram_cmd <= cmd_nop;
@@ -193,6 +263,8 @@ module sdram (
end
else
begin
+ vdu_rdy <= 1'b0;
+
case (state)
st_reset:
begin
@@ -238,6 +310,8 @@ module sdram (
state <= st_rfsh; // High priority refresh
else if (cpu_wait_f)
state <= st_cpu_act;
+ else if (vdu_go & ~cpu_req)
+ state <= st_vdu_act;
else if (rfsh_ctr[9] & ~cpu_req)
state <= st_rfsh; // Low priority refresh
end
@@ -303,6 +377,34 @@ module sdram (
sdram_d_en <= 1'b1;
state <= st_idle;
nop_ctr <= 4'd4;
+ end // case: st_cpu_wr_cmd
+ st_vdu_act:
+ begin
+ sdram_cmd <= cmd_act;
+ sdram_a <= vdu_a_ctr[22:11];
+ sdram_ba <= vdu_a_ctr[10:9];
+ state <= st_vdu_rd_cmd;
+ nop_ctr <= 4'd2; // tRCD = 3 cycles
+ end
+ st_vdu_rd_cmd:
+ begin
+ sdram_cmd <= cmd_rd;
+ sdram_a[7:0] <= { vdu_a_ctr[8:3], 2'b00 };
+ sdram_a[10] <= 1'b1; // Auto precharge
+ sdram_ba <= vdu_a_ctr[10:9];
+ nop_ctr <= 4'd4; // == CAS latency + 1
+ state <= st_vdu_rd_data;
+ vdu_a_ctr <= vdu_a_ctr + 1'b1;
+ vdu_ctr <= vdu_ctr - 1'b1;
+ end
+ st_vdu_rd_data:
+ begin
+ // Note: with one DESL from the idle state,
+ // tRC (8) and tRP (3) are both satisfied
+ sdram_cmd <= cmd_nop;
+ vdu_rdy <= 1'b1;
+ nop_ctr <= 4'd3; // Burst length - 1
+ state <= st_idle;
end
endcase // case(state)
end // else: !if(|nop_ctr)