summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2010-11-25 03:06:10 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:50 (GMT)
commitde959f272f6ff6a14ca0270478425d6b21831b58 (patch)
tree5edabd90e77a0fb16798e2d7bb33c845608d2e48
parent214f18df9941d93b8b4b3c9292d91cc016f6a8f1 (diff)
downloadabc8000-de959f272f6ff6a14ca0270478425d6b21831b58.zip
abc8000-de959f272f6ff6a14ca0270478425d6b21831b58.tar.gz
abc8000-de959f272f6ff6a14ca0270478425d6b21831b58.tar.bz2
abc8000-de959f272f6ff6a14ca0270478425d6b21831b58.tar.xz
sdram: enable read bursts, use PRE commands to interrupt
Enable burst for read only in the MRS (currently length 4); use a PRE command to immediately interrupt it. This is in preparation for using the SDRAM as a frame buffer.
-rw-r--r--sdram.v22
1 files changed, 16 insertions, 6 deletions
diff --git a/sdram.v b/sdram.v
index 5ba0f14..87d57c1 100644
--- a/sdram.v
+++ b/sdram.v
@@ -146,8 +146,9 @@ module sdram (
parameter st_idle = 4'h0;
parameter st_cpu_act = 4'h1;
parameter st_cpu_rd_cmd = 4'h2;
- parameter st_cpu_wr_cmd = 4'h3;
+ parameter st_cpu_rd_pre = 4'h3;
parameter st_cpu_rd_data = 4'h4;
+ parameter st_cpu_wr_cmd = 4'h6;
parameter st_rfsh = 4'h8;
//
@@ -221,7 +222,9 @@ module sdram (
st_mrs:
begin
sdram_cmd <= cmd_mrs;
- sdram_a <= 12'b0000_0011_0000; // CAS=3, burst 1
+ // Writes are single location
+ // CAS=3, burst 4, sequential
+ sdram_a <= 12'b0010_0011_0010;
sdram_ba <= 2'b00;
state <= st_idle;
nop_ctr <= 4'd2;
@@ -263,12 +266,19 @@ module sdram (
begin
sdram_cmd <= cmd_rd;
sdram_a[7:0] <= cpu_a[8:1];
- sdram_a[10] <= 1'b1; // Auto precharge
+ sdram_ba <= cpu_a[10:9];
+ state <= st_cpu_rd_pre;
+ end
+ st_cpu_rd_pre:
+ begin
+ // The PRE command issued in the cycle immediately
+ // after the read will terminate the burst after
+ // exactly one data strobe. Note that the nop_ctr
+ // below is the CL, not CL-1, due to bus turnaround.
+ sdram_cmd <= cmd_pre;
sdram_ba <= cpu_a[10:9];
state <= st_cpu_rd_data;
- // CAS latency is 3 cycles, plus one cycle for the
- // bus and clock turnaround.
- nop_ctr <= 4'd4;
+ nop_ctr <= 4'd3; // == CAS latency
end
st_cpu_rd_data:
begin