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authorH. Peter Anvin <hpa@zytor.com>2011-06-15 05:10:03 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:50 (GMT)
commitc6ec187f2fe73b17144be0031c648fc571882d55 (patch)
tree178f8ec928f1e15a9f879132e8d4b48055ccee12
parent6c669fe9007513e7d58ba72e0f2890b523aaf399 (diff)
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de1.qsf: add enc28j60.v, update Quartus
Update to Quartus version 11 Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--de1/de1.qsf99
1 files changed, 50 insertions, 49 deletions
diff --git a/de1/de1.qsf b/de1/de1.qsf
index 2bf630d..8a6c68c 100644
--- a/de1/de1.qsf
+++ b/de1/de1.qsf
@@ -31,13 +31,13 @@
# Project-Wide Assignments
# ========================
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
-
-# Pin & Location Assignments
-# ==========================
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.0
+
+# Pin & Location Assignments
+# ==========================
set_location_assignment PIN_A13 -to gpio_0[0]
set_location_assignment PIN_B13 -to gpio_0[1]
set_location_assignment PIN_A14 -to gpio_0[2]
@@ -321,16 +321,16 @@ set_location_assignment PIN_V20 -to sd_clk
set_location_assignment PIN_Y20 -to sd_cmd
set_location_assignment PIN_W20 -to sd_dat0
set_location_assignment PIN_U20 -to sd_dat3
-
-# Timing Assignments
-# ==================
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+
+# Timing Assignments
+# ==================
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
@@ -351,10 +351,10 @@ set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name INC_PLC_MODE OFF
-set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name INC_PLC_MODE OFF
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
@@ -362,27 +362,27 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
# ===========================
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
-set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
-set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
+
+# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
-set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
-set_global_assignment -name GENERATE_HEX_FILE ON
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name GENERATE_HEX_FILE ON
+set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
# Design Assistant Assignments
# ============================
@@ -437,10 +437,10 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# ------------------
-# start CLOCK(clkin)
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# ------------------
+# start CLOCK(clkin)
# Timing Assignments
# ==================
@@ -520,13 +520,13 @@ set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timi
# -----------------
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
-set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clock_50
set_instance_assignment -name CLOCK_SETTINGS clock_50 -to clock_50
set_global_assignment -name FMAX_REQUIREMENT "27 MHz" -section_id clock_27
@@ -557,6 +557,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_g
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_r
set_global_assignment -name MISC_FILE de1.dpf
+set_global_assignment -name VERILOG_FILE ../enc28j60.v
set_global_assignment -name VERILOG_FILE ../debounce.v
set_global_assignment -name VERILOG_FILE ../display.v
set_global_assignment -name VERILOG_FILE ../ps2.v