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authorH. Peter Anvin <hpa@zytor.com>2011-11-10 06:07:38 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:51 (GMT)
commit7c8deb987b2f9b3302162037d296ba4660b26903 (patch)
treed512dcffd903503232641e536111ddbcf88981f3
parent108ebe9b94aa581a62aba3d1b2fe4916016fa81e (diff)
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display: be smarter about initial shifting
Use the pixelcnt counter for shifting into place initially.
-rw-r--r--display.v29
1 files changed, 12 insertions, 17 deletions
diff --git a/display.v b/display.v
index f221341..e68d6cb 100644
--- a/display.v
+++ b/display.v
@@ -53,7 +53,7 @@ module display (
// 33 lines front porch
//
parameter hsync_minus = 1'b1; // -hsync
- parameter vsync_minus = 1'b0; // +vsync
+ parameter vsync_minus = 1'b1; // -vsync
parameter [10:0] h_active = 11'd640;
parameter [10:0] h_ctrstart = -16-96-48;
@@ -232,17 +232,8 @@ module display (
nextaddr = rowaddr + ctl_rowstride;
// Should we advance the pixel shift register?
- reg advance;
- always @(*)
- casex ( { yblank, xblank, &xctr[9:4], ctl_mode } )
- 5'b1xx_xx: advance = 1'b0;
- 5'b00x_xx: advance = 1'b1;
- 5'b010_xx: advance = 1'b0;
- 5'b011_00: advance = (xctr[3:0] > ~rowaddr[3:0]);
- 5'b011_01: advance = (xctr[3:0] > { 1'b1, ~rowaddr[3:1] });
- 5'b011_10: advance = (xctr[3:0] > { 2'b11, ~rowaddr[3:2] });
- 5'b011_11: advance = (xctr[3:0] > { 3'b111, ~rowaddr[3] });
- endcase // casex( { yblank, xblank, &xctr[9:4], ctl_mode } )
+ // We start the shifter 15 pixels before the end of the xblank.
+ wire advance = ~yblank & (~xblank | (&xctr[9:4] & |xctr[3:0]));
// This signal is true when consuming data from vdu_d
assign vdu_ack = advance & ~|pixelcnt;
@@ -289,20 +280,25 @@ module display (
begin
xctr <= h_ctrstart;
xseq[0] <= 1'b1;
- yctr <= yctr + 1;
+ yctr <= yctr + 1'b1;
if ( yctr >= v_total )
yctr <= 9'd0;
end
else
begin
- xctr <= xctr + 1;
+ xctr <= xctr + 1'b1;
xseq[0] <= 1'b0;
end // else: !if( xctr == h_active-1 )
if ( xseq[0] )
begin
rowaddr <= nextaddr;
- pixelcnt <= 4'd0;
+ case (ctl_mode)
+ 2'b00: pixelcnt <= { ~nextaddr[3:0] };
+ 2'b01: pixelcnt <= { 1'b1, ~nextaddr[3:1] };
+ 2'b10: pixelcnt <= { 2'b11, ~nextaddr[3:2] };
+ 2'b11: pixelcnt <= { 3'b111, ~nextaddr[3] };
+ endcase // case(ctl_mode)
end
end // else: !if(~rst_n)
@@ -349,8 +345,7 @@ module display (
end
else
begin
- // Two cycles delay: one for the setting of pixeldata, and
- // one cycle for the RAMDAC memory
+ // 2 cycles delay to catch up with the pipeline
blank_q <= { blank_q[0], blank };
hsync <= ((xctr >= h_syncstart) & (xctr < h_syncend)) ^ hsync_minus;