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authorH. Peter Anvin <hpa@zytor.com>2011-11-10 19:14:14 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2014-02-11 02:07:51 (GMT)
commit34b8942737fed05ce891934720b3ce8403d2ea46 (patch)
tree7bf781a8a0b0aa3bb1a08455d8bb6bbfac9e2e0e
parente76aee326f79b469e7b13166ed5468da355d99e2 (diff)
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display: simplify logic by making advance a register
Simplify the combinatorial logic by making advance a register instead of a high-fanin/high-fanout combinatorial node.
-rw-r--r--display.v10
1 files changed, 8 insertions, 2 deletions
diff --git a/display.v b/display.v
index e68d6cb..9338e83 100644
--- a/display.v
+++ b/display.v
@@ -232,8 +232,7 @@ module display (
nextaddr = rowaddr + ctl_rowstride;
// Should we advance the pixel shift register?
- // We start the shifter 15 pixels before the end of the xblank.
- wire advance = ~yblank & (~xblank | (&xctr[9:4] & |xctr[3:0]));
+ reg advance;
// This signal is true when consuming data from vdu_d
assign vdu_ack = advance & ~|pixelcnt;
@@ -248,6 +247,8 @@ module display (
rowaddr <= 22'hxxxxxx;
pixeldata <= 16'hxxxx;
pixelcnt <= 4'd0;
+
+ advance <= 1'b0;
end // if (~rst_n)
else
begin
@@ -278,6 +279,7 @@ module display (
xseq[1] <= xseq[0];
if ( xctr == h_active-1 )
begin
+ advance <= 1'b0;
xctr <= h_ctrstart;
xseq[0] <= 1'b1;
yctr <= yctr + 1'b1;
@@ -286,6 +288,10 @@ module display (
end
else
begin
+ // We start advancing 15 pixels before unblank; combined
+ // with the setting of pixelcnt below this ensures that we
+ // have the right data shifted and ready at the proper time.
+ advance <= advance | (~yblank & &xctr[9:4]);
xctr <= xctr + 1'b1;
xseq[0] <= 1'b0;
end // else: !if( xctr == h_active-1 )