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// -----------------------------------------------------------------------
//   
//   Copyright 2011 H. Peter Anvin - All Rights Reserved
//
//   Permission is hereby granted, free of charge, to any person
//   obtaining a copy of this software and associated documentation
//   files (the "Software"), to deal in the Software without
//   restriction, including without limitation the rights to use,
//   copy, modify, merge, publish, distribute, sublicense, and/or
//   sell copies of the Software, and to permit persons to whom
//   the Software is furnished to do so, subject to the following
//   conditions:
//   
//   The above copyright notice and this permission notice shall
//   be included in all copies or substantial portions of the Software.
//   
//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
//   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
//   OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
//   NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
//   HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
//   WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
//   FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
//   OTHER DEALINGS IN THE SOFTWARE.
//
// -----------------------------------------------------------------------

//
// enc28j60.v
//
// Driver for the Microchip ENC28J60 SPI Ethernet controller
//

module enc28j60 (
	       input         rst_n,	// Global reset
	       input         clk,	// CPU clk (25 MHz)

	       output        eth_cs_n,	// SPI CS#
	       output        eth_mosi,	// SPI MOSI (SI)
	       output        eth_sck,	// SPI SCLK
	       input         eth_miso,	// SPI MISO (SO)

	       input   [7:0] cpu_do,	// CPU data out (CPU->controller)
	       output  [7:0] cpu_di,	// CPU data in (controller->CPU)
	       input         msel,	// Select
	       input   [1:0] cpu_a,	// Address bits
	       input         cpu_r_wn,	// R/W#
	       output        cpu_wait_n
	       );

   // ------------------------------------------------------------------------
   //
   //  ENC28J60 supports up to 20 MHz on the SPI bus, but we run it at
   //  CPU clk / 2 (12.5 MHz).  However, all fixed timings are such that
   //  running this module up to 40 MHz for a 20 MHz output should work.
   //
   //  The CPU interface is a byte-oriented peripheral.
   //  The actual connection to the 68000 bus shifts the addresses left
   //  by one.
   //
   //  00	- read input shift register (ignored on write)
   //  01	- start bus transaction, leave CS# asserted
   //  10	- start bus transaction, then deassert CS# (1 cycle hold)
   //  11	- start bus transaction, then deassert CS# (9 cycles hold)
   // ------------------------------------------------------------------------

   reg [7:0] 		     spi_shr_out;
   reg [7:0] 		     spi_shr_in;
   reg [3:0] 		     spi_ctr; 		// Bit or cycle counter

   reg 			     spi_cs_n;
   reg 			     spi_clk;
   
   reg 			     spi_active;
   reg 			     spi_cmd_ok;
   reg [1:0]		     spi_finish;

   assign 		     eth_cs_n = spi_cs_n;
   assign 		     eth_sck  = spi_clk;
   assign 		     eth_mosi = spi_shr_out[7];
   
   assign 		     cpu_wait_n = ~(msel & ~spi_cmd_ok);

   reg [1:0] 		     spi_state;
   parameter 		     st_idle    = 2'b00;
   parameter 		     st_data    = 2'b01;
   parameter 		     st_cshold0 = 2'b10;
   parameter 		     st_cshold1 = 2'b11;
   
   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  spi_state   <= st_idle;
	  spi_cs_n    <= 1'b1;
	  spi_clk     <= 1'b0;
	  spi_shr_out <= 8'hff;
	  spi_shr_in  <= 8'hxx;
	  spi_ctr     <= 4'd0;
	  spi_finish  <= 1'bx;
	  spi_cmd_ok  <= 1'b0;
       end
     else
       begin
	  spi_cmd_ok  <= spi_cmd_ok & msel;
	  
	  case (spi_state)
	    st_idle:
	      begin
		 spi_cmd_ok  <= 1'b1;

		 if (msel & |cpu_a)
		   begin
		      spi_cs_n    <= 1'b0;
		      spi_state   <= st_data;
		      spi_shr_out <= cpu_r_wn ? 8'hff : cpu_do;
		      spi_ctr     <= 4'd7;
		      spi_finish  <= cpu_a;
		   end
	      end // case: spi_idle

	    st_data:
	      begin
		 spi_cs_n      <= 1'b0;
		 spi_clk       <= ~spi_clk;
		 
		 if (spi_clk)
		   begin
		      spi_shr_out <= { spi_shr_out[6:0], 1'b1 };
		      spi_ctr     <= spi_ctr - 1'b1;
		      
		      if (~|spi_ctr)
			begin
			   if (spi_finish[1])
			     begin
				spi_ctr   <= { spi_finish[0], 3'b000 };
				spi_state <= st_cshold0;
			     end
			   else if (msel & |cpu_a)
			     begin
				spi_shr_out <= cpu_r_wn ? 8'hff : cpu_do;
				spi_ctr     <= 4'd7;
				spi_finish  <= cpu_a;
				spi_cmd_ok  <= 1'b1;
			     end
			   else
			     begin
				spi_state   <= st_idle;
				spi_cmd_ok  <= 1'b1;
			     end
			end // if (~|spi_ctr)
		   end // if (spi_clk)
		 else
		   begin
		      spi_shr_in <= { spi_shr_in[6:0], eth_miso };
		   end // else: !if(spi_clk)
	      end // case: spi_data

	    st_cshold0:
	      begin
		 spi_ctr        <= spi_ctr - 1'b1;

		 if (~|spi_ctr)
		   begin
		      spi_cs_n  <= 1'b1;
		      spi_state <= st_cshold1;
		   end
	      end
	    
	    st_cshold1:
		begin
		   spi_state    <= st_idle;
		   spi_cmd_ok   <= 1'b1;
		end

	    endcase
	  end // else: !if(~rst_n)

   //
   // Output data
   //
   assign cpu_di = (msel & cpu_r_wn) ? spi_shr_in : 8'hff;

endmodule // enc28j60