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module display (
		input         rst_n,
		input         clk,

		input  [15:0] cpu_do,
		output [15:0] cpu_di,
		input  [18:1] cpu_a,
		input         msel_ctl, 	// Control or RAMDAC
		input  [1:0]  cpu_be_n,
		input         cpu_r_wn,

		// Signals to memory controller
		output        vdu_start,  // VDU line start strobe
		output [22:1] vdu_a,      // VDU line address
		output  [6:0] vdu_cnt,    // VDU strobe count
		input  [15:0] vdu_d,      // VDU data out
		output        vdu_ack,    // VDU data strobe

		output	      hblank_n,
		output        vblank_n,

		output  [3:0] vga_r,
		output  [3:0] vga_g,
		output  [3:0] vga_b,
		output        vga_hs,
		output        vga_vs
		);

   //
   // 640x480 60 Hz using a standard VGA monitor in 480 line mode
   //
   // 31.78 us horizontal lines, 449 total lines:
   // We use a pixel clock of 25 MHz (nominal would be 25.175 MHz); the
   // error is 0.7% -- tolerance is supposed to be 0.5%, but it's close
   // enough (we could drop 6-8 pixels from the horizontal refresh to
   // match better if this is an issue.)
   //
   // Horizontal:
   //  16 pixels back porch
   //  96 pixels hsync
   //  48 pixels front porch
   // 640 pixels active
   //
   // Note that the beginning of a "line" is with the back porch of
   // the previous line; we start counting at -160 with active pixels
   // >= 0.  The reason for this is that we start fetching data
   // for any one line as soon as the horizontal blank 
   //
   // Vertical:
   // 480 lines active
   //  10 lines back porch
   //   2 lines vsync
   //  33 lines front porch
   //
   parameter 	 hsync_minus = 1'b1; // -hsync
   parameter 	 vsync_minus = 1'b1; // -vsync

   parameter [10:0] h_active    = 11'd640;
   parameter [10:0] h_ctrstart  = -16-96-48;
   parameter [10:0] h_syncstart = -96-48;
   parameter [10:0] h_syncend   = -48;

   parameter  [9:0] v_active    = 10'd480;
   parameter  [9:0] v_syncstart = v_active + 10;
   parameter  [9:0] v_syncend   = v_syncstart + 2;
   parameter  [9:0] v_total     = v_syncend + 33;

   reg [25:0] 	 ctl_row0start;
   reg [25:0] 	 ctl_rowNstart;
   reg [25:0] 	 ctl_rowstride;
   reg [8:0] 	 ctl_rowN;
   reg [1:0] 	 ctl_mode;
   reg [8:0] 	 ctl_dacxor;
   
   reg [25:0] 	 rowaddr;
   
   reg [3:0]     r;
   reg [3:0] 	 g;
   reg [3:0] 	 b;
   reg 		 hsync;
   reg 		 vsync;

   assign vga_r  = r;
   assign vga_g  = g;
   assign vga_b  = b;
   assign vga_hs = hsync;
   assign vga_vs = vsync;
   
   reg [10:0] 	 xctr;
   reg [9:0] 	 yctr;
   reg [1:0] 	 xseq;		// Sequencer for per-horizontal-line events
   
   reg [7:0] 	 pixel;
   reg [15:0] 	 pixeldata;
   reg [3:0] 	 pixelcnt;
   
   wire 	 xblank = xctr[10];
   wire 	 yblank = (yctr >= v_active);
   wire 	 blank = xblank | yblank;
   reg [1:0] 	 blank_q;	// Track the blanking through the pixel pipe

   reg 		 hblank_q;
   reg 		 vblank_q;

   // Blanking signals out
   always @(negedge rst_n or posedge clk)
     if ( ~rst_n )
       begin
	  hblank_q <= 1'b0;
	  vblank_q <= 1'b0;
       end
     else
       begin
	  hblank_q <= xblank;
	  vblank_q <= yblank;
       end

   assign hblank_n = ~hblank_q;
   assign vblank_n = ~vblank_q;

   // Handshaking with memory controller
   assign vdu_a    = rowaddr[25:4];
   assign vdu_cnt  = ( ctl_mode == 2'b00 ) ? 7'd11 :
	             ( ctl_mode == 2'b01 ) ? 7'd21 :
	             ( ctl_mode == 2'b10 ) ? 7'd41 : 7'd81;

   //
   // Control register read/write
   //
   // Control registers are as follows:
   // $0000 - DWORD - Row 0 start (in bits!)
   // $0004 - DWORD - Row N start (in bits!)
   // $0008 - DWORD - Row stride  (in bits!)
   // $000C - WORD  - Row N
   // $000E - WORD  - Mode
   // $0010 - WORD  - Pixel XOR value
   // $0012 - WORD  - Horizontal counter
   // $0014 - WORD  - Vertical counter
   // $8xxx - WORD x 512 - RAMDAC
   //
   wire [15:0] 	 cpu_di_ramdac;
   reg  [15:0] 	 cpu_di_out;

   always @(*)
     casex ( { cpu_a[15], cpu_a[4:1] } )
       5'b00000: cpu_di_out = { 6'b0, ctl_row0start[25:16] };
       5'b00001: cpu_di_out = ctl_row0start[15:0];
       5'b00010: cpu_di_out = { 6'b0, ctl_rowNstart[25:16] };
       5'b00011: cpu_di_out = ctl_rowNstart[15:0];
       5'b00100: cpu_di_out = { 6'b0, ctl_rowstride[25:16] };
       5'b00101: cpu_di_out = ctl_rowstride[15:0];
       5'b00110: cpu_di_out = { 7'b0, ctl_rowN };
       5'b00111: cpu_di_out = { 14'b0, ctl_mode };
       5'b01000: cpu_di_out = { 7'b0, ctl_dacxor };
       5'b01001: cpu_di_out = { {5{xctr[10]}}, xctr };
       5'b01010: cpu_di_out = { 6'b0, yctr };
       5'b1xxxx: cpu_di_out = cpu_di_ramdac;
       default:  cpu_di_out = 16'hxxxx;
     endcase

   assign cpu_di = (msel_ctl & cpu_r_wn) ? cpu_di_out : 16'hffff;

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  ctl_row0start  <= 22'h0;
	  ctl_rowNstart  <= 22'h0;
	  ctl_rowstride  <= 22'd5120; // 640 * 8
	  ctl_rowN       <= 9'h1ff;   // No split
	  ctl_mode       <= 2'b11;    // 8 bpp
	  ctl_dacxor     <= 9'h0;
       end
     else
       if ( msel_ctl & ~cpu_a[15] & ~cpu_r_wn )
	 case ( cpu_a[4:1] )
	   4'b0000:
	     begin
		if ( ~cpu_be_n[0] ) ctl_row0start[25:16] <= cpu_do[9:0];
	     end
	   4'b0001:
	     begin
		if ( ~cpu_be_n[1] ) ctl_row0start[15:8]  <= cpu_do[15:8];
		if ( ~cpu_be_n[0] ) ctl_row0start[7:0]   <= cpu_do[7:0];
	     end
	   4'b0010:
	     begin
		if ( ~cpu_be_n[0] ) ctl_rowNstart[25:16] <= cpu_do[9:0];
	     end
	   4'b0011:
	     begin
		if ( ~cpu_be_n[1] ) ctl_rowNstart[15:8]  <= cpu_do[15:8];
		if ( ~cpu_be_n[0] ) ctl_rowNstart[7:0]   <= cpu_do[7:0];
	     end
	   4'b0100:
	     begin
		if ( ~cpu_be_n[0] ) ctl_rowstride[25:16] <= cpu_do[9:0];
	     end
	   4'b0101:
	     begin
		if ( ~cpu_be_n[1] ) ctl_rowstride[15:8]  <= cpu_do[15:8];
		if ( ~cpu_be_n[0] ) ctl_rowstride[7:0]   <= cpu_do[7:0];
	     end
	   4'b0110:
	     begin
		if ( ~cpu_be_n[1] ) ctl_rowN[8] <= cpu_do[8];
		if ( ~cpu_be_n[0] ) ctl_rowN[7:0] <= cpu_do[7:0];
	     end
	   4'b0111:
	     begin
		if ( ~cpu_be_n[0] ) ctl_mode    <= cpu_do[1:0];
	     end
	   4'b1000:
	     begin
		if ( ~cpu_be_n[1] ) ctl_dacxor[8]   <= cpu_do[8];
		if ( ~cpu_be_n[0] ) ctl_dacxor[7:0] <= cpu_do[7:0];
	     end
	 endcase // case ( cpu_a[4:1] )

   //
   // Video generation
   //

   // The address of the next row
   reg [25:0] nextaddr;

   always @(*)
     if ( yctr == ctl_rowN )
       nextaddr = ctl_rowNstart;
     else if ( yctr == 9'd0 )
       nextaddr = ctl_row0start;
     else
       nextaddr = rowaddr + ctl_rowstride;

   // Should we advance the pixel shift register?
   reg        advance;

   // This signal is true when consuming data from vdu_d
   assign     vdu_ack = advance & ~|pixelcnt;
   
   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  xctr           <= h_ctrstart;
	  yctr           <= 9'h0;
	  xseq           <= 2'b01;

	  rowaddr        <= 22'hxxxxxx;
	  pixeldata      <= 16'hxxxx;
	  pixelcnt       <= 4'd0;

	  advance        <= 1'b0;
       end // if (~rst_n)
     else
       begin
	  if ( advance )
	    begin
	       if ( ~|pixelcnt )
		 begin
		    pixeldata         <= vdu_d;
		    case (ctl_mode)
		      2'b00: pixelcnt <= 4'd15;
		      2'b01: pixelcnt <= 4'd7;
		      2'b10: pixelcnt <= 4'd3;
		      2'b11: pixelcnt <= 4'd1;
		    endcase
		 end
	       else
		 begin
  		    case (ctl_mode)
		      2'b00: pixeldata <= { pixeldata[14:0], 1'bx };
		      2'b01: pixeldata <= { pixeldata[13:0], 2'bxx };
		      2'b10: pixeldata <= { pixeldata[11:0], 4'bxxxx };
		      2'b11: pixeldata <= { pixeldata[ 7:0], 8'bxxxxxxxx };
		    endcase // case(ctl_mode & {2{~xblank}})
		    pixelcnt <= pixelcnt - 1'b1;
		 end // else: !if( pixelcnt == 3'd0 )
	    end // if ( advance )

	  xseq[1] <= xseq[0];
	  if ( xctr == h_active-1 )
	    begin
	       advance <= 1'b0;
	       xctr <= h_ctrstart;
	       xseq[0] <= 1'b1;
	       yctr <= yctr + 1'b1;
	       if ( yctr >= v_total )
		 yctr <= 9'd0;
	    end
	  else
	    begin
	       // We start advancing 15 pixels before unblank; combined
	       // with the setting of pixelcnt below this ensures that we
	       // have the right data shifted and ready at the proper time.
	       advance <= advance | (~yblank & &xctr[9:4]);
	       xctr <= xctr + 1'b1;
	       xseq[0] <= 1'b0;
	    end // else: !if( xctr == h_active-1 )

	  if ( xseq[0] )
	    begin
	       rowaddr        <= nextaddr;
	       case (ctl_mode)
		 2'b00: pixelcnt <= { ~nextaddr[3:0] };
		 2'b01: pixelcnt <= { 1'b1, ~nextaddr[3:1] };
		 2'b10: pixelcnt <= { 2'b11, ~nextaddr[3:2] };
		 2'b11: pixelcnt <= { 3'b111, ~nextaddr[3] };
	       endcase // case(ctl_mode)
	    end
       end // else: !if(~rst_n)

   assign vdu_start = xseq[1];
   
   // Pixel data selector - would be so much easier in littleendian, sigh
   always @(*)
     case (ctl_mode)
       2'b00: pixel = { 7'b0, pixeldata[15] };
       2'b01: pixel = { 6'b0, pixeldata[15:14] };
       2'b10: pixel = { 4'b0, pixeldata[15:12] };
       2'b11: pixel = pixeldata[15:8];
     endcase // case(mode)

   // Actual RAMDAC
   wire [15:0] dac_out;
   
   ramdac ramdac (
		  .clock ( clk ),
		  
		  .address_a ( cpu_a[9:1] ),
		  .byteena_a ( ~cpu_be_n ),
		  .data_a ( cpu_do ),
		  .wren_a ( msel_ctl & cpu_a[15] ),
		  .q_a ( cpu_di_ramdac ),

		  .address_b ( { 1'b0, pixel } ^ ctl_dacxor ),
		  .data_b ( 16'hxxxx ),
		  .wren_b ( 1'b0 ),
		  .q_b ( dac_out )
		  );

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  hsync <= hsync_minus;
	  vsync <= vsync_minus;

	  r <= 4'h0;
	  g <= 4'h0;
	  b <= 4'h0;

	  blank_q <= 2'b00;
       end
     else
       begin
	  // 2 cycles delay to catch up with the pipeline
	  blank_q <= { blank_q[0], blank };
	  
	  hsync <= ((xctr >= h_syncstart) & (xctr < h_syncend)) ^ hsync_minus;
	  vsync <= ((yctr >= v_syncstart) & (yctr < v_syncend)) ^ vsync_minus;

	  r <= dac_out[11:8] & ~{4{blank_q[1]}};
	  g <= dac_out[7:4]  & ~{4{blank_q[1]}};
	  b <= dac_out[3:0]  & ~{4{blank_q[1]}};
       end // else: !if(~rst_n)
   
endmodule // display