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authorH. Peter Anvin <hpa@zytor.com>2011-06-15 05:10:03 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2011-06-15 05:10:03 (GMT)
commitc11f98e9cc2ca16c9410a692172ecaa266d65646 (patch)
treee4173d89590142590db1055364e63a4ed1844981
parent70b88d7c1540dd54b4b68103a5bee73388a0542f (diff)
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de1.qsf: add enc28j60.v, update Quartus
Update to Quartus version 11 Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--de1/de1.qsf87
1 files changed, 44 insertions, 43 deletions
diff --git a/de1/de1.qsf b/de1/de1.qsf
index 522ce47..7bb46f2 100644
--- a/de1/de1.qsf
+++ b/de1/de1.qsf
@@ -34,7 +34,7 @@
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
-set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name LAST_QUARTUS_VERSION 11.0
# Pin & Location Assignments
# ==========================
@@ -324,18 +324,18 @@ set_location_assignment PIN_U20 -to sd_dat3
# Timing Assignments
# ==================
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name AUTO_ROM_RECOGNITION ON
-set_global_assignment -name AUTO_RAM_RECOGNITION ON
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name TOP_LEVEL_ENTITY abc8000_de1
@@ -348,10 +348,10 @@ set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
-set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
@@ -365,10 +365,10 @@ set_global_assignment -name MAX_SCC_SIZE 50
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
-set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
# Assembler Assignments
@@ -379,7 +379,7 @@ set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
-set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name GENERATE_HEX_FILE ON
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
@@ -437,7 +437,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
-set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
# ------------------
# start CLOCK(clkin)
@@ -523,7 +523,7 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
@@ -544,7 +544,7 @@ set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name PARALLEL_SYNTHESIS ON
+set_global_assignment -name PARALLEL_SYNTHESIS ON
set_global_assignment -name POWER_USE_TA_VALUE 30
set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
@@ -557,32 +557,33 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_g
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vga_r
set_global_assignment -name MISC_FILE de1.dpf
-set_global_assignment -name VERILOG_FILE ../debounce.v
-set_global_assignment -name VERILOG_FILE ../display.v
-set_global_assignment -name VERILOG_FILE ../ps2.v
-set_global_assignment -name VERILOG_FILE ../sdcard.v
-set_global_assignment -name VERILOG_FILE ../sdram.v
-set_global_assignment -name VERILOG_FILE ../serial.v
-set_global_assignment -name VHDL_FILE ../tg68/TG68.vhd
-set_global_assignment -name VHDL_FILE ../tg68/TG68_fast.vhd
-set_global_assignment -name VHDL_FILE ../ym2149/vol_table_array.vhd
-set_global_assignment -name VHDL_FILE ../ym2149/YM2149_volmix.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_pkg.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_interrupts.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_gpio.vhd
-set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_tx.vhd
-set_global_assignment -name VERILOG_FILE ../mega/bytefifo.v
-set_global_assignment -name VERILOG_FILE ../mega/ddio_out.v
-set_global_assignment -name VERILOG_FILE ../mega/pll1.v
-set_global_assignment -name VERILOG_FILE ../mega/pll2.v
-set_global_assignment -name VERILOG_FILE ../mega/ramdac.v
-set_global_assignment -name VERILOG_FILE de1.v
-set_global_assignment -name SDC_FILE de1.sdc
-set_global_assignment -name VERILOG_FILE i2c.v
-set_global_assignment -name VERILOG_FILE sound.v
+set_global_assignment -name VERILOG_FILE ../enc28j60.v
+set_global_assignment -name VERILOG_FILE ../debounce.v
+set_global_assignment -name VERILOG_FILE ../display.v
+set_global_assignment -name VERILOG_FILE ../ps2.v
+set_global_assignment -name VERILOG_FILE ../sdcard.v
+set_global_assignment -name VERILOG_FILE ../sdram.v
+set_global_assignment -name VERILOG_FILE ../serial.v
+set_global_assignment -name VHDL_FILE ../tg68/TG68.vhd
+set_global_assignment -name VHDL_FILE ../tg68/TG68_fast.vhd
+set_global_assignment -name VHDL_FILE ../ym2149/vol_table_array.vhd
+set_global_assignment -name VHDL_FILE ../ym2149/YM2149_volmix.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_pkg.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_interrupts.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_gpio.vhd
+set_global_assignment -name VHDL_FILE ../mfp68901/wf68901ip_usart_tx.vhd
+set_global_assignment -name VERILOG_FILE ../mega/bytefifo.v
+set_global_assignment -name VERILOG_FILE ../mega/ddio_out.v
+set_global_assignment -name VERILOG_FILE ../mega/pll1.v
+set_global_assignment -name VERILOG_FILE ../mega/pll2.v
+set_global_assignment -name VERILOG_FILE ../mega/ramdac.v
+set_global_assignment -name VERILOG_FILE de1.v
+set_global_assignment -name SDC_FILE de1.sdc
+set_global_assignment -name VERILOG_FILE i2c.v
+set_global_assignment -name VERILOG_FILE sound.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file