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authorH. Peter Anvin <hpa@zytor.com>2011-11-10 03:10:20 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2011-11-10 03:10:20 (GMT)
commit85e19afad2760f2a2bd14e87e5929d74caca8ad0 (patch)
treeec8bfe95f3eb3019f6de915c717f2a6ff63c3dbc
parent4783d2a98569417997b31e5f8c8dd6eeb17cd727 (diff)
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display: make vdu_ack combinatorial
Make vdu_ack combinatorial, so the memory unit observes data being consumed when it happens and not a pixel later.
-rw-r--r--display.v11
1 files changed, 3 insertions, 8 deletions
diff --git a/display.v b/display.v
index 529e572..ec675de 100644
--- a/display.v
+++ b/display.v
@@ -117,9 +117,6 @@ module display (
assign vblank_n = ~vblank_q;
// Handshaking with memory controller
- reg vdu_ack_q;
-
- assign vdu_ack = vdu_ack_q;
assign vdu_a = rowaddr[25:4];
assign vdu_cnt = ( ctl_mode == 2'b00 ) ? 7'd11 :
( ctl_mode == 2'b01 ) ? 7'd21 :
@@ -244,6 +241,9 @@ module display (
5'b011_10: advance = (xctr[3:0] > { 2'b11, ~rowaddr[3:2] });
5'b011_11: advance = (xctr[3:0] > { 3'b111, ~rowaddr[3] });
endcase // casex( { yblank, xblank, &xctr[9:4], ctl_mode } )
+
+ // This signal is true when consuming data from vdu_d
+ assign vdu_ack = advance & ~|pixelcnt;
always @(negedge rst_n or posedge clk)
if (~rst_n)
@@ -255,19 +255,14 @@ module display (
rowaddr <= 22'hxxxxxx;
pixeldata <= 16'hxxxx;
pixelcnt <= 4'd0;
-
- vdu_ack_q <= 1'b0;
end // if (~rst_n)
else
begin
- vdu_ack_q <= 1'b0;
-
if ( advance )
begin
if ( ~|pixelcnt )
begin
pixeldata <= vdu_d;
- vdu_ack_q <= 1'b1;
case (ctl_mode)
2'b00: pixelcnt <= 4'd15;
2'b01: pixelcnt <= 4'd7;