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// -----------------------------------------------------------------------
//
//   Copyright 2016 H. Peter Anvin - All Rights Reserved
//
//   This program is free software; you can redistribute it and/or modify
//   it under the terms of the GNU General Public License as published by
//   the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
//   Boston MA 02110-1301, USA; either version 2 of the License, or
//   (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------

//
// neopixel.v
//
// Driver for WS281x/SK6812 (neopixel) LED chains
//
// This drives 32 output channels and expects a 25 MHz clock.
// As long as the external RAM can keep up, the number of channels
// should scale with clock frequency.
//

module neopixel (
		 // System signals
		 input         rst_n,
		 input         clk,
		 input         enable,

		 // CPU interface to the config RAM
		 input  [7:0]  cpu_do,
		 input  [6:0]  cpu_a,
		 input         cpu_wr_n,
		 input         cpu_rd_n,
		 output [7:0]  cpu_di,

		 // SRAM interface
		 output [18:0] ram_a, // BIT address into system RAM
		 input         ram_q, // Expected one cycle later

		 // Neopixel pulse output
		 output reg [31:0] npout
		 );

   // Code assumes pulse0 < pulse1
   //
   // Documented times (in ns) are (±150 ns):
   //
   //		WS2811		WS2182		WS2812B		SK6812
   // T0H	250/500		350		400		300
   // T1H	400/800		800		800		600
   // TH+TL	1250/2500	1250±600	1250±600	1250±600
   //
   // Our cycle time is 32x40 ns = 1280 ns.
   //

   parameter pulse0 =  8;	// 320 ns
   parameter pulse1 = 20;	// 800 ns

   // Pipeline stages:
   // A - generate address for config/status RAM
   // B - generate address for SRAM, advance staus RAM
   //     pulse shaping (delay line for data)

   reg g_enable;		// Global enable, latched on word boundaries

   // Bit/channel counters
   // 32 channels x 24 bits
   reg [9:0] a_ctr;
   reg [9:0] b_ctr;

   wire [9:0] a_ctr_p1 = a_ctr + 1'b1;

   always @(negedge rst_n or posedge clk)
     if (~rst_n)
       begin
	  a_ctr <= 10'd0;
	  b_ctr <= 10'd1;
	  g_enable <= 1'b0;
       end
     else
       begin
	  // a_ctr[9:5] counts from 0 to 23 (bits per word)
	  if (&a_ctr_p1[9:8])
	    begin
	       a_ctr    <= 10'b0;
	       g_enable <= enable;
	    end
	  else
	    begin
	       a_ctr <= a_ctr_p1;
	    end

	  b_ctr <= a_ctr;
       end // else: !if(~rst_n)

   // A stage, counter fed to RAMs

   wire [7:0]  conf_cpu_q;
   wire [31:0] b_conf_q;

   // Configuration RAM
   npconfram npconfram (
			.clock ( clk ),

			.address_a ( a_ctr[4:0] ),
			.data_a ( 32'bx ),
			.wren_a ( 1'b0 ), // Readonly port
			.q_a ( b_conf_q ),

			.address_b ( cpu_a ),
			.data_b ( cpu_do ),
			.wren_b ( ~cpu_wr_n ),
			.q_b ( conf_cpu_q )
			);

   assign cpu_di = ~cpu_rd_n ? conf_cpu_q : ~8'b0;

   wire [16:0] b_stat_q;
   reg  [16:0] b_stat_d;

   // Status RAM
   npstatram npstatram (
			.clock ( clk ),

			.rdaddress ( a_ctr[4:0] ),
			.q ( b_stat_q ),

			.wraddress ( b_ctr[4:0] ),
			.wren ( 1'b1 ),
			.data ( b_stat_d )
			);

   // B stage, SRAM address generation

   wire [15:0] b_conf_addr = b_conf_q[15:0];
   wire  [7:0] b_conf_plen = b_conf_q[23:16]; // Pattern len
   wire  [7:0] b_conf_clen = b_conf_q[31:24]; // Chain len

   wire  [7:0] b_stat_pctr = b_stat_q[7:0];
   wire  [8:0] b_stat_cctr = b_stat_q[16:8];

   // Channel is enabled if plen > 0 or global disable
   wire b_ena = |b_conf_plen & |b_conf_clen & g_enable;

   //
   // This is true immediately before before stat ctr wrap.
   //
   // Chain reset (end of transmission) requires 300 µs starting
   // with WS2813.  This is 234 bit times; to simplify the circuitry
   // and give us enough margin we implement this as
   // 241 bit-times = 308.5 µs.
   //
   // We use negative numbers (2's complement) for reset;
   // this therefore turns true for cycle -241.
   //
   wire b_stat_end = b_stat_cctr[8] & ~b_stat_cctr[7:4];

   wire [7:0]  b_stat_pctr_p1 = b_stat_pctr + 1'b1;

   always @(*)
     begin
	b_stat_d = b_stat_q;

	if ( ~b_ena )
	  begin
	     b_stat_d[7:0]  = 8'b0;
	     b_stat_d[16:8] = ~9'b0;
	  end
	else
	  begin
	     if (b_ctr[9] & &b_ctr[7:5]) // New word?
	       begin
		  b_stat_d[7:0] = (b_stat_end | ~|(b_stat_pctr_p1^b_conf_plen))
		    ? 8'b0 : b_stat_pctr_p1;

		  b_stat_d[16:8] = (b_stat_end
				     ? {1'b0, b_conf_clen} : b_stat_cctr) - 1'b1;
	       end
	  end // else: !if( ~b_ena )
     end // always @ (*)

   // Output: are we in chain reset?
   wire b_in_rst = ~b_ena | b_stat_cctr[8];

   // Byte address in RAM
   // The WS2812 wants data in order GRB, so we swizzle the addresses
   // slightly so we can use RGB order in memory.

   // XXX: for a 32-bit version of this design, it would make more
   // sense to count bytes rather than LEDs, and just drop this.  This
   // would provide better support for RGBW as well as a mix of LED types.

   wire [1:0] b_ctr_byte = { b_ctr[9], ~b_ctr[9]^b_ctr[8] };
   wire [15:0] b_stat_addr = b_conf_addr + b_stat_pctr*2'd3 + b_ctr_byte;

   // b_ctr[7:5] is inverted as bit order is bigendian
   assign ram_a = { b_stat_addr, ~b_ctr[7:5] };

   // Pulse generation.  We can start the pulse even before the data
   // arrives from SRAM, as we will already know if we are in reset!

   // Shift register to delay data for pulse generation
   reg [pulse0-2:0] data_q;
   always @(posedge clk)
     data_q <= { ram_q, data_q[pulse0-2:1] };

   // Output pulse generation
   genvar i;
   generate
      for (i = 0; i < 32; i = i + 1)
	begin: gen_npout
	   always @(negedge rst_n or posedge clk)
	     if ( ~rst_n )
	       npout[i] <= 1'b0;
	     else
	       begin
		  case ( b_ctr[4:0] )
		    (i & 5'h1f):
		      npout[i] <= ~b_in_rst;
		    ((i+pulse0) & 5'h1f):
		      npout[i] <= npout[i] & data_q[0];
		    ((i+pulse1) & 5'h1f):
		      npout[i] <= 1'b0;
		  endcase // case ( b_ctr[4:0] )
	       end // else: !if( ~rst_n )
	end // block: gen_npout
   endgenerate

endmodule // neopixel