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// -----------------------------------------------------------------------
//
//   Copyright 2011 H. Peter Anvin - All Rights Reserved
//
//   Permission is hereby granted, free of charge, to any person
//   obtaining a copy of this software and associated documentation
//   files (the "Software"), to deal in the Software without
//   restriction, including without limitation the rights to use,
//   copy, modify, merge, publish, distribute, sublicense, and/or
//   sell copies of the Software, and to permit persons to whom
//   the Software is furnished to do so, subject to the following
//   conditions:
//
//   The above copyright notice and this permission notice shall
//   be included in all copies or substantial portions of the Software.
//
//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
//   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
//   OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
//   NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
//   HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
//   WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
//   FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
//   OTHER DEALINGS IN THE SOFTWARE.
//
// -----------------------------------------------------------------------

//
// enc28j60.v
//
// Driver for the Microchip ENC28J60 SPI Ethernet controller
//

module enc28j60 (
	       input         rst_n,	// Global reset
	       input         clk,	// CPU clk (25 MHz)

	       output        eth_cs_n,	// SPI CS#
	       output        eth_mosi,	// SPI MOSI (SI)
	       output        eth_sck,	// SPI SCLK
	       input         eth_miso,	// SPI MISO (SO)

	       input   [7:0] abc_do,	// ABC-bus data out (CPU->controller)
	       output  [7:0] abc_di,	// ABC-bus data in (controller->CPU)
	       input         abc_out_n, // ABC-bus data out select (OUT 0)
	       input         abc_cs_n,	// ABC-bus Card Select
	       input         abc_c1_n,	// ABC-bus Command 1 (OUT 2)
	       input         abc_c2_n,	// ABC-bus Command 2 (OUT 3)
	       input         abc_c3_n,	// ABC-bus Command 3 (OUT 4)
	       input	     abc_c4_n,	// ABC-bus Command 4 (OUT 5)
	       input	     abc_inp_n,	// ABC-bus data in select (IN 0)
	       input         abc_status_n, // ABC-bus status (IN 1)
	       input         abc_rst_n,	// ABC-bus reset (IN 7)
	       output        abc_rdy,   // ABC-bus RDY/WAIT#

	       output        select     // Selected LED
	       );

   // ------------------------------------------------------------------------
   //
   //  ENC28J60 supports up to 20 MHz on the SPI bus, but we run it at
   //  CPU clk / 2 (12.5 MHz).  However, all fixed timings are such that
   //  running this module up to 40 MHz for a 20 MHz output should work.
   //
   //  Write commands:
   //  OUT	- send data byte, leave CS# asserted
   //  C1	- send data byte, deassert CS#
   //  C3	- reset
   //  Read commands:
   //  INP	- read input shift register, output FF, leave CS# asserted
   //  STATUS	- read input shift register, deassert CS#
   // ------------------------------------------------------------------------

   parameter                 selectcode = 6'd9;
   reg                       selected;
   assign                    select = selected;

   reg [7:0]		     spi_shr_out;
   reg [7:0]		     spi_shr_in;
   reg [3:0]		     spi_ctr;		// Bit or cycle counter

   reg			     spi_cs_n;
   reg			     spi_clk;

   reg			     spi_active;
   reg			     spi_cmd_ok;
   reg                       spi_finish;

   assign		     eth_cs_n = spi_cs_n;
   assign		     eth_sck  = spi_clk;
   assign		     eth_mosi = spi_shr_out[7];

   wire abc_start   =   selected & (~abc_out_n | ~abc_c1_n |  ~abc_inp_n );
   wire abc_endread =   selected & ~abc_status_n;
   wire abc_active  =   abc_start | abc_endread;
   wire abc_read    =   selected & (~abc_inp_n | ~abc_status_n);
   
   assign		     abc_rdy = ~(abc_active & ~spi_cmd_ok);

   reg [1:0]		     spi_state;
   parameter		     st_idle    = 2'b00;
   parameter		     st_data    = 2'b01;
   parameter		     st_cshold0 = 2'b10;
   parameter		     st_cshold1 = 2'b11;

   wire [7:0] cpu_to_spi_data = (~abc_out_n | ~abc_c1_n) ? abc_do : 8'hff;

   always @(posedge clk)
     if (~rst_n)
       selected <= 1'b0;
     else
       begin
	  if (~abc_rst_n)
	    selected <= 1'b0;
	  else if (~abc_cs_n)
	    selected <= abc_do[5:0] == selectcode;
       end

   always @(posedge clk)
     if (~rst_n | ~abc_rst_n | (selected & ~abc_c3_n))
       begin
	  spi_state   <= st_idle;
	  spi_cs_n    <= 1'b1;
	  spi_clk     <= 1'b0;
	  spi_shr_out <= 8'hff;
	  spi_shr_in  <= 8'hff;
	  spi_ctr     <= 4'd0;
	  spi_finish  <= 1'bx;
	  spi_cmd_ok  <= 1'b0;
       end
     else
       begin
	  spi_cmd_ok  <= spi_cmd_ok & abc_active;

	  case (spi_state)
	    st_idle:
	      begin
		 spi_cmd_ok  <= 1'b1;

		 if (abc_start)
		   begin
		      spi_cs_n    <= 1'b0;
		      spi_state   <= st_data;
		      spi_shr_out <= cpu_to_spi_data;
		      spi_ctr     <= 4'd7;
		      spi_finish  <= ~abc_c1_n;
		   end
	      end // case: spi_idle

	    st_data:
	      begin
		 spi_cs_n      <= 1'b0;
		 spi_clk       <= ~spi_clk;

		 if (spi_clk)
		   begin
		      spi_shr_out <= { spi_shr_out[6:0], 1'b1 };
		      spi_ctr     <= spi_ctr - 1'b1;

		      if (~|spi_ctr)
			begin
			   if (spi_finish)
			     begin
				spi_ctr   <= 4'd8;
				spi_state <= st_cshold0;
			     end
			   else if (abc_endread)
			     begin
				// After STATUS# we raise CS# immediately
				spi_state   <= st_cshold1;
				spi_cs_n    <= 1'b1;
				spi_cmd_ok  <= 1'b1;
			     end
			   else if (abc_start)
			     begin
				spi_shr_out <= cpu_to_spi_data;
				spi_ctr     <= 4'd7;
				spi_finish  <= ~abc_c1_n;
				spi_cmd_ok  <= 1'b1;
			     end
			   else
			     begin
				spi_state   <= st_idle;
				spi_cmd_ok  <= 1'b1;
			     end
			end // if (~|spi_ctr)
		   end // if (spi_clk)
		 else
		   begin
		      spi_shr_in <= { spi_shr_in[6:0], eth_miso };
		   end // else: !if(spi_clk)
	      end // case: spi_data

	    st_cshold0:
	      begin
		 spi_ctr        <= spi_ctr - 1'b1;

		 if (~|spi_ctr)
		   begin
		      spi_cs_n  <= 1'b1;
		      spi_state <= st_cshold1;
		   end
	      end

	    st_cshold1:
	      begin
		 spi_cs_n     <= 1'b1;
		 spi_state    <= st_idle;
		 spi_cmd_ok   <= 1'b1;
	      end

	  endcase
       end // else: !if(~rst_n)

   //
   // Output data
   //
   assign abc_di = abc_read ? spi_shr_in : 8'hff;

endmodule // enc28j60