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# -*- fundamental -*-

# Clock constraints

create_clock -name "clock_50" -period 20ns [get_ports {clock_50}]
create_clock -name "clock_24[0]" -period 41.667ns [get_ports {clock_24[0]}]
create_clock -name "clock_24[1]" -period 41.667ns [get_ports {clock_24[1]}]
create_clock -name "clock_27[0]" -period 37.037ns [get_ports {clock_27[0]}]
create_clock -name "clock_27[1]" -period 37.037ns [get_ports {clock_27[1]}]

# Automatically constrain PLL and other generated clocks
derive_pll_clocks

# Indicate that the clocks are independent
set_clock_groups -asynchronous \
	-group {clock_50 pll1|*} \
	-group {clock_24[*] pll2|*} \
	-group {clock_27[*]}

set_multicycle_path -from [get_keepers {mmuram*q_a[*]}] -to [get_keepers {sram_*_q*}] 4
set_multicycle_path -start -from [get_keepers {msel*[*]}] -to [get_clocks {pll1|*|clk[2]}] 2
set_multicycle_path -from [get_clocks {pll1|*|clk[2]}] -to [get_keepers {sram_*_q*}] 2
set_multicycle_path -from [get_keepers {neopixel:*}] -to [get_keepers {sram_*_q*}] 6
set_multicycle_path -start -from [get_keepers {sram_q[*]}] -to [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] 2
set_multicycle_path -start -from [get_keepers {npled_do}] -to [get_keepers {neopixel:*}] 5

# I/O pin constraints
set_input_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_dq[*]}]
set_input_delay -clock {pll1|*|clk[0]} -max 3ns [get_ports {sram_dq[*]}]
# These numbers are a bit tricky, they appear to be relative to the *next*
# edge of the clock, so -max -1ns refer to a 6ns clock-to-pad delay.
set_output_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_*}]
set_output_delay -clock {pll1|*|clk[0]} -max -1ns [get_ports {sram_*}]

# Automatically calculate clock uncertainty to jitter and other effects.
# Not supported for family Cyclone II
#derive_clock_uncertainty

# Not supported in Quartus II 13.0
#report_metastability

# tsu/th constraints

# tco constraints

# tpd constraints