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DEFAULT_DESIGN_ASSISTANT_SETTINGS
{
	HCPY_ALOAD_SIGNALS = OFF;
	HCPY_VREF_PINS = OFF;
	HCPY_CAT = OFF;
	HCPY_ILLEGAL_HC_DEV_PKG = OFF;
	ACLK_RULE_IMSZER_ADOMAIN = OFF;
	ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF;
	ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF;
	ACLK_CAT = OFF;
	SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF;
	SIGNALRACE_CAT = OFF;
	NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF;
	NONSYNCHSTRUCT_RULE_SRLATCH = OFF;
	NONSYNCHSTRUCT_RULE_DLATCH = OFF;
	NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF;
	NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF;
	NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF;
	NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF;
	NONSYNCHSTRUCT_RULE_REG_LOOP = OFF;
	NONSYNCHSTRUCT_RULE_COMBLOOP = OFF;
	NONSYNCHSTRUCT_CAT = OFF;
	TIMING_RULE_COIN_CLKEDGE = OFF;
	TIMING_RULE_SHIFT_REG = OFF;
	TIMING_RULE_HIGH_FANOUTS = OFF;
	TIMING_CAT = OFF;
	RESET_RULE_ALL = OFF;
	RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF;
	RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF;
	RESET_RULE_REG_ASNYCH = OFF;
	RESET_RULE_COMB_ASYNCH_RESET = OFF;
	RESET_RULE_IMSYNCH_EXRESET = OFF;
	RESET_RULE_UNSYNCH_EXRESET = OFF;
	RESET_RULE_INPINS_RESETNET = OFF;
	RESET_CAT = OFF;
	CLK_RULE_ALL = OFF;
	CLK_RULE_MIX_EDGES = OFF;
	CLK_RULE_CLKNET_CLKSPINES = OFF;
	CLK_RULE_INPINS_CLKNET = OFF;
	CLK_RULE_GATING_SCHEME = OFF;
	CLK_RULE_INV_CLOCK = OFF;
	CLK_RULE_COMB_CLOCK = OFF;
	CLK_CAT = OFF;
	HCPY_EXCEED_USER_IO_USAGE = OFF;
	HCPY_EXCEED_RAM_USAGE = OFF;
	NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF;
	NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF;
	SIGNALRACE_RULE_TRISTATE = OFF;
	ASSG_RULE_MISSING_TIMING = OFF;
	ASSG_RULE_MISSING_FMAX = OFF;
	ASSG_CAT = OFF;
}
SYNTHESIS_FITTING_SETTINGS
{
	AUTO_SHIFT_REGISTER_RECOGNITION = ON;
	AUTO_RAM_RECOGNITION = OFF;
	REMOVE_DUPLICATE_LOGIC = ON;
	AUTO_MERGE_PLLS = ON;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_CARRY_CHAINS = ON;
	AUTO_DELAY_CHAINS = ON;
	STRATIX_CARRY_CHAIN_LENGTH = 70;
	AUTO_PACKED_REG_CYCLONE = NORMAL;
	CYCLONE_OPTIMIZATION_TECHNIQUE = SPEED;
	AUTO_GLOBAL_MEMORY_CONTROLS = ON;
	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
	AUTO_GLOBAL_CLOCK = ON;
	LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
	ENABLE_BUS_HOLD_CIRCUITRY = OFF;
	WEAK_PULL_UP_RESISTOR = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	IGNORE_LCELL_BUFFERS = OFF;
	IGNORE_ROW_GLOBAL_BUFFERS = OFF;
	IGNORE_GLOBAL_BUFFERS = OFF;
	IGNORE_CASCADE_BUFFERS = OFF;
	IGNORE_CARRY_BUFFERS = OFF;
	REMOVE_DUPLICATE_REGISTERS = ON;
	REMOVE_REDUNDANT_LOGIC_CELLS = ON;
	ALLOW_POWER_UP_DONT_CARE = ON;
	PCI_IO = OFF;
	NOT_GATE_PUSH_BACK = ON;
	SLOW_SLEW_RATE = OFF;
	STATE_MACHINE_PROCESSING = AUTO;
}
DEFAULT_HARDCOPY_SETTINGS
{
	HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 ns";
}
DEFAULT_TIMING_REQUIREMENTS
{
	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
	RUN_ALL_TIMING_ANALYSES = ON;
	IGNORE_CLOCK_SETTINGS = OFF;
	DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = OFF;
	NUMBER_OF_PATHS_TO_REPORT = 2000;
	NUMBER_OF_DESTINATION_TO_REPORT = 10;
	NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
	MAX_SCC_SIZE = 50;
	DO_MIN_ANALYSIS = ON;
	DO_MIN_TIMING = OFF;
}
HDL_SETTINGS
{
	VERILOG_INPUT_VERSION = VERILOG_2001;
	VHDL_INPUT_VERSION = VHDL93;
	VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF;
	ENABLE_IP_DEBUG = OFF;
}
PROJECT_INFO(abc80)
{
	ORIGINAL_QUARTUS_VERSION = 2.2;
	LAST_QUARTUS_VERSION = 3.0;
	SHOW_REGISTRATION_MESSAGE = ON;
}
THIRD_PARTY_EDA_TOOLS(abc80)
{
	EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
	EDA_SIMULATION_TOOL = "<NONE>";
	EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
	EDA_BOARD_DESIGN_TOOL = "<NONE>";
	EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
	EDA_RESYNTHESIS_TOOL = "<NONE>";
}
EDA_TOOL_SETTINGS(eda_design_synthesis)
{
	EDA_INPUT_GND_NAME = GND;
	EDA_INPUT_VCC_NAME = VCC;
	EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_INPUT_DATA_FORMAT = EDIF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
}
EDA_TOOL_SETTINGS(eda_simulation)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
	EDA_GENERATE_SDF_OUTPUT_FILE = ON;
	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
}
EDA_TOOL_SETTINGS(eda_timing_analysis)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
	EDA_GENERATE_SDF_OUTPUT_FILE = ON;
	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
}
EDA_TOOL_SETTINGS(eda_board_design)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
	EDA_GENERATE_SDF_OUTPUT_FILE = ON;
	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
}
EDA_TOOL_SETTINGS(eda_formal_verification)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
	EDA_GENERATE_SDF_OUTPUT_FILE = ON;
	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
}
EDA_TOOL_SETTINGS(eda_palace)
{
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_MAINTAIN_DESIGN_HIERARCHY = OFF;
	EDA_GENERATE_SDF_OUTPUT_FILE = ON;
	EDA_WRITE_DEVICE_CONTROL_PORTS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	RESYNTHESIS_RETIMING = FULL;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
}
CLOCK(clkin)
{
	FMAX_REQUIREMENT = "50.0 MHz";
	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
	DUTY_CYCLE = 50;
	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
	MULTIPLY_BASE_CLOCK_PERIOD_BY = 1;
	INVERT_BASE_CLOCK = OFF;
}
CLOCK(pld_clkfb)
{
	DUTY_CYCLE = 50;
	DIVIDE_BASE_CLOCK_PERIOD_BY = 1;
	MULTIPLY_BASE_CLOCK_PERIOD_BY = 2;
	INVERT_BASE_CLOCK = OFF;
	BASED_ON_CLOCK_SETTINGS = clkin;
}