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authorH. Peter Anvin <hpa@zytor.com>2016-11-11 04:06:19 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-11 04:06:19 (GMT)
commitf82772116d1024cea9a05278394a0550a75e3427 (patch)
tree8914be76cfe5db7494897b0c4281d33fe8628af8
parente2851010ab6a08d49d89b40c65f9c2802f104cad (diff)
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Finally: a functional version of the 200 MHz SRAM
The 200 MHz SRAM seems to finally work. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.qsf11
-rw-r--r--abc80.sdc9
-rw-r--r--abc80.v284
-rw-r--r--data/Makefile25
-rwxr-xr-xdata/buildrom.pl2
-rwxr-xr-xdata/mmuinit.pl201
-rwxr-xr-xdata/munge_basic.pl41
-rw-r--r--data/rambasic.asm13
-rw-r--r--mega/mmuram.v42
-rw-r--r--mega/pll1.v10
-rw-r--r--sync.v6
11 files changed, 348 insertions, 296 deletions
diff --git a/abc80.qsf b/abc80.qsf
index 11aaae5..5d25c0f 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -540,7 +540,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name USE_SIGNALTAP_FILE stp6.stp
+set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
@@ -574,7 +574,6 @@ set_global_assignment -name VERILOG_FILE mega/pll2.v
set_global_assignment -name VERILOG_FILE mega/serrxfifo.v
set_global_assignment -name VERILOG_FILE i2c.v
set_global_assignment -name MIF_FILE data/sddrom.mif
-set_global_assignment -name VERILOG_FILE mega/basic80.v
set_global_assignment -name VERILOG_FILE mega/sddrom.v
set_global_assignment -name VERILOG_FILE mega/sddram.v
set_global_assignment -name VERILOG_FILE mega/ddio_out.v
@@ -587,7 +586,6 @@ set_global_assignment -name VHDL_FILE t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE t80/T80.vhd
set_global_assignment -name VHDL_FILE t80/T80s.vhd
set_global_assignment -name VHDL_FILE t80/T80se.vhd
-set_global_assignment -name MIF_FILE data/basic80.mif
set_global_assignment -name MIF_FILE data/videoram.mif
set_global_assignment -name MIF_FILE data/chargen.mif
set_global_assignment -name MIF_FILE data/keyboard.mif
@@ -616,5 +614,8 @@ set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SOURCE_FILE db/abc80.cmp.rdb
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation \ No newline at end of file
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+set_global_assignment -name SIGNALTAP_FILE stp2.stp
+set_global_assignment -name SLD_FILE "/home/hpa/abc80/abc80-de1/stp2_auto_stripped.stp"
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/abc80.sdc b/abc80.sdc
index 64844e9..3dbab3b 100644
--- a/abc80.sdc
+++ b/abc80.sdc
@@ -17,13 +17,8 @@ set_clock_groups -asynchronous \
-group {clock_24[*] pll2|*} \
-group {clock_27[*]}
-set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[2]}] 7
-set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[1]}] 3
-set_multicycle_path -from [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] -to [get_keepers {mmuram:mmu|*portb*}] 2
-set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[2]}] 6
-set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[1]}] 2
-set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[2]}] 6
-set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[1]}] 2
+set_multicycle_path -from [get_keepers {mmuram*q_a[*]}] -to [get_keepers {sram_*_q*}] 4
+set_multicycle_path -start -from [get_keepers {msel[*] mselrd[*] mselwr[*]}] -to [get_clocks {pll1|*|clk[2]}] 2
set_multicycle_path -from [get_clocks {pll1|*|clk[2]}] -to [get_keepers {sram_*_q*}] 2
set_multicycle_path -start -from [get_keepers {sram_do*}] -to [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] 2
diff --git a/abc80.v b/abc80.v
index 65f2535..b1dfd55 100644
--- a/abc80.v
+++ b/abc80.v
@@ -148,9 +148,8 @@ module abc80 (
reg [9:0] prog_ledr;
reg [7:0] prog_led;
- reg [7:0] prog_s7_1;
- reg [7:0] prog_s7_0;
- reg [1:0] prog_led_ctl;
+ reg [6:0] prog_s7[0:3];
+ reg [3:0] prog_led_ctl;
wire [7:0] sd_errled;
@@ -158,10 +157,10 @@ module abc80 (
assign ledr = prog_led_ctl[1] ? prog_ledr : sw;
assign ledg = prog_led_ctl[0] ? prog_led : std_led;
- assign s7_3 = ~prog_s7_1[6:0];
- assign s7_2 = ~prog_s7_0[6:0];
- assign s7_1 = sd_errled[7] ? ~7'b1111001 : ~std_s7_1[6:0];
- assign s7_0 = sd_errled[7] ? ~sd_errled[6:0] : ~std_s7_0[6:0];
+ assign s7_3 = ~prog_s7[3];
+ assign s7_2 = ~prog_s7[2];
+ assign s7_1 = prog_led_ctl[3] ? ~prog_s7[1] : sd_errled[7] ? ~7'b1111001 : ~std_s7_1[6:0];
+ assign s7_0 = prog_led_ctl[2] ? ~prog_s7[0] : sd_errled[7] ? ~sd_errled[6:0] : ~std_s7_0[6:0];
// ------------------------------------------------------------------------
// Timers
@@ -214,9 +213,11 @@ module abc80 (
// ------------------------------------------------------------------------
wire [15:0] cpu_a; // Output address from CPU (used for IORQ)
wire [19:0] mmu_a; // Output address from MMU (within a device)
- reg [7:0] msel; // Decoded device selects for MREQ
- reg [7:0] cpu_di; // Input data to CPU
- wire [7:0] cpu_do; // Output data from CPU
+ reg [7:0] msel; // Decoded device selects for MREQ#
+ reg [7:0] mselwr; // Decoded device selects for MREQ# + RD#
+ reg [7:0] mselrd; // Decoded device selects for MREQ# + WR#
+ reg [7:0] cpu_di; // Input data to CPU
+ wire [7:0] cpu_do; // Output data from CPU
wire cpu_m1_n; // M1# from CPU
wire cpu_iorq_n; // IORQ# from CPU
wire cpu_mreq_n; // MREQ# from CPU
@@ -265,7 +266,7 @@ module abc80 (
reg [5:0] fgxaddr; // Byte address horizontally
reg [8:0] fgyaddr; // Byte address vertically x 2 (see below)
- wire [7:0] sram_fgdata;
+ reg [7:0] sram_fgdata;
reg sram_fgack;
wire fgfull;
wire [4:0] fgwrusedw; // FIFO fill status
@@ -354,7 +355,7 @@ module abc80 (
.q_a ( video_d ),
.clock_a ( video_clk ),
.data_b ( cpu_do ),
- .wren_b ( msel[2] & ~cpu_wr_n ),
+ .wren_b ( mselwr[2] ),
.address_b ( mmu_a[11:0] ),
.q_b ( vram_do ),
.clock_b ( fast_clk )
@@ -366,7 +367,7 @@ module abc80 (
.q_a ( chargen_d ),
.clock_a ( video_clk ),
.data_b ( cpu_do ),
- .wren_b ( msel[3] & ~cpu_wr_n ),
+ .wren_b ( mselwr[3] ),
.address_b ( mmu_a[11:0] ),
.q_b ( cgen_do ),
.clock_b ( fast_clk )
@@ -378,7 +379,7 @@ module abc80 (
.q_a ( bgram_d ),
.clock_a ( video_clk ),
.data_b ( {cpu_do[6], cpu_do[4:0]} ),
- .wren_b ( msel[4] & ~cpu_wr_n ),
+ .wren_b ( mselwr[4] ),
.address_b ( mmu_a[12:0] ),
.q_b ( {bgram_do[6], bgram_do[4:0]} ),
.clock_b ( fast_clk )
@@ -434,7 +435,7 @@ module abc80 (
// ? ns - propagation delay
// ? ns - pad to input register
// 10 ns - output data
- //
+ //
// Events per 25 MHz CPU cycle, numbers correspond to sram_clk_phase:
//
// CPU or fgfifo read:
@@ -496,16 +497,18 @@ module abc80 (
wire [7:0] sram_q; // Data out from sram
reg [7:0] sram_do; // Latched output data from sram
- reg sram_fg_q; // sram_do is for the fg unit
+ reg sram_fg_q; // Data is for the fg unit
+ reg sram_cpu_q; // Data is for the CPU
reg sram_ce_q;
reg sram_oe_q;
reg sram_we_q;
reg sram_fgrd;
reg [18:0] sram_addr_q;
- reg [7:0] sram_d_q; // Output data (from write)
+ reg [7:0] sram_d_q; // Output data (from write)
- // Are we actually accessed by the CPU?
- wire sram_cpu = msel[0] & cpu_clk_en;
+ // Are we actually accessed by the CPU? Use msel_q[] here rather than
+ // msel[] to save two sram_clk cycles.
+ wire sram_cpu = msel_q[0] & ~cpu_mreq_n & cpu_clk_en_q;
wire [18:0] npled_addr = 19'bx; // Just bullshit for now
reg [7:0] npled_do;
@@ -517,25 +520,28 @@ module abc80 (
sram_oe_q <= 1'b0;
sram_we_q <= 1'b0;
sram_fg_q <= 1'b0;
+ sram_cpu_q <= 1'b0;
sram_addr_q <= 19'bx;
sram_d_q <= 8'bx;
sram_do <= 8'bx;
+ sram_fgdata <= 8'bx;
npled_do <= 8'bx;
end // if ( ~rst_n )
else
begin
case (sram_clk_phase)
- 3'd2:
+ 3'd1:
begin
npled_do <= sram_q;
+ sram_d_q <= cpu_do;
if (sram_cpu)
begin
sram_ce_q <= 1'b1;
- sram_we_q <= ~cpu_wr_n;
+ sram_we_q <= ~cpu_wr_n & ~mmu_ro;
sram_oe_q <= ~cpu_rd_n;
sram_addr_q <= mmu_a[18:0];
- sram_d_q <= ~cpu_wr_n ? cpu_do : 8'bx;
+ sram_cpu_q <= 1'b1;
sram_fg_q <= 1'b0;
end
else if (sram_fgrd)
@@ -544,7 +550,7 @@ module abc80 (
sram_we_q <= 1'b0;
sram_oe_q <= 1'b1;
sram_addr_q <= sram_fgaddr;
- sram_d_q <= 8'bx;
+ sram_cpu_q <= 1'b0;
sram_fg_q <= 1'b1;
end
else
@@ -553,23 +559,26 @@ module abc80 (
sram_we_q <= 1'b0;
sram_oe_q <= 1'b0;
sram_addr_q <= 19'bx;
- sram_d_q <= 8'bx;
+ sram_cpu_q <= 1'b0;
sram_fg_q <= 1'b0;
end // else: !if(sram_fgrd)
end
- 3'd5:
+ 3'd4:
begin
sram_we_q <= 1'b0;
end
- 3'd6:
+ 3'd5:
begin
- sram_do <= sram_q;
+ if (sram_fg_q)
+ sram_fgdata <= sram_q;
+ if (sram_cpu_q)
+ sram_do <= sram_q;
- sram_ce_q <= 1'b1;
+ sram_ce_q <= 1'b0;
sram_we_q <= 1'b0;
- sram_oe_q <= 1'b1;
+ sram_oe_q <= 1'b0;
sram_addr_q <= npled_addr;
end
@@ -589,14 +598,11 @@ module abc80 (
assign sram_oe_n = ~sram_oe_q;
assign sram_we_n = ~sram_we_q;
- assign sram_dq = sram_we_q ? { sram_d_q, sram_d_q } : 16'bz;
+ assign sram_dq = ~sram_oe_q ? { sram_d_q, sram_d_q } : 16'bz;
// SRAM Input side MUX
assign sram_q = sram_addr_q[0] ? sram_dq[15:8] : sram_dq[7:0];
- // fg unit FIFO handshake
- assign sram_fgdata = sram_do;
-
always @(negedge rst_n or posedge cpu_clk)
if ( ~rst_n )
begin
@@ -628,7 +634,7 @@ module abc80 (
// ------------------------------------------------------------------------
reg [7:0] flsh_do; // Data out from flash
- wire flsh_oe_w = msel[1] & ~cpu_rd_n;
+ wire flsh_oe_w = mselrd[1];
reg [1:0] flsh_wait_ctr = 2'b00;
wire flsh_wait_n = ~(flsh_oe_w & ~flsh_wait_ctr[1]);
@@ -668,74 +674,90 @@ module abc80 (
assign dram_dq = ~16'b0;
// ------------------------------------------------------------------------
- // BASIC patching ROM for 80-column mode
- // ------------------------------------------------------------------------
-
- wire [15:0] brompatch;
-
- // Patch rom: contains alternate contents for 80-column mode
- basic80 basic_patch (
- .address( mmu_a[7:0] ),
- .clock( fast_clk ),
- .q ( brompatch )
- );
-
- // The patching itself is now done in the CPU data input
-
- // ------------------------------------------------------------------------
// MMU and memory address decoding
// ------------------------------------------------------------------------
wire [15:0] mmu_q; // The actual bits coming out of the MMU
wire [2:0] mmu_devsel; // Undecoded device selects
- wire mmu_patch; // Patch BASIC?
+ wire mmu_ro; // Protect data from writes (where applicable)
- reg [9:0] mmu_mod_addr; // Modify address holding register
+ reg [10:0] mmu_mod_addr; // Modify address holding register
reg [7:0] mmu_mod_data; // Modify data holding register (low byte)
wire mmu_wr_e; // MMU write enable
wire [15:0] mmu_rd_data; // Read data output from MMU
- reg [3:0] mmu_map_sel; // WWRR
- wire [1:0] mmu_map;
+ reg [1:0] mmu_map; // One of four MMU map x 40/80 char mode
- assign mmu_map =
- ~cpu_wr_n ? mmu_map_sel[3:2] :
- mmu_map_sel[1:0];
+ reg [7:0] msel_q; // Stashed memory selects
+ reg [7:0] msel_wq; // Stashed memory selects for write only
+ // The address is available one CPU cycle before MREQ#, RD# and WR# are asserted.
+ // Make the best of that cycle by doing as much work as we can before those signals
+ // are asserted.
mmuram mmu (
- .address_a ( { mmu_map, cpu_a[15:8] } ),
+ .address_a ( { video_width, mmu_map, cpu_a[15:8] } ),
.data_a ( 16'bx ), // Never written
.q_a ( mmu_q ),
.wren_a ( 1'b0 ),
- .clock ( sram_clk ),
- .address_b ( mmu_mod_addr[9:0] ),
+ .clock ( fast_clk ),
+ .address_b ( mmu_mod_addr ),
.data_b ( { cpu_do, mmu_mod_data[7:0] } ),
.q_b ( mmu_rd_data ),
.wren_b ( mmu_wr_e ),
);
- assign mmu_patch = mmu_q[15];
- assign mmu_devsel = mmu_q[14:12];
+ assign mmu_ro = mmu_q[15];
+ assign mmu_devsel = mmu_q[14:12];
assign mmu_a[19:8] = mmu_q[11:0];
- assign mmu_a[7:0] = cpu_a[7:0];
+ assign mmu_a[7:0] = cpu_a[7:0];
- always @(posedge sram_clk)
+ always @(posedge fast_clk)
begin
- if ( ~cpu_mreq_n & cpu_rfsh_n )
- case ( mmu_devsel )
- 3'h0: msel <= 8'b00000001;
- 3'h1: msel <= 8'b00000010;
- 3'h2: msel <= 8'b00000100;
- 3'h3: msel <= 8'b00001000;
- 3'h4: msel <= 8'b00010000;
- 3'h5: msel <= 8'b00100000;
- 3'h6: msel <= 8'b01000000;
- 3'h7: msel <= 8'b10000000;
- endcase // case( mmu_devsel )
- else
- msel <= 8'b00000000;
- end
+ case ( mmu_devsel )
+ 3'h0: msel_q <= 8'b00000001;
+ 3'h1: msel_q <= 8'b00000010;
+ 3'h2: msel_q <= 8'b00000100;
+ 3'h3: msel_q <= 8'b00001000;
+ 3'h4: msel_q <= 8'b00010000;
+ 3'h5: msel_q <= 8'b00100000;
+ 3'h6: msel_q <= 8'b01000000;
+ 3'h7: msel_q <= 8'b10000000;
+ endcase // case( mmu_devsel )
+ end // always @ (posedge sram_clk)
+
+ always @(posedge fast_clk)
+ begin
+ casez ( {mmu_ro, mmu_devsel} )
+ 4'h0: msel_wq <= 8'b00000001;
+ 4'h1: msel_wq <= 8'b00000010;
+ 4'h2: msel_wq <= 8'b00000100;
+ 4'h3: msel_wq <= 8'b00001000;
+ 4'h4: msel_wq <= 8'b00010000;
+ 4'h5: msel_wq <= 8'b00100000;
+ 4'h6: msel_wq <= 8'b01000000;
+ 4'h7: msel_wq <= 8'b10000000;
+ default: msel_wq <= 8'b00000000;
+ endcase // casez ( {mmu_ro, mmu_devsel} )
+ end // always @ (posedge sram_clk)
+
+ reg was_read;
+
+ always @(negedge rst_n or posedge fast_clk)
+ if ( ~rst_n )
+ begin
+ msel <= 8'b0;
+ mselrd <= 8'b0;
+ mselwr <= 8'b0;
+ was_read <= 1'b0;
+ end
+ else
+ begin
+ was_read <= ~cpu_mreq_n & ~cpu_wr_n;
+ msel <= msel_q & {8{~cpu_mreq_n}};
+ mselrd <= msel_q & {8{~cpu_mreq_n & ~cpu_rd_n}};
+ mselwr <= msel_wq & {8{~cpu_mreq_n & ~cpu_wr_n & ~was_read}}; // Pulse for one fast_clk cycle
+ end
// ------------------------------------------------------------------------
// PIO
@@ -1012,7 +1034,7 @@ module abc80 (
.strobe ( key1_strobe )
);
- always @(posedge cpu_clk)
+ always @(negedge rst_n or posedge cpu_clk)
begin
if ( ~rst_n )
video_width <= ~sw[9]; // Set SW9 to go to 40 column after reset
@@ -1024,8 +1046,6 @@ module abc80 (
video_width <= 1'b1;
else if ( key1_strobe & key1_debounced )
video_width <= ~video_width;
- else
- video_width <= video_width; // Help for Quartus
end
end
@@ -1048,7 +1068,7 @@ module abc80 (
reg [3:0] i2c_ctr;
synchronize #(.width(8))
- sound_sc_sync(.d(sound), .q(sound_sc), .reset(1'b0),
+ sound_sc_sync(.d(sound), .q(sound_sc), .reset(1'b0),
.clk(audio_clk), .enable(1'b1));
sound_i2s sound_i2s (
@@ -1139,19 +1159,21 @@ module abc80 (
begin
if ( !rst_n )
begin
- mmu_mod_addr <= 0;
- mmu_mod_data <= 0;
- mmu_map_sel <= 0;
+ mmu_mod_addr <= 8'b0;
+ mmu_mod_data <= 8'b0;
+ mmu_map <= 2'b0;
- nmi_dis <= 0;
+ nmi_dis <= 1'b0;
- turbo_set <= 0;
+ turbo_set <= 1'b0;
- prog_led_ctl <= 0;
- prog_led <= 0;
- prog_ledr <= 0;
- prog_s7_0 <= 0;
- prog_s7_1 <= 0;
+ prog_led_ctl <= 2'b0;
+ prog_led <= 8'b0;
+ prog_ledr <= 10'b0;
+ prog_s7[0] <= 7'b0;
+ prog_s7[1] <= 7'b0;
+ prog_s7[2] <= 7'b0;
+ prog_s7[3] <= 7'b0;
intio_do <= ~8'b0;
@@ -1163,34 +1185,41 @@ module abc80 (
end
else
begin
- intio_do <= ~8'b0;
- turbo_set <= 0;
+ intio_do <= ~8'b0;
+ turbo_set <= 1'b0;
if ( intio_sel & ~cpu_wr_n )
begin
- casex ( cpu_a[6:0] )
+ casez ( cpu_a[6:0] )
7'b0000000:
mmu_mod_addr[7:0] <= cpu_do[7:0];
7'b0000001:
- mmu_mod_addr[9:8] <= cpu_do[1:0];
+ mmu_mod_addr[10:8] <= cpu_do[2:0];
7'b0000010:
mmu_mod_data <= cpu_do[7:0];
- 7'b00001xx:
- mmu_map_sel <= cpu_do[3:0];
- 7'b00100xx:
- turbo_set <= 1;
+ 7'b00001zz:
+ begin
+ mmu_map <= cpu_do[1:0];
+ nmi_dis <= cpu_do[2];
+ end
+ 7'b00100zz:
+ turbo_set <= 1'b1;
7'b0010100:
- prog_led_ctl <= cpu_do[1:0];
+ prog_led_ctl <= cpu_do[3:0];
7'b0010101:
prog_led <= cpu_do[7:0];
7'b0010110:
- prog_s7_0 <= cpu_do[7:0];
+ prog_s7[0] <= cpu_do[6:0];
7'b0010111:
- prog_s7_1 <= cpu_do[7:0];
+ prog_s7[1] <= cpu_do[6:0];
7'b0011000:
prog_ledr[7:0] <= cpu_do[7:0];
7'b0011001:
prog_ledr[9:8] <= cpu_do[1:0];
+ 7'b0011010:
+ prog_s7[2] <= cpu_do[6:0];
+ 7'b0011011:
+ prog_s7[3] <= cpu_do[6:0];
7'b0011110:
fgctl <= cpu_do[7:0];
7'b0011111:
@@ -1223,17 +1252,17 @@ module abc80 (
gpio_dat[cpu_do[5:0]] <= cpu_do[7];
end
end
- endcase // casex cpu_a[6:0] )
+ endcase // casez cpu_a[6:0] )
end // if ( intio_sel & ~cpu_wr_n )
else if ( ~abc_out_n[7] )
begin
// For compatibility with Mikrodatorn's 64K hack
- mmu_map_sel <= { cpu_do[1:0], cpu_do[1:0] };
+ mmu_map <= cpu_do[1:0];
nmi_dis <= cpu_do[2];
end
else if ( intio_sel & ~cpu_rd_n )
begin
- casex ( cpu_a[6:0] )
+ casez ( cpu_a[6:0] )
7'b0000000:
intio_do <= mmu_mod_addr[7:0];
7'b0000001:
@@ -1242,22 +1271,26 @@ module abc80 (
intio_do <= mmu_rd_data[7:0];
7'b0000011:
intio_do <= mmu_rd_data[15:8];
- 7'b00001xx:
- intio_do <= { 4'b0, mmu_map_sel };
- 7'b00100xx:
+ 7'b00001zz:
+ intio_do <= { video_width, 4'b0, nmi_dis, mmu_map };
+ 7'b00100zz:
intio_do <= { 6'b0, cpu_turbo };
7'b0010100:
intio_do <= { 6'b0, prog_led_ctl };
7'b0010101:
intio_do <= prog_led;
7'b0010110:
- intio_do <= prog_s7_0;
+ intio_do <= { 1'b0, prog_s7[0] };
7'b0010111:
- intio_do <= prog_s7_1;
+ intio_do <= { 1'b0, prog_s7[1] };
7'b0011000:
intio_do <= prog_ledr[7:0];
7'b0011001:
intio_do <= prog_ledr[9:8];
+ 7'b0011010:
+ intio_do <= { 1'b0, prog_s7[2] };
+ 7'b0011011:
+ intio_do <= { 1'b0, prog_s7[3] };
7'b0011110:
intio_do <= fgctl;
7'b0011111:
@@ -1294,7 +1327,7 @@ module abc80 (
intio_do <= { 4'b0, gpio_ctl[35:32] };
default:
intio_do <= 8'hFF;
- endcase // casex ( cpu_a[6:0] )
+ endcase // casez ( cpu_a[6:0] )
end // if ( intio_sel & ~cpu_rd_n )
end
end
@@ -1350,23 +1383,21 @@ module abc80 (
assign cpu_nmi_n = ctr_20ms | nmi_dis;
wire cpu_wait_n = 1'b1; // See cpu_clk_en
wire cpu_clk_en;
+ reg cpu_clk_en_q; // Indicates that the CPU advanced
+ // in the previous cycle
always @(*)
begin
- if ( ~cpu_mreq_n & mmu_patch & video_width &
- ( brompatch[15:8] == mmu_a[15:8] ) )
- cpu_di <= brompatch[7:0];
- else
- case ( msel )
- 8'b00000001: cpu_di <= sram_do;
- 8'b00000010: cpu_di <= flsh_do;
- 8'b00000100: cpu_di <= vram_do;
- 8'b00001000: cpu_di <= cgen_do;
- 8'b00010000: cpu_di <= bgram_do;
- 8'b10000000: cpu_di <= mmu_a[15:8];
- 8'b00000000: cpu_di <= io_do;
- default: cpu_di <= 8'bx;
- endcase // case( msel )
+ case ( mselrd )
+ 8'b00000001: cpu_di <= sram_do;
+ 8'b00000010: cpu_di <= flsh_do;
+ 8'b00000100: cpu_di <= vram_do;
+ 8'b00001000: cpu_di <= cgen_do;
+ 8'b00010000: cpu_di <= bgram_do;
+ 8'b10000000: cpu_di <= mmu_a[15:8];
+ 8'b00000000: cpu_di <= io_do;
+ default: cpu_di <= 8'hFF;
+ endcase // case( msel )
end // always @ (*)
// If cpu_turbo is 0, we want to execute at 3 MHz instead of 25
@@ -1411,6 +1442,9 @@ module abc80 (
assign std_led[7:5] = cpu_slow_mask;
+ always @(posedge cpu_clk)
+ cpu_clk_en_q <= cpu_clk_en;
+
always @(*)
case ( cpu_turbo )
2'b00:
diff --git a/data/Makefile b/data/Makefile
index fa0999b..b2b3012 100644
--- a/data/Makefile
+++ b/data/Makefile
@@ -7,15 +7,17 @@ Z80ASM = ../tools/z80asm/z80asm
.asm.bin:
$(Z80ASM) -o$@ -l$*.lst $<
-all : keyboard.mif abc80rom.bin basic80.mif \
+all : keyboard.mif abc80rom.bin \
mmu.mif chargen.mif videoram.mif fgcol.mif sddrom.mif \
abcsefi.bas abcdkno.bas abcintl.bas cpm.bas cpm.abs cpm.bac \
rambasic.bas
-abc80rom.bin : buildrom.pl abcbasic.rom ufddos.bin printer.bin
- $(PERL) buildrom.pl $@ 32768 \
- abcbasic.rom=0,16384 ufddos.bin=0x6000,4096 \
- printer.bin=0x7800
+abc80rom.bin : buildrom.pl abcbasic.rom abcbas80.rom ufddos.bin printer.bin
+ $(PERL) buildrom.pl $@ 0xc000 \
+ abcbasic.rom=0,16384 \
+ ufddos.bin=0x6000,4096 \
+ printer.bin=0x7800 \
+ abcbas80.rom=0x8000,16384
ufddos.bin : ufddos.rom ufdpatch.pl
$(PERL) ufdpatch.pl $< $@
@@ -23,24 +25,15 @@ ufddos.bin : ufddos.rom ufdpatch.pl
keyboard.mif : keyboard.bin $(BIN2MIF)
$(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-basic80.mif : munge_basic.pl
+abcbas80.rom : abcbasic.rom munge_basic.pl
$(PERL) munge_basic.pl || ( rm -f $@ ; exit 1 )
-abcbasic.mif : abcbasic.rom $(BIN2MIF)
- $(PERL) $(BIN2MIF) 16384 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-
-abcdos.mif : ufddos.rom $(BIN2MIF)
- $(PERL) $(BIN2MIF) 4096 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-
videoram.mif : videoram.bin $(BIN2MIF)
$(PERL) $(BIN2MIF) 2048 8 < $< > $@ || ( rm -f $@ ; exit 1 )
sddrom.mif : sddrom.bin $(BIN2MIF)
$(PERL) $(BIN2MIF) 1024 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-printer.mif : printer.bin $(BIN2MIF)
- $(PERL) $(BIN2MIF) 768 8 < $< > $@ || ( rm -f $@ ; exit 1 )
-
mmu.mif : mmuinit.pl
$(PERL) mmuinit.pl > $@ || ( rm -f $@ ; exit 1 )
@@ -91,7 +84,7 @@ fgcol.mif : fgcol.pl
$(PERL) fgcol.pl > $@ || ( rm -f $@ ; exit 1 )
clean:
- rm -f *.obj *.bin *.mif *.bas *.abs *.bac *.lst
+ rm -f *.obj *.bin *.mif *.bas *.abs *.bac *.lst abcbas80.rom
dist: all
rm -f *.obj
diff --git a/data/buildrom.pl b/data/buildrom.pl
index 62ebfeb..96f029f 100755
--- a/data/buildrom.pl
+++ b/data/buildrom.pl
@@ -13,7 +13,7 @@ sub num($) {
}
$file = shift(@ARGV);
-$size = shift(@ARGV);
+$size = num(shift(@ARGV));
$data = "\xff" x $size; # Fill unused memory with FF
diff --git a/data/mmuinit.pl b/data/mmuinit.pl
index fb04118..75be757 100755
--- a/data/mmuinit.pl
+++ b/data/mmuinit.pl
@@ -3,27 +3,37 @@
# Create MMU initialization file
#
-# Each MMU entry is 16 bits; there are 4 address maps total.
-# These are initialized with a 2K video RAM window at 30-32K.
+# Each MMU entry is 16 bits; there are 4 address maps for each of
+# 40-column mode and 80-column mode. These are initialized with
+# 1K/2K video RAM window at 29-31K (80 col only) and 31-32K.
# The defaults match the map uses from Mikrodatorn's 64K RAM
# expansion:
#
+# 40-column mode:
+#
# Map 0: default (32K RAM)
-# Map 1: 0-30K is RAM
-# Map 2: 0-62K RAM; 62-64K video
+# Map 1: 0-31K is RAM
+# Map 2: 0-63K RAM; 63-64K video
# Map 3: 0-64K RAM, no video
#
+# 80-column mode:
+#
+# Map 4: default (32K RAM)
+# Map 5: 0-29K, 30-31K is RAM
+# Map 6: 0-62K RAM; 62-64K video
+# Map 7: 0-64K RAM, no video
+#
# The format of each entry is as follows:
-# Bit [15] -> Apply BASIC "patch" for 80 characters?
+# Bit [15] -> Make memory readonly
# Bits [14:12] -> device index:
# 0 - SRAM
-# 1 - Flash ROM
+# 1 - Flash ROM (RO)
# 2 - Video RAM
# 3 - Character generator RAM
# 4 - Block graphics RAM
# 5 - Reserved
# 6 - Reserved
-# 7 - Hyperspace (reads bits[7:0], writes nowhere)
+# 7 - Hyperspace (reads back bits[7:0], RO)
#
# Bits [11:0] -> A[19:8]
#
@@ -31,94 +41,119 @@
$testram = 0;
$with_bgram = 1;
-sub do_ram() {
+sub do_maps($$)
+{
+ my($testram, $is80) = @_;
+
+ my $a = $is80 ? 4*256 : 0;
+ my $i;
+ my $lorom = $is80 ? 0x9080 : 0x9000;
+ my $hirom = 0x9000; # Do not switch on screen size change
+ my $loram = $is80 ? 0x0100 : 0x0000;
+ my $hiram = 0x0000; # Do not switch on screen size change
+ my $bgram = 0x4000;
+ my $vram = 0x2000;
+ my $nothing = 0xffff;
+
+ # Map 0 (standard)
+ for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC
+ printf("%03X : %04X;\n", $a++, $lorom+$i);
+ }
+ for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Free for expansion
+ printf("%03X : %04X;\n", $a++, $nothing);
+ }
+ for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # Free for expansion or bgram
+ printf("%03X : %04X;\n", $a++,
+ $with_bgram ? $bgram+($i-0x48) : $nothing);
+ }
+ for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS, IEC options
+ printf("%03X : %04X;\n", $a++, $hirom+$i);
+ }
+ for ( $i = 0x74 ; $i < 0x78 ; $i++ ) { # Video RAM (for 80 col only)
+ printf("%03X : %04X;\n", $a++,
+ $is80 ? $vram+($i-0x74) : $nothing);
+ }
+ for ( $i = 0x78 ; $i < 0x7B ; $i++ ) { # PR option
+ printf("%03X : %04X;\n", $a++, $hirom+$i);
+ }
+ for ( $i = 0x7B ; $i < 0x7C ; $i++ ) { # RAM in the PR option area
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( $i = 0x7C ; $i < 0x80 ; $i++ ) { # Video RAM
+ printf("%03X : %04X;\n", $a++, $vram+4+($i-0x7C));
+ }
+ $a = do_ram($testram, $a, $i);
+
+ # Map 1 (standard layout in RAM)
+ for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC
+ printf("%03X : %04X;\n", $a++, $loram+$i);
+ }
+ for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Free for expansion
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # Free for expansion or bgram
+ printf("%03X : %04X;\n", $a++,
+ $with_bgram ? $bgram+($i-0x48) : $hiram+$i);
+ }
+ for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS, IEC options
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( $i = 0x74 ; $i < 0x78 ; $i++ ) { # Video RAM (for 80 col only)
+ printf("%03X : %04X;\n", $a++,
+ $is80 ? $vram + ($i-0x74) : $hiram+$i);
+ }
+ for ( $i = 0x78 ; $i < 0x7B ; $i++ ) { # PR option
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( $i = 0x7B ; $i < 0x7C ; $i++ ) { # RAM in the PR option area
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( $i = 0x7C ; $i < 0x80 ; $i++ ) { # Video RAM
+ printf("%03X : %04X;\n", $a++, $vram + 4 + ($i-0x7C));
+ }
+ $a = do_ram($testram, $a, $i);
+
+ # Map 2 (CP/M with video enabled)
+ for ( $i = 0x00 ; $i < ($is80 ? 0xF8 : 0xFC) ; $i++ ) { # RAM
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+ for ( ; $i < 0x100 ; $i++ ) { # Video RAM
+ printf("%03X : %04X;\n", $a++, $vram + ($i-0xF8));
+ }
+
+ # Map 3 (CP/M all memory)
+ for ( $i = 0x00 ; $i < 0x100 ; $i++ ) { # All RAM
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+}
+
+sub do_ram($$$) {
+ my($testram, $a, $i) = @_;
+
+ my $hiram = 0x0000; # Do not switch on screen size change
+
if ( $testram ) {
# Tiny amount of RAM (4K)
for ( ; $i < 0xF0 ; $i++ ) {
- printf("%03X : %04X;\n", $a++, 0x70FF);
- }
- for ( $i = 0xF0 ; $i < 0x100 ; $i++ ) {
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
- }
- } else {
- for ( ; $i < 0x100 ; $i++ ) {
- # Important: No offset for this index
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
+ printf("%03X : %04X;\n", $a++, $nothing);
}
}
+
+ for ( ; $i < 0x100 ; $i++ ) {
+ printf("%03X : %04X;\n", $a++, $hiram+$i);
+ }
+
+ return $a;
}
-print "DEPTH = 1024;\n";
+print "DEPTH = 2048;\n";
print "WIDTH = 16;\n";
print "ADDRESS_RADIX = HEX;\n";
print "DATA_RADIX = HEX;\n";
print "CONTENT\n";
print "BEGIN\n";
-$a = 0;
-
-# Map 0 (standard)
-for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC
- printf("%03X : %04X;\n", $a++, 0x9000|$i);
-}
-for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Free for expansion
- printf("%03X : %04X;\n", $a++, 0x70FF);
-}
-for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # Free for expansion or bgram
- printf("%03X : %04X;\n", $a++, $with_bgram ? 0x4000|($i-0x48) : 0x70FF);
-}
-for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS, IEC options
- printf("%03X : %04X;\n", $a++, 0x1000|$i);
-}
-for ( $i = 0x74 ; $i < 0x78 ; $i++ ) { # Video RAM (for 80 col only)
- printf("%03X : %04X;\n", $a++, 0x2000|($i-0x74));
-}
-for ( $i = 0x78 ; $i < 0x7B ; $i++ ) { # PR option
- printf("%03X : %04X;\n", $a++, 0x1000|$i);
-}
-for ( $i = 0x7B ; $i < 0x7C ; $i++ ) { # RAM in the PR option area
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
-for ( $i = 0x7C ; $i < 0x80 ; $i++ ) { # Video RAM
- printf("%03X : %04X;\n", $a++, 0x2004|($i-0x7C));
-}
-do_ram();
-
-# Map 1 (standard layout in RAM)
-for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC (in RAM)
- printf("%03X : %04X;\n", $a++, 0x8000|$i);
-}
-for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Expansion (fill with RAM)
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
-for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # RAM or bgram
- printf("%03X : %04X;\n", $a++, $with_bgram ? 0x4000|($i-0x48) : 0x0000|$i);
-}
-for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS and IEC (in RAM)
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
-for ( $i = 0x74 ; $i < 0x78 ; $i++ ) { # Video RAM (for 80 col only)
- printf("%03X : %04X;\n", $a++, 0x2000|($i-0x74));
-}
-for ( $i = 0x78 ; $i < 0x7C ; $i++ ) { # PR option (in RAM)
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
-for ( $i = 0x7C ; $i < 0x80 ; $i++ ) { # Video RAM
- printf("%03X : %04X;\n", $a++, 0x2004|($i-0x7C));
-}
-do_ram();
-
-# Map 2 (CP/M with video enabled)
-for ( $i = 0x00 ; $i < 0xF8 ; $i++ ) { # RAM
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
-for ( $i = 0xF8 ; $i < 0x100 ; $i++ ) { # Video RAM
- printf("%03X : %04X;\n", $a++, 0x2000|($i-0xF8));
-}
-
-# Map 3 (CP/M all memory)
-for ( $i = 0x00 ; $i < 0x100 ; $i++ ) { # All RAM
- printf("%03X : %04X;\n", $a++, 0x0000|$i);
-}
+do_maps($testram, 0); # 40 col
+do_maps($testram, 1); # 80 col
print "END;\n";
diff --git a/data/munge_basic.pl b/data/munge_basic.pl
index 20840d0..30b5185 100755
--- a/data/munge_basic.pl
+++ b/data/munge_basic.pl
@@ -1,6 +1,7 @@
#!/usr/bin/perl
#
# Script to patch ABC80 rom with checksum 9913 to support 80 column text
+# Checksum 11273 should be an easy mod...
#
use bytes;
@@ -21,30 +22,22 @@ for ( $i = 0 ; $i < 24; $i++ ) {
$rompatch{885+2*$i} = ($a >> 8) & 0xff;
}
-# Create patch rom
-$patchwidth = 256;
-@patchrom = (0xffff) x $patchwidth;
-@patched = (undef) x $patchwidth;
-foreach $a ( keys(%rompatch) ) {
- $p = $a % $patchwidth;
- if ( defined($patched[$p]) ) {
- printf STDERR "Address 0x%04x conflicts with 0x%04x\n", $a, $patched{$p};
- exit 1;
- }
- $patched[$p] = $a;
- $patchrom[$p] = (int($a/$patchwidth) << 8) + $rompatch{$a};
+open(ROM, '<', 'abcbasic.rom')
+ or die "$0: abcbasic.rom: $!\n";
+
+if (read(ROM, $rom, 16384) != 16384) {
+ die "$0: abcbasic.rom: $!\n";
}
-# Produce MIF file for the patch ROM
-open(PMIF, "> basic80.mif");
-print PMIF "DEPTH = $patchwidth;\n";
-print PMIF "WIDTH = 16;\n";
-print PMIF "ADDRESS_RADIX = HEX;\n";
-print PMIF "DATA_RADIX = HEX;\n";
-print PMIF "CONTENT\n";
-print PMIF "BEGIN\n";
-for ( $i = 0 ; $i < $patchwidth ; $i++ ) {
- printf PMIF "%02X : %04X;\n", $i, $patchrom[$i];
+close(ROM);
+
+@rom = unpack("C*", $rom);
+
+foreach $p (keys %rompatch) {
+ $rom[$p] = $rompatch{$p};
}
-print PMIF "END;\n";
-close(PMIF);
+
+open(R80, '>', 'abcbas80.rom')
+ or die "$0: abcbas80.rom: $!\n";
+print R80 pack("C*", @rom);
+close(R80);
diff --git a/data/rambasic.asm b/data/rambasic.asm
index 3b7323f..3ca93d5 100644
--- a/data/rambasic.asm
+++ b/data/rambasic.asm
@@ -5,9 +5,8 @@ entry: ; On entry HL points here
inc h ; Buffer at +256 bytes
push hl ; Buffer address
xor a
- ld l,a
+ ld l,a ; HL -> ROM address
ld h,a
- ; DE -> ROM address
; Wait for NMI before copying the first chunk
di
@@ -20,8 +19,9 @@ entry: ; On entry HL points here
add c
ld (hl),a
ld a,(hl)
- sub c
- jr z,error ; A = 0, HL = 0 on error
+ ld (hl),c
+ cp c
+ jr z,error ; HL = 0 on error
copy:
xor a
@@ -49,9 +49,10 @@ copy:
bit 7,h
jr z,copy
- ; A = 1, HL != 0
-
+ ld hl,-1 ; Success
error:
+ pop de ; Drop entry from stack
+ xor a ; Don't switch to RAM yet
out (7),a
ei
diff --git a/mega/mmuram.v b/mega/mmuram.v
index 1ba3ec7..6c448e9 100644
--- a/mega/mmuram.v
+++ b/mega/mmuram.v
@@ -47,8 +47,8 @@ module mmuram (
q_a,
q_b);
- input [9:0] address_a;
- input [9:0] address_b;
+ input [10:0] address_a;
+ input [10:0] address_b;
input clock;
input [15:0] data_a;
input [15:0] data_b;
@@ -105,17 +105,17 @@ module mmuram (
altsyncram_component.init_file = "./data/mmu.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.numwords_a = 1024,
- altsyncram_component.numwords_b = 1024,
+ altsyncram_component.numwords_a = 2048,
+ altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
- altsyncram_component.outdata_reg_a = "UNREGISTERED",
- altsyncram_component.outdata_reg_b = "UNREGISTERED",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.widthad_a = 10,
- altsyncram_component.widthad_b = 10,
+ altsyncram_component.widthad_a = 11,
+ altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
@@ -158,18 +158,18 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./data/mmu.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
@@ -197,24 +197,24 @@ endmodule
// Retrieval info: CONSTANT: INIT_FILE STRING "./data/mmu.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
+// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
@@ -222,8 +222,8 @@ endmodule
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
+// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
diff --git a/mega/pll1.v b/mega/pll1.v
index a085b15..f08b816 100644
--- a/mega/pll1.v
+++ b/mega/pll1.v
@@ -107,7 +107,7 @@ module pll1 (
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 1,
+ altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
@@ -194,7 +194,7 @@ endmodule
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -223,11 +223,11 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
@@ -287,7 +287,7 @@ endmodule
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
diff --git a/sync.v b/sync.v
index 83b12f6..a4060c1 100644
--- a/sync.v
+++ b/sync.v
@@ -51,13 +51,13 @@ module synchronizer(reset, clk, enable, d, q);
always @(posedge clk)
if (reset)
d_q <= {width{1'b0}};
- else // if (stage_enable[0])
+ else if (stage_enable[0])
d_q <= d;
always @(posedge clk)
if (reset)
stage[1] <= {width{1'b0}};
- else // if (stage_enable[1])
+ else if (stage_enable[1])
stage[1] <= d_q;
genvar i;
@@ -67,7 +67,7 @@ module synchronizer(reset, clk, enable, d, q);
always @(posedge clk)
if (reset)
stage[i] <= {width{1'b0}};
- else // if (stage_enable[i])
+ else if (stage_enable[i])
stage[i] <= stage[i-1];
end
endgenerate