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authorH. Peter Anvin <hpa@zytor.com>2016-11-10 05:22:15 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-10 05:22:41 (GMT)
commite2851010ab6a08d49d89b40c65f9c2802f104cad (patch)
tree3fb13de3c1b303c0b19d1f981617eacaa890fdce
parentbf72deac95fd4fe0d996ebab7454ae3118a27d68 (diff)
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The address is available one CPU cycle before MREQ#, use that
To do that, we have to remove the read/write mmu map select, however. While we're at it, drop the ugly "basic patch" hack and instead have separate memory maps for 48 and 80 col.
-rw-r--r--mega/basic80.v139
1 files changed, 0 insertions, 139 deletions
diff --git a/mega/basic80.v b/mega/basic80.v
deleted file mode 100644
index 03d8f56..0000000
--- a/mega/basic80.v
+++ /dev/null
@@ -1,139 +0,0 @@
-// megafunction wizard: %ALTSYNCRAM%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: basic80.v
-// Megafunction Name(s):
-// altsyncram
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-// ************************************************************
-
-
-//Copyright (C) 1991-2003 Altera Corporation
-//Any megafunction design, and related netlist (encrypted or decrypted),
-//support information, device programming or simulation file, and any other
-//associated documentation or information provided by Altera or a partner
-//under Altera's Megafunction Partnership Program may be used only
-//to program PLD devices (but not masked PLD devices) from Altera. Any
-//other use of such megafunction design, netlist, support information,
-//device programming or simulation file, or any other related documentation
-//or information is prohibited for any other purpose, including, but not
-//limited to modification, reverse engineering, de-compiling, or use with
-//any other silicon devices, unless such use is explicitly licensed under
-//a separate agreement with Altera or a megafunction partner. Title to the
-//intellectual property, including patents, copyrights, trademarks, trade
-//secrets, or maskworks, embodied in any such megafunction design, netlist,
-//support information, device programming or simulation file, or any other
-//related documentation or information provided by Altera or a megafunction
-//partner, remains with Altera, the megafunction partner, or their respective
-//licensors. No other licenses, including any licenses needed under any third
-//party's intellectual property, are provided herein.
-
-
-module basic80 (
- address,
- clock,
- q);
-
- input [7:0] address;
- input clock;
- output [15:0] q;
-
- wire [15:0] sub_wire0;
- wire [15:0] q = sub_wire0[15:0];
-
- altsyncram altsyncram_component (
- .clock0 (clock),
- .address_a (address),
- .q_a (sub_wire0));
- defparam
- altsyncram_component.operation_mode = "ROM",
- altsyncram_component.width_a = 16,
- altsyncram_component.widthad_a = 8,
- altsyncram_component.numwords_a = 256,
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.width_byteena_a = 1,
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.address_aclr_a = "NONE",
- altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.ram_block_type = "AUTO",
- altsyncram_component.init_file = "data/basic80.mif",
- altsyncram_component.intended_device_family = "Stratix";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGrren NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/basic80.mif"
-// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/basic80.mif"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all