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authorH. Peter Anvin <hpa@zytor.com>2016-11-01 02:58:24 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-01 03:01:17 (GMT)
commitc1d00c83383834613ec98b2af435a81ac9e673d5 (patch)
tree92ec48a304ac89b2133d8788b7ffc45babd099fb
parent03edc2bbe9e27949d9d8ba336d5eb71fadc00a3f (diff)
downloadabc80-c1d00c83383834613ec98b2af435a81ac9e673d5.zip
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WIP: adjust SRAM timing to be able to share with another device
Infrastructure for changing the SRAM timing to add another shared device (intended to be the Neopixel driver.) This means upping the SRAM state machine clock to 200 MHz; move video_clk to pll2 to be able to generate that output. It actually gets closer to proper VGA timing, but at the expense of needing a synchronizing FIFO for the fg unit. This also clears a lot of timing warnings. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.qsf326
-rw-r--r--abc80.sdc76
-rw-r--r--abc80.v216
-rw-r--r--debounce.v90
-rw-r--r--display.v50
-rw-r--r--mega/fgfifo.v177
-rw-r--r--mega/pll1.v734
-rw-r--r--mega/pll2.v654
-rw-r--r--sddisk.v36
-rw-r--r--sync.v61
10 files changed, 1414 insertions, 1006 deletions
diff --git a/abc80.qsf b/abc80.qsf
index dd7f9f7..69a2a3d 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -1,43 +1,43 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Any megafunction design, and related netlist (encrypted or decrypted),
-# support information, device programming or simulation file, and any other
-# associated documentation or information provided by Altera or a partner
-# under Altera's Megafunction Partnership Program may be used only
-# to program PLD devices (but not masked PLD devices) from Altera. Any
-# other use of such megafunction design, netlist, support information,
-# device programming or simulation file, or any other related documentation
-# or information is prohibited for any other purpose, including, but not
-# limited to modification, reverse engineering, de-compiling, or use with
-# any other silicon devices, unless such use is explicitly licensed under
-# a separate agreement with Altera or a megafunction partner. Title to the
-# intellectual property, including patents, copyrights, trademarks, trade
-# secrets, or maskworks, embodied in any such megafunction design, netlist,
-# support information, device programming or simulation file, or any other
-# related documentation or information provided by Altera or a megafunction
-# partner, remains with Altera, the megafunction partner, or their respective
-# licensors. No other licenses, including any licenses needed under any third
-# party's intellectual property, are provided herein.
-
-
-# The default values for assignments are stored in the file
-# abc80_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
+# Copyright (C) 1991-2005 Altera Corporation
+# Any megafunction design, and related netlist (encrypted or decrypted),
+# support information, device programming or simulation file, and any other
+# associated documentation or information provided by Altera or a partner
+# under Altera's Megafunction Partnership Program may be used only
+# to program PLD devices (but not masked PLD devices) from Altera. Any
+# other use of such megafunction design, netlist, support information,
+# device programming or simulation file, or any other related documentation
+# or information is prohibited for any other purpose, including, but not
+# limited to modification, reverse engineering, de-compiling, or use with
+# any other silicon devices, unless such use is explicitly licensed under
+# a separate agreement with Altera or a megafunction partner. Title to the
+# intellectual property, including patents, copyrights, trademarks, trade
+# secrets, or maskworks, embodied in any such megafunction design, netlist,
+# support information, device programming or simulation file, or any other
+# related documentation or information provided by Altera or a megafunction
+# partner, remains with Altera, the megafunction partner, or their respective
+# licensors. No other licenses, including any licenses needed under any third
+# party's intellectual property, are provided herein.
+
+
+# The default values for assignments are stored in the file
+# abc80_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+# Project-Wide Assignments
+# ========================
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 2.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:24:24 AUGUST 26, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-
-# Pin & Location Assignments
-# ==========================
+
+# Pin & Location Assignments
+# ==========================
set_location_assignment PIN_A13 -to gpio_0[0]
set_location_assignment PIN_B13 -to gpio_0[1]
set_location_assignment PIN_A14 -to gpio_0[2]
@@ -321,58 +321,58 @@ set_location_assignment PIN_V20 -to sd_clk
set_location_assignment PIN_Y20 -to sd_cmd
set_location_assignment PIN_W20 -to sd_dat0
set_location_assignment PIN_U20 -to sd_dat3
-
-# Timing Assignments
-# ==================
+
+# Timing Assignments
+# ==================
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
-
-# Analysis & Synthesis Assignments
-# ================================
+
+# Analysis & Synthesis Assignments
+# ================================
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name AUTO_ROM_RECOGNITION OFF
-set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name TOP_LEVEL_ENTITY abc80
+set_global_assignment -name TOP_LEVEL_ENTITY abc80
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
-
-# Fitter Assignments
-# ==================
+
+# Fitter Assignments
+# ==================
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
-set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS OFF
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE AUTO
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name INC_PLC_MODE OFF
set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-
-# Timing Analysis Assignments
-# ===========================
+
+# Timing Analysis Assignments
+# ===========================
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 2000
set_global_assignment -name MAX_SCC_SIZE 50
-
-# EDA Netlist Writer Assignments
-# ==============================
+
+# EDA Netlist Writer Assignments
+# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"
-
-# Assembler Assignments
-# =====================
+
+# Assembler Assignments
+# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
@@ -383,9 +383,9 @@ set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE AUTO
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
set_global_assignment -name GENERATE_HEX_FILE ON
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-
-# Design Assistant Assignments
-# ============================
+
+# Design Assistant Assignments
+# ============================
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name ASSG_CAT OFF
@@ -426,99 +426,99 @@ set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT ON
set_global_assignment -name HCPY_VREF_PINS OFF
-
-# Programmer Assignments
-# ======================
+
+# Programmer Assignments
+# ======================
set_global_assignment -name GENERATE_JAM_FILE ON
-
-# SignalTap II Assignments
-# ========================
+
+# SignalTap II Assignments
+# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
-
-# LogicLock Region Assignments
-# ============================
+
+# LogicLock Region Assignments
+# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
-
-# ------------------
-# start CLOCK(clkin)
-
- # Timing Assignments
- # ==================
-
-# end CLOCK(clkin)
-# ----------------
-
-# ----------------------
-# start CLOCK(pld_clkfb)
-
- # Timing Assignments
- # ==================
-
-# end CLOCK(pld_clkfb)
-# --------------------
-
-# -----------------------------------------
-# start EDA_TOOL_SETTINGS(eda_board_design)
-
- # EDA Netlist Writer Assignments
- # ==============================
+
+# ------------------
+# start CLOCK(clkin)
+
+ # Timing Assignments
+ # ==================
+
+# end CLOCK(clkin)
+# ----------------
+
+# ----------------------
+# start CLOCK(pld_clkfb)
+
+ # Timing Assignments
+ # ==================
+
+# end CLOCK(pld_clkfb)
+# --------------------
+
+# -----------------------------------------
+# start EDA_TOOL_SETTINGS(eda_board_design)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_board_design
-
-# end EDA_TOOL_SETTINGS(eda_board_design)
-# ---------------------------------------
-
-# ------------------------------------------------
-# start EDA_TOOL_SETTINGS(eda_formal_verification)
-
- # EDA Netlist Writer Assignments
- # ==============================
+
+# end EDA_TOOL_SETTINGS(eda_board_design)
+# ---------------------------------------
+
+# ------------------------------------------------
+# start EDA_TOOL_SETTINGS(eda_formal_verification)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_formal_verification
-
-# end EDA_TOOL_SETTINGS(eda_formal_verification)
-# ----------------------------------------------
-
-# -----------------------------------
-# start EDA_TOOL_SETTINGS(eda_palace)
-
- # EDA Netlist Writer Assignments
- # ==============================
+
+# end EDA_TOOL_SETTINGS(eda_formal_verification)
+# ----------------------------------------------
+
+# -----------------------------------
+# start EDA_TOOL_SETTINGS(eda_palace)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_palace
-
-# end EDA_TOOL_SETTINGS(eda_palace)
-# ---------------------------------
-
-# ---------------------------------------
-# start EDA_TOOL_SETTINGS(eda_simulation)
-
- # EDA Netlist Writer Assignments
- # ==============================
+
+# end EDA_TOOL_SETTINGS(eda_palace)
+# ---------------------------------
+
+# ---------------------------------------
+# start EDA_TOOL_SETTINGS(eda_simulation)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_simulation
-
-# end EDA_TOOL_SETTINGS(eda_simulation)
-# -------------------------------------
-
-# --------------------------------------------
-# start EDA_TOOL_SETTINGS(eda_timing_analysis)
-
- # EDA Netlist Writer Assignments
- # ==============================
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# --------------------------------------------
+# start EDA_TOOL_SETTINGS(eda_timing_analysis)
+
+ # EDA Netlist Writer Assignments
+ # ==============================
set_global_assignment -name EDA_GENERATE_SDF_OUTPUT_FILE ON -section_id eda_timing_analysis
-
-# end EDA_TOOL_SETTINGS(eda_timing_analysis)
-# ------------------------------------------
-
-# -------------------
-# start ENTITY(abc80)
-
- # Timing Assignments
- # ==================
-
- # Fitter Assignments
- # ==================
-
-# end ENTITY(abc80)
-# -----------------
-
+
+# end EDA_TOOL_SETTINGS(eda_timing_analysis)
+# ------------------------------------------
+
+# -------------------
+# start ENTITY(abc80)
+
+ # Timing Assignments
+ # ==================
+
+ # Fitter Assignments
+ # ==================
+
+# end ENTITY(abc80)
+# -----------------
+
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
@@ -535,16 +535,38 @@ set_instance_assignment -name CLOCK_SETTINGS clock_27 -to clock_27[1]
set_global_assignment -name FMAX_REQUIREMENT "24 MHz" -section_id clock_24
set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[0]
set_instance_assignment -name CLOCK_SETTINGS clock_24 -to clock_24[1]
-
+
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-
+
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name USE_SIGNALTAP_FILE stp6.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name PARALLEL_SYNTHESIS ON
+set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, A101, A102, A103, A104, A105, A106, A107, A108, S101, S102, S103, S104, D101, D102, D103"
+set_global_assignment -name DISABLE_DA_RULE "T101, T102, A109, A110"
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION ON
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sw
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to ext_clock
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name VERILOG_FILE mega/fgfifo.v
+set_global_assignment -name VERILOG_FILE sync.v
set_global_assignment -name VERILOG_FILE mega/bgram.v
set_global_assignment -name VERILOG_FILE enc28j60.v
set_global_assignment -name VERILOG_FILE mega/fgcolrom.v
@@ -585,4 +607,6 @@ set_global_assignment -name VERILOG_FILE hexled.v
set_global_assignment -name VERILOG_FILE hexascii.v
set_global_assignment -name VERILOG_FILE abc80.v
set_global_assignment -name SDC_FILE abc80.sdc
+
+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/abc80.sdc b/abc80.sdc
index 1ada1aa..87dcc8c 100644
--- a/abc80.sdc
+++ b/abc80.sdc
@@ -1,45 +1,31 @@
-#************************************************************
-# THIS IS A WIZARD-GENERATED FILE.
-#
-# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-#
-#************************************************************
-
-# Copyright (C) 1991-2010 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-# Clock constraints
-
-create_clock -name "clock_50" -period 20ns [get_ports {clock_50}] -waveform {0.000ns 10.000ns}
-create_clock -name "clock_24[0]" -period 41.667ns [get_ports {clock_24[0]}] -waveform {0.000ns 20.833ns}
-create_clock -name "clock_24[1]" -period 41.667ns [get_ports {clock_24[1]}] -waveform {0.000ns 20.833ns}
-create_clock -name "clock_27[0]" -period 37.037ns [get_ports {clock_27[0]}] -waveform {0.000ns 18.518ns}
-create_clock -name "clock_27[1]" -period 37.037ns [get_ports {clock_27[1]}] -waveform {0.000ns 18.518ns}
-
-
-# Automatically constrain PLL and other generated clocks
-derive_pll_clocks -create_base_clocks
-
-# Automatically calculate clock uncertainty to jitter and other effects.
-#derive_clock_uncertainty
-# Not supported for family Cyclone II
-
-# tsu/th constraints
-
-# tco constraints
-
-# tpd constraints
-
+# -*- fundamental -*-
+
+# Clock constraints
+
+create_clock -name "clock_50" -period 20ns [get_ports {clock_50}]
+create_clock -name "clock_24[0]" -period 41.667ns [get_ports {clock_24[0]}]
+create_clock -name "clock_24[1]" -period 41.667ns [get_ports {clock_24[1]}]
+create_clock -name "clock_27[0]" -period 37.037ns [get_ports {clock_27[0]}]
+create_clock -name "clock_27[1]" -period 37.037ns [get_ports {clock_27[1]}]
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks
+
+# Indicate that the clocks are independent
+set_clock_groups -asynchronous \
+ -group {clock_50 pll1|*} \
+ -group {clock_24[*] pll2|*} \
+ -group {clock_27[*]}
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+# Not supported for family Cyclone II
+#derive_clock_uncertainty
+
+# Not supported in Quartus II 13.0
+#report_metastability
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
diff --git a/abc80.v b/abc80.v
index 8629a21..b2f2acc 100644
--- a/abc80.v
+++ b/abc80.v
@@ -1,6 +1,6 @@
// -----------------------------------------------------------------------
//
-// Copyright 2003-2015 H. Peter Anvin - All Rights Reserved
+// Copyright 2003-2016 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -95,42 +95,47 @@ module abc80 (
// PLLs and clock distribution
// ------------------------------------------------------------------------
- wire cpu_clk; // 25 MHz
- wire video_clk; // 18.75 MHz = compatible screen pixel rate
- wire fast_clk; // 100 MHz
- wire audio_clk; // 16 MHz = I2S master clock
+ wire cpu_clk; // 25 MHz
+ wire video_clk; // 18.78 MHz = compatible screen pixel rate
+ wire sram_clk; // 200 MHz
+ wire fast_clk; // 100 MHz
+ wire audio_clk; // 16 MHz = I2S master clock
wire pll1_locked;
wire pll2_locked;
pll1 pll1 (
.inclk0 ( clock_50 ), // 50 MHz input clock
- .c0 ( fast_clk ), // x2/1 = 100 MHz
- .c1 ( cpu_clk ), // x1/2 = 25 MHz
- .c2 ( video_clk ), // x3/8 = 18.75 MHz
+ .c0 ( sram_clk ), // x4/1 = 200 MHz
+ .c1 ( fast_clk ), // x2/1 = 100 MHz
+ .c2 ( cpu_clk ), // x1/2 = 25 MHz
.locked ( pll1_locked )
);
pll2 pll2 (
.inclk0 ( clock_24[0] ), // 24 MHz input clock
- .c0 ( audio_clk ), // x2/3 = 16 MHz
+ .c0 ( audio_clk ), // x2/3 = 16 MHz
+ .c1 ( video_clk ), // x18/23 = 18.78 MHz
.locked ( pll2_locked )
);
// ------------------------------------------------------------------------
// Reset - synchronization and pulse stretch
// ------------------------------------------------------------------------
-`define RESET_WIDTH 6 // 2^6 = 64 cycles minimum width
- reg [`RESET_WIDTH:0] rst_ctr = 0;
- wire rst_n = rst_ctr[`RESET_WIDTH];
+ parameter reset_width = 6; // 2^6 = 64 cycles minimum width
+ reg [reset_width:0] rst_ctr = 0;
+ reg rst_n;
reg power_rst_n = 1'b0;
always @(posedge cpu_clk)
if (~key_n[2] | ~pll1_locked | ~pll2_locked) // KEY2 = CPU reset
rst_ctr <= 0;
- else if (~rst_n)
+ else if (~rst_ctr[reset_width])
rst_ctr <= rst_ctr + 1;
always @(posedge cpu_clk)
+ rst_n <= rst_ctr[reset_width];
+
+ always @(posedge cpu_clk)
power_rst_n <= 1'b1;
// ------------------------------------------------------------------------
@@ -259,43 +264,72 @@ module abc80 (
// ------------------------------------------------------------------------
reg [5:0] fgxaddr; // Byte address horizontally
- reg [8:0] fgyaddr; // Byte address vertically (bit 0 ignored)
- reg [7:0] fgdata;
- wire fgxrst;
- reg [1:0] fgxrst_q;
- wire fgyrst;
- reg [1:0] fgyrst_q;
- wire fgack;
- reg [1:0] fgack_q;
+ reg [8:0] fgyaddr; // Byte address vertically x 2 (see below)
+ reg [7:0] sram_fgdata;
+ reg sram_fgack;
+ wire fgfull;
+ wire [4:0] fgwrusedw; // FIFO fill status
+ wire [1:0] v_fgdata;
+ wire v_fgack;
+ wire fgrst;
+ wire c_fgrst;
reg [7:0] fgctl;
reg [4:0] fgpage; // Which 16K page in SRAM
- always @(posedge cpu_clk)
- fgack_q <= { fgack_q[0], fgack };
+ synchronize fgrst_sync
+ (.d(fgrst), .q(c_fgrst), .reset (~rst_n), .clk (cpu_clk));
- always @(posedge cpu_clk)
- fgxrst_q <= { fgxrst_q[0], fgxrst };
+ always @(negedge rst_n or posedge cpu_clk)
+ if ( ~rst_n )
+ begin
+ fgxaddr <= 6'd0;
+ fgyaddr <= 9'h00;
+ // fgctl and fgpage are initialized elsewhere
+ end
+ else
+ begin
+ if ( c_fgrst )
+ begin
+ fgxaddr <= 6'd0;
+ fgyaddr <= 9'd0;
+ end
+ else if ( sram_fgack )
+ begin
+ if ( fgxaddr >= 6'd60 )
+ begin
+ fgxaddr <= 6'd0;
+ fgyaddr <= fgyaddr + 1'b1;
+ end
+ else
+ fgxaddr <= fgxaddr + 1'b1;
+ end
+ end // else: !if( ~rst_n | c_fgrst )
- always @(posedge cpu_clk)
- fgyrst_q <= { fgyrst_q[0], fgyrst };
+ // fgyaddr[0] ignored due to double-scanning
+ wire [18:0] sram_fgaddr = { fgpage, fgyaddr[8:1], fgxaddr };
- always @(posedge cpu_clk)
- begin
- if (fgxrst_q[0] & ~fgxrst_q[1])
- fgxaddr <= ~6'h00; // The first ACK will advance this to 0
- else if (fgack_q[0] & ~fgack_q[1])
- fgxaddr <= fgxaddr + 1;
+ assign fgfull = &fgwrusedw[4:3]; // Max 75% full, to deal with skid
+ wire sram_fgreq = ~c_fgrst & ~fgfull;
- if (fgyrst_q[0] & ~fgyrst_q[1])
- fgyaddr <= 8'h00;
- else if (fgxrst_q[0] & ~fgxrst_q[1])
- fgyaddr <= fgyaddr + 1;
- end // always @(posedge cpu_clk)
+ // As far too many systems have done, the bit order in the fgram
+ // is bigendian, even though this is a littleendian system.
+ wire [7:0] fifo_fgdata = { sram_fgdata[1:0], sram_fgdata[3:2],
+ sram_fgdata[5:4], sram_fgdata[7:6] };
- // fgyaddr[0] ignored due to double-scanning
- wire [18:0] sram_fgaddr = { fgpage, fgyaddr[8:1], fgxaddr };
+ // FIFO to allow proper asynchronous operation
+ fgfifo fgfifo (
+ .aclr ( fgrst ),
+
+ .wrclk ( cpu_clk ),
+ .data ( fifo_fgdata ),
+ .wrreq ( sram_fgack ),
+ .wrusedw ( fgwrusedw ),
+ .wrfull ( ),
- wire sram_fgreq = fgack_q[0] & ~fgack_q[1];
+ .rdclk ( video_clk ),
+ .q ( v_fgdata ),
+ .rdreq ( v_fgack )
+ );
// ------------------------------------------------------------------------
// Video controller
@@ -370,10 +404,9 @@ module abc80 (
.hsync ( vga_hs ),
.fg_ctl ( fgctl ),
- .fg_data ( fgdata ),
- .fg_ack ( fgack ),
- .fg_xrst ( fgxrst ),
- .fg_yrst ( fgyrst )
+ .fg_data ( v_fgdata ),
+ .fg_ack ( v_fgack ),
+ .fg_rst ( fgrst )
);
// SW[4] and SW[3] can be used to emulate a green or amber monitor
@@ -389,10 +422,51 @@ module abc80 (
// The SRAM is very fast (10 ns) but is a asychronous part, so we
// generate the SRAM cycles from the fast_clk to make sure things happen
// in the right order. The SRAM is only active when actually addressed
- // by the CPU; the intent is to be able to multiplex it with a graphics
- // unit in the future.
+ // by the CPU so it can be multiplexed with other functions.
+ //
+ // Events per 100 MHz cycle, numbers correspond to fast_clk_phase:
+ //
+ // CPU read:
+ // 0. MMU address is output and CS# and OE# asserted
+ // 1. Nop
+ // 2. Latch CPU data, output mpled driver address, CS# and OE# asserted
+ // 3. Nop
+ // 0. Latch mpled data
+ //
+ // CPU write:
+ // 0. MMU address and data are output, CS# and WE# asserted
+ // 1. WE# is deasserted
+ // 2. Output mpled driver address, CS# and OE# asserted
+ // 3. Nop
+ // 0. Latch mpled data
+ //
+ // No CPU cycle:
+ // 0. Deassert CS#, OE#, WE#
+ // 1. Nop
+ // 2. Output mpled driver address, CS# and OE# asserted
+ // 3. Nop
+ // 0. Latch mpled data
+ //
// ------------------------------------------------------------------------
+ // This logic provides a counter for where sram_clk is with respect to
+ // cpu_clk. sram_clk = 0 corresponds to the rising edge of cpu_clk.
+ (* noprune *) reg [2:0] sram_clk_phase = 3'd0;
+ reg [2:0] sram_clk_next_phase = 3'd1;
+ reg last_cpu_clk = 1'b0;
+
+ always @(negedge sram_clk)
+ begin
+ last_cpu_clk <= cpu_clk;
+ if (cpu_clk & ~last_cpu_clk)
+ sram_clk_next_phase <= 3'b1;
+ else
+ sram_clk_next_phase <= sram_clk_next_phase + 3'b1;
+ end
+
+ always @(posedge sram_clk)
+ sram_clk_phase <= sram_clk_next_phase;
+
wire [7:0] sram_do; // Data out from sram
wire sram_oe_w;
wire sram_we_w;
@@ -420,8 +494,8 @@ module abc80 (
sram_we_q2 <= sram_we_q1;
end // else: !if( ~rst_n )
- // The address to drive onto the bus. This is a placeholder for
- // multiplexing with the Fine Graphics unit.
+ // The address to drive onto the bus.
+ // Multiplex the CPU with the Fine Graphics unit.
wire [18:0] sram_addr = sram_cpu ? mmu_a[18:0] : sram_fgaddr;
// Driving output pins.
@@ -438,14 +512,25 @@ module abc80 (
// SRAM Input side MUX
assign sram_do = sram_addr[0] ? sram_dq[15:8] : sram_dq[7:0];
- always @(posedge cpu_clk)
- if (sram_fgreq)
- sram_fgrd <= 1'b1;
- else if (sram_fgrd & ~sram_cpu)
+ always @(negedge rst_n or posedge cpu_clk)
+ if ( ~rst_n )
begin
- sram_fgrd <= 1'b0;
- fgdata <= sram_do;
+ sram_fgrd <= 1'b0;
+ sram_fgack <= 1'b0;
+ sram_fgdata <= 8'hxx;
end
+ else
+ begin
+ sram_fgack <= 1'b0; // Only asserted for one clock
+ sram_fgrd <= sram_fgreq;
+
+ if (sram_fgrd & ~sram_cpu)
+ begin
+ sram_fgrd <= 1'b0;
+ sram_fgdata <= sram_do;
+ sram_fgack <= 1'b1;
+ end
+ end // else: !if( ~rst_n )
// ------------------------------------------------------------------------
// External flash ROM
@@ -485,6 +570,21 @@ module abc80 (
flsh_do <= fl_dq;
// ------------------------------------------------------------------------
+ // SDRAM controller - unused, but avoid floating values
+ // ------------------------------------------------------------------------
+
+ assign dram_ba = 2'b00;
+ assign dram_ras_n = 1'b1;
+ assign dram_cas_n = 1'b1;
+ assign dram_cke = 1'b0;
+ assign dram_clk = 1'b1;
+ assign dram_cs_n = 1'b1;
+ assign dram_we_n = 1'b1;
+ assign dram_dqm = 2'b11;
+ assign dram_a = ~18'b0;
+ assign dram_dq = ~16'b0;
+
+ // ------------------------------------------------------------------------
// BASIC patching ROM for 80-column mode
// ------------------------------------------------------------------------
@@ -792,6 +892,7 @@ module abc80 (
// The ENC28J60 module is attached to GPIO1 signals 26-33, corresponding
// to pins 29-38 (including power). This is dictated by VCC33 and GND
// on pins 29-30 corresponding to the MOD-ENC28J60 pins 1-2.
+ assign gpio_1[25:0] = 26'bz;
assign gpio_1[26] = 1'bz; // Optional connection to LEDA
assign gpio_1[27] = 1'bz;
assign eth_wol_n = gpio_1[27];
@@ -803,6 +904,7 @@ module abc80 (
assign gpio_1[31] = eth_mosi;
assign gpio_1[32] = eth_sck;
assign gpio_1[33] = eth_cs_n;
+ assign gpio_1[35:34] = 2'bz;
// The terminology gets a bit funny there. abc_do means data from
// the ABC-bus to the main CPU.
@@ -827,7 +929,7 @@ module abc80 (
.strobe ( key1_strobe )
);
- always @(negedge rst_n or posedge cpu_clk)
+ always @(posedge cpu_clk)
begin
if ( ~rst_n )
video_width <= ~sw[9]; // Set SW9 to go to 40 column after reset
@@ -839,6 +941,8 @@ module abc80 (
video_width <= 1'b1;
else if ( key1_strobe & key1_debounced )
video_width <= ~video_width;
+ else
+ video_width <= video_width; // Help for Quartus
end
end
diff --git a/debounce.v b/debounce.v
index b9d4877..16894c4 100644
--- a/debounce.v
+++ b/debounce.v
@@ -5,47 +5,65 @@ module debounce (
out,
strobe
);
+ // This is optimized for a 25 MHz clock and the
+ // assumption that glitches are limited to ~2 ms
+ parameter ctrbits = 16;
+
+ parameter width = 1;
+
input clk;
input reset_n;
- input in;
- output out;
+ input [width-1:0] in;
+ output [width-1:0] out;
output strobe;
- // This is optimized for a 25 MHz clock and the
- // assumption that glitches are limited to ~2 ms
+ reg [width-1:0] out;
+ reg [width-1:0] strobes;
+ reg [ctrbits-1:0] ctr [0:width-1];
- reg out;
- reg out1;
- reg [15:0] ctr;
-
- assign strobe = out ^ out1;
-
- always @(negedge reset_n or posedge clk)
- if ( ~reset_n )
- begin
- out <= 0;
- out1 <= 0;
- ctr <= 0;
- end
- else
- begin
- out1 <= out;
-
- if ( in )
- begin
- if ( ctr == 16'hFFFF )
- out <= 1;
- else
- ctr <= ctr + 1;
- end
- else
- begin
- if ( ctr == 16'h0000 )
- out <= 0;
+ assign strobe = |strobes;
+
+ wire [width-1:0] in_q;
+
+ synchronize #(.width(width))
+ debounce_sync (.reset(~reset_n), .clk(clk), .d(in), .q(in_q));
+
+ genvar i;
+ generate
+ for (i = 0; i < width; i = i + 1)
+ begin: gen_debounce
+ always @(negedge reset_n or posedge clk)
+ if ( ~reset_n )
+ begin
+ out[i] <= 1'b0;
+ strobes[i] <= 1'b0;
+ ctr[i] <= {1'b0, {ctrbits-1{1'b0}}};
+ end
else
- ctr <= ctr - 1;
- end
- end // else: !if( ~reset_n )
+ begin
+ strobes[i] <= 1'b0;
+ if ( in_q[i] )
+ begin
+ if ( &ctr[i] )
+ begin
+ out[i] <= 1'b1;
+ strobes[i] <= 1'b1;
+ end
+ else
+ ctr[i] <= ctr[i] + 1'b1;
+ end
+ else
+ begin
+ if ( ~|ctr[i] )
+ begin
+ out[i] <= 1'b0;
+ strobes[i] <= 1'b1;
+ end
+ else
+ ctr[i] <= ctr[i] - 1'b1;
+ end // else: !if( in[i] )
+ end // else: !if( ~reset_n )
+ end // block: gen_debounce
+ endgenerate
endmodule // debounce
- \ No newline at end of file
diff --git a/display.v b/display.v
index 68c5be0..8e539d4 100644
--- a/display.v
+++ b/display.v
@@ -1,12 +1,11 @@
module display (
- input clk, // 18.75 MHz
+ input clk, // 18.78 MHz
input width,
input reverse,
input noblink,
input testpattern,
input reveal,
-
output reg [10:0] a,
input [7:0] d,
output [10:0] ga,
@@ -19,16 +18,15 @@ module display (
output hsync,
input [7:0] fg_ctl,
- input [7:0] fg_data,
+ input [1:0] fg_data,
output fg_ack,
- output fg_xrst,
- output fg_yrst
+ output fg_rst
);
// We use the standard VGA 640x480 monitor timings mode, htime = 31.77
// us (31.47 kHz), vtime = 16.68 ms (60 Hz) The standard VGA uses a
-// pixel clock of 25.175 MHz, we use 18.75 MHz, which is 25*3/4 for
-// 480 horizontal pixels; the error is about 0.8%, which is far, far
+// pixel clock of 25.175 MHz, we use 18.783 MHz, which is 25*3/4 for
+// 480 horizontal pixels; the error is about 0.6%, which is far, far
// less than the margin of error in real systems.
//
// This gives us the following timings:
@@ -74,6 +72,8 @@ module display (
parameter hsync_minus = 1'b1; // -hsync
parameter vsync_minus = 1'b1; // -vsync
+ wire v_width; // Synchronized width
+
reg hsync_q; // Horizontal sync active
reg vsync_q; // Vertical sync active
@@ -97,8 +97,9 @@ module display (
reg prefetch; // True for the prefetch character position
// Fine Graphics control
+ wire [7:0] v_fgctl; // Synchronized version of fg_ctl
reg [7:0] fgctl_q; // Latched version of fg_ctl
- reg [7:0] fgpixels; // One byte of fg pixels
+ reg [1:0] fgpixels; // One fg pixel from FIFO
// Block graphics data
reg [5:0] block_rgb; // Current block graphics pixel
@@ -137,10 +138,18 @@ module display (
wire do_flsh = wasdble ? wasflsh : isflsh;
wire do_hide = wasdble ? washide : ishide;
+ // Synchronize width input
+ synchronize
+ width_sync (.reset(1'b0), .clk(clk), .d(width), .q(v_width));
+
+ // Synchronize fg_ctl input
+ synchronize #(.width(8))
+ fg_ctl_sync (.reset(1'b0), .clk(clk), .d(fg_ctl), .q(v_fgctl));
+
// Should we advance the character pixel?
// We need to always advance at full speed during prefetch, or
// we would have to start the prefetch earlier in 40-character mode.
- wire advance = width | x[0] | prefetch;
+ wire advance = v_width | x[0] | prefetch;
// Address mapping for 40 and 80 characters
assign a80[3:0] = xchr[3:0];
@@ -168,7 +177,7 @@ module display (
// Note: We read the current char between pixels 0 and 1,
// and the char above between pixels 2 and 3; hence the use of xpxl[1].
always @(*)
- case ( { width, xpxl[1] } )
+ case ( { v_width, xpxl[1] } )
2'b00:
a = a40;
2'b01:
@@ -177,7 +186,7 @@ module display (
a = a80;
2'b11:
a = a80u;
- endcase // case( { width, xchr[1] } )
+ endcase // case( { v_width, xchr[1] } )
// Block graphics address mapping
assign bga[3:0] = block_x[3:0];
@@ -196,8 +205,9 @@ module display (
assign xvideo = ( x < x_blank );
assign yvideo = ( y < y_blank );
- assign hsync = hsync_q ^ hsync_minus;
- assign vsync = vsync_q ^ vsync_minus;
+ assign hsync = hsync_q ^ hsync_minus;
+ assign vsync = vsync_q ^ vsync_minus;
+ assign fg_rst = vsync;
// Flashing
wire flash_on = scan_counter[4];
@@ -210,24 +220,20 @@ module display (
//
// Fine graphics
//
- assign fg_ack = xvideo & yvideo & (x[2:0] == 3'b000);
- assign fg_xrst = yvideo & hsync_q;
- assign fg_yrst = vsync_q;
+ assign fg_ack = xvideo & yvideo & ~x[0];
wire [3:0] fg_argb;
always @(posedge clk)
if ( ~yvideo ) // Only change mode during vertical blank
- fgctl_q <= fg_ctl;
+ fgctl_q <= v_fgctl;
always @(posedge clk)
- if (x[2:0] == 3'b100)
+ if (~x[0])
fgpixels <= fg_data;
- else if (~x[0])
- fgpixels <= { fgpixels[5:0], 2'bxx };
fgcolrom fgcolrom (
- .address ( { fgctl_q[6:0], fgpixels[7:6] } ),
+ .address ( { fgctl_q[6:0], fgpixels } ),
.clock ( clk ),
.q ( fg_argb )
);
@@ -262,7 +268,7 @@ module display (
if ( advance )
pixrow <= { pixrow[4:0], pixrow[5] };
- // This code is run 6 times per character; regardless of width
+ // This code is run 6 times per character; regardless of v_width
if ( advance )
begin
case ( xpxl )
diff --git a/mega/fgfifo.v b/mega/fgfifo.v
new file mode 100644
index 0000000..63549bb
--- /dev/null
+++ b/mega/fgfifo.v
@@ -0,0 +1,177 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo_mixed_widths
+
+// ============================================================
+// File Name: fgfifo.v
+// Megafunction Name(s):
+// dcfifo_mixed_widths
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fgfifo (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ wrusedw);
+
+ input aclr;
+ input [7:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [1:0] q;
+ output [4:0] wrusedw;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 aclr;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [1:0] sub_wire0;
+ wire [4:0] sub_wire1;
+ wire [1:0] q = sub_wire0[1:0];
+ wire [4:0] wrusedw = sub_wire1[4:0];
+
+ dcfifo_mixed_widths dcfifo_mixed_widths_component (
+ .aclr (aclr),
+ .data (data),
+ .rdclk (rdclk),
+ .rdreq (rdreq),
+ .wrclk (wrclk),
+ .wrreq (wrreq),
+ .q (sub_wire0),
+ .wrusedw (sub_wire1),
+ .rdempty (),
+ .rdfull (),
+ .rdusedw (),
+ .wrempty (),
+ .wrfull ());
+ defparam
+ dcfifo_mixed_widths_component.intended_device_family = "Cyclone II",
+ dcfifo_mixed_widths_component.lpm_hint = "MAXIMIZE_SPEED=5,",
+ dcfifo_mixed_widths_component.lpm_numwords = 32,
+ dcfifo_mixed_widths_component.lpm_showahead = "ON",
+ dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
+ dcfifo_mixed_widths_component.lpm_width = 8,
+ dcfifo_mixed_widths_component.lpm_widthu = 5,
+ dcfifo_mixed_widths_component.lpm_widthu_r = 7,
+ dcfifo_mixed_widths_component.lpm_width_r = 2,
+ dcfifo_mixed_widths_component.overflow_checking = "ON",
+ dcfifo_mixed_widths_component.rdsync_delaypipe = 5,
+ dcfifo_mixed_widths_component.underflow_checking = "ON",
+ dcfifo_mixed_widths_component.use_eab = "ON",
+ dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
+ dcfifo_mixed_widths_component.wrsync_delaypipe = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "32"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "2"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7"
+// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "2"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL "wrusedw[4..0]"
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
+// Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fgfifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll1.v b/mega/pll1.v
index b21c3d0..a2bc288 100644
--- a/mega/pll1.v
+++ b/mega/pll1.v
@@ -1,366 +1,368 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll1.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2009 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll1 (
- inclk0,
- c0,
- c1,
- c2,
- locked);
-
- input inclk0;
- output c0;
- output c1;
- output c2;
- output locked;
-
- wire [5:0] sub_wire0;
- wire sub_wire4;
- wire [0:0] sub_wire7 = 1'h0;
- wire [2:2] sub_wire3 = sub_wire0[2:2];
- wire [1:1] sub_wire2 = sub_wire0[1:1];
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire c1 = sub_wire2;
- wire c2 = sub_wire3;
- wire locked = sub_wire4;
- wire sub_wire5 = inclk0;
- wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
-
- altpll altpll_component (
- .inclk (sub_wire6),
- .clk (sub_wire0),
- .locked (sub_wire4),
- .activeclock (),
- .areset (1'b0),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.clk0_divide_by = 1,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 2,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 2,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 1,
- altpll_component.clk1_phase_shift = "0",
- altpll_component.clk2_divide_by = 8,
- altpll_component.clk2_duty_cycle = 50,
- altpll_component.clk2_multiply_by = 3,
- altpll_component.clk2_phase_shift = "0",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.gate_lock_counter = 8192,
- altpll_component.gate_lock_signal = "YES",
- altpll_component.inclk0_input_frequency = 20000,
- altpll_component.intended_device_family = "Cyclone II",
- altpll_component.invalid_lock_multiplier = 5,
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_UNUSED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_USED",
- altpll_component.port_clk2 = "PORT_USED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.valid_lock_multiplier = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "8"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "18.750000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "8192"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "3"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "18.75000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "8"
-// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "3"
-// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "8192"
-// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll1.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll1 (
+ inclk0,
+ c0,
+ c1,
+ c2,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output c2;
+ output locked;
+
+ wire [5:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [2:2] sub_wire4 = sub_wire0[2:2];
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire c2 = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
+
+ altpll altpll_component (
+ .inclk (sub_wire6),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 1,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 4,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 1,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.clk2_divide_by = 2,
+ altpll_component.clk2_duty_cycle = 50,
+ altpll_component.clk2_multiply_by = 1,
+ altpll_component.clk2_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.gate_lock_counter = 8192,
+ altpll_component.gate_lock_signal = "YES",
+ altpll_component.inclk0_input_frequency = 20000,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_USED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "2"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "8192"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll1.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "8192"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll2.v b/mega/pll2.v
index d4a55d7..fed73d9 100644
--- a/mega/pll2.v
+++ b/mega/pll2.v
@@ -1,312 +1,342 @@
-// megafunction wizard: %ALTPLL%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altpll
-
-// ============================================================
-// File Name: pll2.v
-// Megafunction Name(s):
-// altpll
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2009 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module pll2 (
- inclk0,
- c0,
- locked);
-
- input inclk0;
- output c0;
- output locked;
-
- wire [5:0] sub_wire0;
- wire sub_wire2;
- wire [0:0] sub_wire5 = 1'h0;
- wire [0:0] sub_wire1 = sub_wire0[0:0];
- wire c0 = sub_wire1;
- wire locked = sub_wire2;
- wire sub_wire3 = inclk0;
- wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
-
- altpll altpll_component (
- .inclk (sub_wire4),
- .clk (sub_wire0),
- .locked (sub_wire2),
- .activeclock (),
- .areset (1'b0),
- .clkbad (),
- .clkena ({6{1'b1}}),
- .clkloss (),
- .clkswitch (1'b0),
- .configupdate (1'b0),
- .enable0 (),
- .enable1 (),
- .extclk (),
- .extclkena ({4{1'b1}}),
- .fbin (1'b1),
- .fbmimicbidir (),
- .fbout (),
- .pfdena (1'b1),
- .phasecounterselect ({4{1'b1}}),
- .phasedone (),
- .phasestep (1'b1),
- .phaseupdown (1'b1),
- .pllena (1'b1),
- .scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
- .scanread (1'b0),
- .scanwrite (1'b0),
- .sclkout0 (),
- .sclkout1 (),
- .vcooverrange (),
- .vcounderrange ());
- defparam
- altpll_component.clk0_divide_by = 3,
- altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 2,
- altpll_component.clk0_phase_shift = "0",
- altpll_component.compensate_clock = "CLK0",
- altpll_component.gate_lock_counter = 4096,
- altpll_component.gate_lock_signal = "YES",
- altpll_component.inclk0_input_frequency = 41666,
- altpll_component.intended_device_family = "Cyclone II",
- altpll_component.invalid_lock_multiplier = 5,
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
- altpll_component.lpm_type = "altpll",
- altpll_component.operation_mode = "NORMAL",
- altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_UNUSED",
- altpll_component.port_clkbad0 = "PORT_UNUSED",
- altpll_component.port_clkbad1 = "PORT_UNUSED",
- altpll_component.port_clkloss = "PORT_UNUSED",
- altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
- altpll_component.port_fbin = "PORT_UNUSED",
- altpll_component.port_inclk0 = "PORT_USED",
- altpll_component.port_inclk1 = "PORT_UNUSED",
- altpll_component.port_locked = "PORT_USED",
- altpll_component.port_pfdena = "PORT_UNUSED",
- altpll_component.port_phasecounterselect = "PORT_UNUSED",
- altpll_component.port_phasedone = "PORT_UNUSED",
- altpll_component.port_phasestep = "PORT_UNUSED",
- altpll_component.port_phaseupdown = "PORT_UNUSED",
- altpll_component.port_pllena = "PORT_UNUSED",
- altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
- altpll_component.port_scanread = "PORT_UNUSED",
- altpll_component.port_scanwrite = "PORT_UNUSED",
- altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_UNUSED",
- altpll_component.port_clk2 = "PORT_UNUSED",
- altpll_component.port_clk3 = "PORT_UNUSED",
- altpll_component.port_clk4 = "PORT_UNUSED",
- altpll_component.port_clk5 = "PORT_UNUSED",
- altpll_component.port_clkena0 = "PORT_UNUSED",
- altpll_component.port_clkena1 = "PORT_UNUSED",
- altpll_component.port_clkena2 = "PORT_UNUSED",
- altpll_component.port_clkena3 = "PORT_UNUSED",
- altpll_component.port_clkena4 = "PORT_UNUSED",
- altpll_component.port_clkena5 = "PORT_UNUSED",
- altpll_component.port_extclk0 = "PORT_UNUSED",
- altpll_component.port_extclk1 = "PORT_UNUSED",
- altpll_component.port_extclk2 = "PORT_UNUSED",
- altpll_component.port_extclk3 = "PORT_UNUSED",
- altpll_component.valid_lock_multiplier = 1;
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
-// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
-// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "4096"
-// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
-// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "312.000"
-// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "4096"
-// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
-// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
-// Retrieval info: CBX_MODULE_PREFIX: ON
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll
+
+// ============================================================
+// File Name: pll2.v
+// Megafunction Name(s):
+// altpll
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll2 (
+ inclk0,
+ c0,
+ c1,
+ locked);
+
+ input inclk0;
+ output c0;
+ output c1;
+ output locked;
+
+ wire [5:0] sub_wire0;
+ wire sub_wire2;
+ wire [0:0] sub_wire6 = 1'h0;
+ wire [0:0] sub_wire3 = sub_wire0[0:0];
+ wire [1:1] sub_wire1 = sub_wire0[1:1];
+ wire c1 = sub_wire1;
+ wire locked = sub_wire2;
+ wire c0 = sub_wire3;
+ wire sub_wire4 = inclk0;
+ wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+ altpll altpll_component (
+ .inclk (sub_wire5),
+ .clk (sub_wire0),
+ .locked (sub_wire2),
+ .activeclock (),
+ .areset (1'b0),
+ .clkbad (),
+ .clkena ({6{1'b1}}),
+ .clkloss (),
+ .clkswitch (1'b0),
+ .configupdate (1'b0),
+ .enable0 (),
+ .enable1 (),
+ .extclk (),
+ .extclkena ({4{1'b1}}),
+ .fbin (1'b1),
+ .fbmimicbidir (),
+ .fbout (),
+ .fref (),
+ .icdrclk (),
+ .pfdena (1'b1),
+ .phasecounterselect ({4{1'b1}}),
+ .phasedone (),
+ .phasestep (1'b1),
+ .phaseupdown (1'b1),
+ .pllena (1'b1),
+ .scanaclr (1'b0),
+ .scanclk (1'b0),
+ .scanclkena (1'b1),
+ .scandata (1'b0),
+ .scandataout (),
+ .scandone (),
+ .scanread (1'b0),
+ .scanwrite (1'b0),
+ .sclkout0 (),
+ .sclkout1 (),
+ .vcooverrange (),
+ .vcounderrange ());
+ defparam
+ altpll_component.clk0_divide_by = 3,
+ altpll_component.clk0_duty_cycle = 50,
+ altpll_component.clk0_multiply_by = 2,
+ altpll_component.clk0_phase_shift = "0",
+ altpll_component.clk1_divide_by = 23,
+ altpll_component.clk1_duty_cycle = 50,
+ altpll_component.clk1_multiply_by = 18,
+ altpll_component.clk1_phase_shift = "0",
+ altpll_component.compensate_clock = "CLK0",
+ altpll_component.gate_lock_counter = 4096,
+ altpll_component.gate_lock_signal = "YES",
+ altpll_component.inclk0_input_frequency = 41666,
+ altpll_component.intended_device_family = "Cyclone II",
+ altpll_component.invalid_lock_multiplier = 5,
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
+ altpll_component.lpm_type = "altpll",
+ altpll_component.operation_mode = "NORMAL",
+ altpll_component.port_activeclock = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_clkbad0 = "PORT_UNUSED",
+ altpll_component.port_clkbad1 = "PORT_UNUSED",
+ altpll_component.port_clkloss = "PORT_UNUSED",
+ altpll_component.port_clkswitch = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_fbin = "PORT_UNUSED",
+ altpll_component.port_inclk0 = "PORT_USED",
+ altpll_component.port_inclk1 = "PORT_UNUSED",
+ altpll_component.port_locked = "PORT_USED",
+ altpll_component.port_pfdena = "PORT_UNUSED",
+ altpll_component.port_phasecounterselect = "PORT_UNUSED",
+ altpll_component.port_phasedone = "PORT_UNUSED",
+ altpll_component.port_phasestep = "PORT_UNUSED",
+ altpll_component.port_phaseupdown = "PORT_UNUSED",
+ altpll_component.port_pllena = "PORT_UNUSED",
+ altpll_component.port_scanaclr = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_UNUSED",
+ altpll_component.port_scanclkena = "PORT_UNUSED",
+ altpll_component.port_scandata = "PORT_UNUSED",
+ altpll_component.port_scandataout = "PORT_UNUSED",
+ altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanread = "PORT_UNUSED",
+ altpll_component.port_scanwrite = "PORT_UNUSED",
+ altpll_component.port_clk0 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk2 = "PORT_UNUSED",
+ altpll_component.port_clk3 = "PORT_UNUSED",
+ altpll_component.port_clk4 = "PORT_UNUSED",
+ altpll_component.port_clk5 = "PORT_UNUSED",
+ altpll_component.port_clkena0 = "PORT_UNUSED",
+ altpll_component.port_clkena1 = "PORT_UNUSED",
+ altpll_component.port_clkena2 = "PORT_UNUSED",
+ altpll_component.port_clkena3 = "PORT_UNUSED",
+ altpll_component.port_clkena4 = "PORT_UNUSED",
+ altpll_component.port_clkena5 = "PORT_UNUSED",
+ altpll_component.port_extclk0 = "PORT_UNUSED",
+ altpll_component.port_extclk1 = "PORT_UNUSED",
+ altpll_component.port_extclk2 = "PORT_UNUSED",
+ altpll_component.port_extclk3 = "PORT_UNUSED",
+ altpll_component.valid_lock_multiplier = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "23"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "16.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.782608"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "4096"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "18"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "16.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.88125000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll2.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "23"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "18"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "4096"
+// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_wave*.jpg FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/sddisk.v b/sddisk.v
index 0e4d43e..aeccb2c 100644
--- a/sddisk.v
+++ b/sddisk.v
@@ -84,25 +84,25 @@ module sdcontroller(
// ------------------------------------------------------------------------
reg ireset;
- always @(negedge reset_n or posedge clk)
+ always @(posedge clk)
begin
if ( ~reset_n )
begin
- ireset <= 1;
- selected <= 0;
+ ireset <= 1'b1;
+ selected <= 1'b0;
end
else // clock
begin
- ireset <= 0;
+ ireset <= 1'b0;
if ( ~abc_rst_n )
begin
- ireset <= 1;
- selected <= 0;
+ ireset <= 1'b1;
+ selected <= 1'b0;
end
else
begin
if ( selected & ~abc_c3_n )
- ireset <= 1;
+ ireset <= 1'b1;
if ( ~abc_cs_n )
selected <= (abc_do[5:0] == selectcode);
@@ -145,7 +145,7 @@ module sdcontroller(
// C1# from the ABC bus generates interrupt; this is used to
// reset the controller state machine to the command state.
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
begin
if ( ireset )
cpu_int_n <= 1'b1;
@@ -158,7 +158,7 @@ module sdcontroller(
// Generate NMI if we do an I/O operation without A7 set,
// and the card is not present.
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
begin
if ( ireset )
cpu_nmi_n <= 1'b1;
@@ -244,7 +244,7 @@ module sdcontroller(
abc_di = 8'hFF;
end // always @ (*)
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
begin
if ( ireset )
begin
@@ -389,7 +389,7 @@ module sdcontroller(
// sd_cmd_ok: 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0
// cpu_wait_n: 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
if (ireset)
sd_cmd_ok <= 1'b0;
else
@@ -412,13 +412,13 @@ module sdcontroller(
assign sd_clk_pos = sd_active & ctr_val & ctr_pol;
assign sd_clk_neg = sd_active_neg & ctr_val & ~ctr_pol;
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
if (ireset)
sd_clk_out <= 1'b0;
else
sd_clk_out <= (sd_clk_out | sd_clk_pos) & ~sd_clk_neg;
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
if (ireset)
begin
sd_shr_out <= 8'hFF;
@@ -520,20 +520,20 @@ module sdcontroller(
// ------------------------------------------------------------------------
// Output LEDs
// ------------------------------------------------------------------------
-`define ACTIVE_TIME 21 // 2^21 cycles @ 25 MHz ~ 84 ms
+ parameter active_time = 21; // 2^21 cycles @ 25 MHz ~ 84 ms
- reg [`ACTIVE_TIME:0] active_delay;
+ reg [active_time:0] active_delay;
assign select = selected; // For external LED, might need hysteresis
- always @(posedge ireset or posedge clk)
+ always @(posedge clk)
if ( ireset )
active_delay <= ~0;
else if ( sd_active )
active_delay <= 0;
- else if ( ~active_delay[`ACTIVE_TIME] )
+ else if ( ~active_delay[active_time] )
active_delay <= active_delay + 1;
- assign active = ~active_delay[`ACTIVE_TIME];
+ assign active = ~active_delay[active_time];
endmodule // cfcontroller
diff --git a/sync.v b/sync.v
new file mode 100644
index 0000000..b1f3077
--- /dev/null
+++ b/sync.v
@@ -0,0 +1,61 @@
+// -----------------------------------------------------------------------
+//
+// Copyright 2016 H. Peter Anvin - All Rights Reserved
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor,
+// Boston MA 02110-1301, USA; either version 2 of the License, or
+// (at your option) any later version; incorporated herein by reference.
+//
+// -----------------------------------------------------------------------
+
+//
+// Synchronize data from different clock domains. This is pretty trivial
+// stuff in theory; most of the complexity comes from giving hints
+// to the synthesizer. Good reason to make this a parameterized module.
+//
+
+(* altera_attribute = "-name synchronizer_identification forced_if_asynchronous; -name auto_shift_register_recognition off; -name global_signal off" *)
+module synchronize(reset, clk, d, q);
+ parameter width = 1; // Minimum 1
+ parameter stages = 2; // Minimum 2
+
+ input reset;
+ input clk;
+ input [width-1:0] d;
+ output [width-1:0] q;
+
+ // Inputs to these modules are inherently asynchronous
+ (* altera_attribute = "-name cut on -from * ; -name sdc_statement \"set_false_path -to [get_keepers {synchronize:*|d_q[*] *|synchronize:*|d_q[*]}]\"" *)
+ reg [width-1:0] d_q;
+
+ reg [width-1:0] stage[1:stages-1];
+
+ assign q = stage[stages-1];
+
+ always @(posedge reset or posedge clk)
+ if (reset)
+ d_q <= {width{1'b0}};
+ else
+ d_q <= d;
+
+ always @(posedge reset or posedge clk)
+ if (reset)
+ stage[1] <= {width{1'b0}};
+ else
+ stage[1] <= d_q;
+
+ genvar i;
+
+ generate
+ for (i = 2; i < stages; i = i + 1)
+ begin: gen_stages
+ always @(posedge reset or posedge clk)
+ if (reset)
+ stage[i] <= {width{1'b0}};
+ else
+ stage[i] <= stage[i-1];
+ end
+ endgenerate
+endmodule