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authorH. Peter Anvin <hpa@zytor.com>2016-11-09 00:04:46 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-09 00:04:46 (GMT)
commitbf72deac95fd4fe0d996ebab7454ae3118a27d68 (patch)
treecd4acee634d94d13a40a37a8a8d748abdf3012cd
parentd0f9ec8780bfbb5ae1588e2c1e63bab7e38e8b8b (diff)
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Current status of SRAM sharing
-rw-r--r--abc80.qsf14
-rw-r--r--abc80.sdc18
-rw-r--r--abc80.v153
-rw-r--r--debounce.v3
-rw-r--r--display.v7
-rw-r--r--mega/mmuram.v476
-rw-r--r--mega/pll1.v12
7 files changed, 365 insertions, 318 deletions
diff --git a/abc80.qsf b/abc80.qsf
index 69a2a3d..11aaae5 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -365,7 +365,7 @@ set_global_assignment -name MAX_SCC_SIZE 50
# EDA Netlist Writer Assignments
# ==============================
-set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
@@ -557,7 +557,6 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL OFF
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to clock_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to sw
@@ -609,4 +608,13 @@ set_global_assignment -name VERILOG_FILE abc80.v
set_global_assignment -name SDC_FILE abc80.sdc
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SOURCE_FILE db/abc80.cmp.rdb
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation \ No newline at end of file
diff --git a/abc80.sdc b/abc80.sdc
index 87dcc8c..64844e9 100644
--- a/abc80.sdc
+++ b/abc80.sdc
@@ -17,6 +17,24 @@ set_clock_groups -asynchronous \
-group {clock_24[*] pll2|*} \
-group {clock_27[*]}
+set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[2]}] 7
+set_multicycle_path -start -from [get_keepers {mmuram:mmu|*porta*}] -to [get_clocks {pll1|*|clk[1]}] 3
+set_multicycle_path -from [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] -to [get_keepers {mmuram:mmu|*portb*}] 2
+set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[2]}] 6
+set_multicycle_path -start -from [get_keepers {mmuram:mmu|*portb*}] -to [get_clocks {pll1|*|clk[1]}] 2
+set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[2]}] 6
+set_multicycle_path -start -from [get_keepers {msel[*]}] -to [get_clocks {pll1|*|clk[1]}] 2
+set_multicycle_path -from [get_clocks {pll1|*|clk[2]}] -to [get_keepers {sram_*_q*}] 2
+set_multicycle_path -start -from [get_keepers {sram_do*}] -to [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] 2
+
+# I/O pin constraints
+set_input_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_dq[*]}]
+set_input_delay -clock {pll1|*|clk[0]} -max 3ns [get_ports {sram_dq[*]}]
+# These numbers are a bit tricky, they appear to be relative to the *next*
+# edge of the clock, so -max -1ns refer to a 6ns clock-to-pad delay.
+set_output_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_*}]
+set_output_delay -clock {pll1|*|clk[0]} -max -1ns [get_ports {sram_*}]
+
# Automatically calculate clock uncertainty to jitter and other effects.
# Not supported for family Cyclone II
#derive_clock_uncertainty
diff --git a/abc80.v b/abc80.v
index 2896498..65f2535 100644
--- a/abc80.v
+++ b/abc80.v
@@ -277,7 +277,8 @@ module abc80 (
reg [4:0] fgpage; // Which 16K page in SRAM
synchronize fgrst_sync
- (.d(fgrst), .q(c_fgrst), .reset (~rst_n), .clk (cpu_clk));
+ (.d(fgrst), .q(c_fgrst),
+ .reset (~rst_n), .clk (cpu_clk), .enable(1'b1));
always @(negedge rst_n or posedge cpu_clk)
if ( ~rst_n )
@@ -425,37 +426,50 @@ module abc80 (
// actually addressed by the CPU so it can be multiplexed with
// other functions.
//
+ // Timing budget for read:
+ // 10 ns - input address
+ // 3 ns - output register to pad
+ // 1 ns - PCB propagation delay
+ // 10 ns - SRAM latency
+ // ? ns - propagation delay
+ // ? ns - pad to input register
+ // 10 ns - output data
+ //
// Events per 25 MHz CPU cycle, numbers correspond to sram_clk_phase:
//
// CPU or fgfifo read:
- // 0. MMU/fgfifo address is output and CE# and OE# asserted
- // 1. Nop
- // 2. Nop
- // 3. Latch CPU/fgfifo data
- // 4. Output npled driver address, CE# and OE# asserted
+ // 2. Latch npled data, output MMU/fgfifo address,
+ // CE# and OE# asserted
+ // 3. Nop
+ // 4. Nop
// 5. Nop
- // 6. Nop
- // 7. Latch npled data
+ // 6. Latch CPU/fgfifo data, output npled driver address,
+ // CE# and OE# asserted
+ // 7. Nop
+ // 0. Nop
+ // 1. Nop
//
// CPU write:
- // 0. MMU address and data are output, CE# and WE# asserted
+ // 2. Latch npled data, output MMU address and CPU data,
+ // CE# and WE# asserted
+ // 3. Nop
+ // 4. Nop
+ // 5. Deassert WE#
+ // 6. Output npled driver address,
+ // CE# and OE# asserted
+ // 7. Nop
+ // 0. Nop
// 1. Nop
- // 2. Nop
- // 3. WE# deasserted
- // 4. Output npled driver address, CE# and OE# asserted
- // 5. Nop
- // 6. Nop
- // 7. Latch npled data
//
// No CPU/fgfifo cycle:
- // 0. Deassert CE#, OE#, WE#
- // 1. Nop
- // 2. Nop
+ // 2. Latch npled data, CE#, WE# and OE# deasserted
// 3. Nop
- // 4. Output npled driver address, CE# and OE# asserted
+ // 4. Nop
// 5. Nop
- // 6. Nop
- // 7. Latch npled data
+ // 6. Output npled driver address, CE# and OE# asserted
+ // 7. Nop
+ // 0. Nop
+ // 1. Nop
//
// ------------------------------------------------------------------------
@@ -471,7 +485,8 @@ module abc80 (
begin
last_cpu_clk <= cpu_clk;
if (cpu_clk & ~last_cpu_clk)
- sram_clk_next_phase <= 3'd1;
+ // 1 cycle observation latency, 1 cycle latch latency
+ sram_clk_next_phase <= 3'd2;
else
sram_clk_next_phase <= sram_clk_next_phase + 1'b1;
end
@@ -486,7 +501,8 @@ module abc80 (
reg sram_oe_q;
reg sram_we_q;
reg sram_fgrd;
- reg [18:0] sram_addr;
+ reg [18:0] sram_addr_q;
+ reg [7:0] sram_d_q; // Output data (from write)
// Are we actually accessed by the CPU?
wire sram_cpu = msel[0] & cpu_clk_en;
@@ -497,62 +513,64 @@ module abc80 (
always @(negedge rst_n or posedge sram_clk)
if ( ~rst_n )
begin
- sram_ce_q <= 1'b0;
- sram_oe_q <= 1'b0;
- sram_we_q <= 1'b0;
- sram_fg_q <= 1'b0;
- sram_addr <= 19'bx;
- sram_do <= 8'bx;
- npled_do <= 8'bx;
+ sram_ce_q <= 1'b0;
+ sram_oe_q <= 1'b0;
+ sram_we_q <= 1'b0;
+ sram_fg_q <= 1'b0;
+ sram_addr_q <= 19'bx;
+ sram_d_q <= 8'bx;
+ sram_do <= 8'bx;
+ npled_do <= 8'bx;
end // if ( ~rst_n )
else
begin
case (sram_clk_phase)
- 3'd0:
+ 3'd2:
begin
npled_do <= sram_q;
- sram_do <= 8'bx;
if (sram_cpu)
begin
- sram_ce_q <= 1'b1;
- sram_we_q <= ~cpu_wr_n;
- sram_oe_q <= ~cpu_rd_n;
- sram_addr <= mmu_a[18:0];
- sram_fg_q <= 1'b0;
+ sram_ce_q <= 1'b1;
+ sram_we_q <= ~cpu_wr_n;
+ sram_oe_q <= ~cpu_rd_n;
+ sram_addr_q <= mmu_a[18:0];
+ sram_d_q <= ~cpu_wr_n ? cpu_do : 8'bx;
+ sram_fg_q <= 1'b0;
end
else if (sram_fgrd)
begin
- sram_ce_q <= 1'b1;
- sram_we_q <= 1'b0;
- sram_oe_q <= 1'b1;
- sram_addr <= sram_fgaddr;
- sram_fg_q <= 1'b1;
+ sram_ce_q <= 1'b1;
+ sram_we_q <= 1'b0;
+ sram_oe_q <= 1'b1;
+ sram_addr_q <= sram_fgaddr;
+ sram_d_q <= 8'bx;
+ sram_fg_q <= 1'b1;
end
else
begin
- sram_ce_q <= 1'b0;
- sram_we_q <= 1'b0;
- sram_oe_q <= 1'b0;
- sram_addr <= 19'bx;
- sram_fg_q <= 1'b0;
+ sram_ce_q <= 1'b0;
+ sram_we_q <= 1'b0;
+ sram_oe_q <= 1'b0;
+ sram_addr_q <= 19'bx;
+ sram_d_q <= 8'bx;
+ sram_fg_q <= 1'b0;
end // else: !if(sram_fgrd)
end
- 3'd3:
+ 3'd5:
begin
sram_we_q <= 1'b0;
end
- 3'd4:
+ 3'd6:
begin
- sram_do <= sram_q;
- npled_do <= 8'bx;
+ sram_do <= sram_q;
- sram_ce_q <= 1'b1;
- sram_we_q <= 1'b0;
- sram_oe_q <= 1'b1;
- sram_addr <= npled_addr;
+ sram_ce_q <= 1'b1;
+ sram_we_q <= 1'b0;
+ sram_oe_q <= 1'b1;
+ sram_addr_q <= npled_addr;
end
default:
@@ -564,17 +582,17 @@ module abc80 (
// Driving output pins.
- assign sram_a = sram_addr[18:1];
- assign sram_be_n = ~{sram_addr[0], ~sram_addr[0]};
+ assign sram_a = sram_addr_q[18:1];
+ assign sram_be_n = ~{sram_addr_q[0], ~sram_addr_q[0]};
assign sram_ce_n = ~sram_ce_q;
assign sram_oe_n = ~sram_oe_q;
assign sram_we_n = ~sram_we_q;
- assign sram_dq = sram_we_q ? { cpu_do, cpu_do } : 16'bz;
+ assign sram_dq = sram_we_q ? { sram_d_q, sram_d_q } : 16'bz;
// SRAM Input side MUX
- assign sram_q = sram_addr[0] ? sram_dq[15:8] : sram_dq[7:0];
+ assign sram_q = sram_addr_q[0] ? sram_dq[15:8] : sram_dq[7:0];
// fg unit FIFO handshake
assign sram_fgdata = sram_do;
@@ -690,11 +708,11 @@ module abc80 (
.data_a ( 16'bx ), // Never written
.q_a ( mmu_q ),
.wren_a ( 1'b0 ),
+ .clock ( sram_clk ),
.address_b ( mmu_mod_addr[9:0] ),
.data_b ( { cpu_do, mmu_mod_data[7:0] } ),
.q_b ( mmu_rd_data ),
.wren_b ( mmu_wr_e ),
- .clock ( fast_clk )
);
assign mmu_patch = mmu_q[15];
@@ -702,7 +720,7 @@ module abc80 (
assign mmu_a[19:8] = mmu_q[11:0];
assign mmu_a[7:0] = cpu_a[7:0];
- always @(posedge fast_clk)
+ always @(posedge sram_clk)
begin
if ( ~cpu_mreq_n & cpu_rfsh_n )
case ( mmu_devsel )
@@ -1016,7 +1034,7 @@ module abc80 (
always @(negedge rst_n or posedge cpu_clk)
begin
if ( ~rst_n )
- sound <= 0;
+ sound <= 8'b0;
else
if ( ~abc_out_n[6] )
sound <= cpu_do;
@@ -1026,15 +1044,12 @@ module abc80 (
// Audio generation
// ------------------------------------------------------------------------
- reg [7:0] sound_sc0;
- reg [7:0] sound_sc;
+ wire [7:0] sound_sc;
reg [3:0] i2c_ctr;
- always @(posedge audio_clk)
- begin
- sound_sc0 <= sound; // Synchronize to audio_clk
- sound_sc <= sound_sc0;
- end
+ synchronize #(.width(8))
+ sound_sc_sync(.d(sound), .q(sound_sc), .reset(1'b0),
+ .clk(audio_clk), .enable(1'b1));
sound_i2s sound_i2s (
.i2s_clk (audio_clk),
diff --git a/debounce.v b/debounce.v
index 16894c4..0fd49ea 100644
--- a/debounce.v
+++ b/debounce.v
@@ -26,7 +26,8 @@ module debounce (
wire [width-1:0] in_q;
synchronize #(.width(width))
- debounce_sync (.reset(~reset_n), .clk(clk), .d(in), .q(in_q));
+ debounce_sync (.reset(~reset_n), .clk(clk), .enable(1'b1),
+ .d(in), .q(in_q));
genvar i;
generate
diff --git a/display.v b/display.v
index c1ec19d..594edaa 100644
--- a/display.v
+++ b/display.v
@@ -139,11 +139,12 @@ module display (
// Synchronize width input
synchronize
- width_sync (.reset(1'b0), .clk(clk), .d(width), .q(v_width));
+ width_sync (.reset(1'b0), .clk(clk), .enable (1'b1),
+ .d(width), .q(v_width));
// Synchronize fg_ctl input, update during vsync only
- synchronize #(.width(8), .stabilize(1))
- fg_ctl_sync (.reset(1'b0), .clk(clk), .enable (~video_y),
+ synchronize #(.width(8))
+ fg_ctl_sync (.reset(1'b0), .clk(clk), .enable (~yvideo),
.d(fg_ctl), .q(fgctl_q));
// Should we advance the character pixel?
diff --git a/mega/mmuram.v b/mega/mmuram.v
index a1593e6..1ba3ec7 100644
--- a/mega/mmuram.v
+++ b/mega/mmuram.v
@@ -1,236 +1,240 @@
-// megafunction wizard: %ALTSYNCRAM%
-// GENERATION: STANDARD
-// VERSION: WM1.0
-// MODULE: altsyncram
-
-// ============================================================
-// File Name: mmuram.v
-// Megafunction Name(s):
-// altsyncram
-//
-// Simulation Library Files(s):
-// altera_mf
-// ============================================================
-// ************************************************************
-// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-//
-// 8.1 Build 163 10/28/2008 SJ Web Edition
-// ************************************************************
-
-
-//Copyright (C) 1991-2008 Altera Corporation
-//Your use of Altera Corporation's design tools, logic functions
-//and other software and tools, and its AMPP partner logic
-//functions, and any output files from any of the foregoing
-//(including device programming or simulation files), and any
-//associated documentation or information are expressly subject
-//to the terms and conditions of the Altera Program License
-//Subscription Agreement, Altera MegaCore Function License
-//Agreement, or other applicable license agreement, including,
-//without limitation, that your use is for the sole purpose of
-//programming logic devices manufactured by Altera and sold by
-//Altera or its authorized distributors. Please refer to the
-//applicable agreement for further details.
-
-
-// synopsys translate_off
-`timescale 1 ps / 1 ps
-// synopsys translate_on
-module mmuram (
- address_a,
- address_b,
- clock,
- data_a,
- data_b,
- wren_a,
- wren_b,
- q_a,
- q_b);
-
- input [9:0] address_a;
- input [9:0] address_b;
- input clock;
- input [15:0] data_a;
- input [15:0] data_b;
- input wren_a;
- input wren_b;
- output [15:0] q_a;
- output [15:0] q_b;
-
- wire [15:0] sub_wire0;
- wire [15:0] sub_wire1;
- wire [15:0] q_a = sub_wire0[15:0];
- wire [15:0] q_b = sub_wire1[15:0];
-
- altsyncram altsyncram_component (
- .wren_a (wren_a),
- .clock0 (clock),
- .wren_b (wren_b),
- .address_a (address_a),
- .address_b (address_b),
- .data_a (data_a),
- .data_b (data_b),
- .q_a (sub_wire0),
- .q_b (sub_wire1),
- .aclr0 (1'b0),
- .aclr1 (1'b0),
- .addressstall_a (1'b0),
- .addressstall_b (1'b0),
- .byteena_a (1'b1),
- .byteena_b (1'b1),
- .clock1 (1'b1),
- .clocken0 (1'b1),
- .clocken1 (1'b1),
- .clocken2 (1'b1),
- .clocken3 (1'b1),
- .eccstatus (),
- .rden_a (1'b1),
- .rden_b (1'b1));
- defparam
- altsyncram_component.address_reg_b = "CLOCK0",
- altsyncram_component.clock_enable_input_a = "BYPASS",
- altsyncram_component.clock_enable_input_b = "BYPASS",
- altsyncram_component.clock_enable_output_a = "BYPASS",
- altsyncram_component.clock_enable_output_b = "BYPASS",
- altsyncram_component.indata_reg_b = "CLOCK0",
- altsyncram_component.init_file = "data/mmu.mif",
- altsyncram_component.intended_device_family = "Cyclone II",
- altsyncram_component.lpm_type = "altsyncram",
- altsyncram_component.maximum_depth = 256,
- altsyncram_component.numwords_a = 1024,
- altsyncram_component.numwords_b = 1024,
- altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
- altsyncram_component.outdata_aclr_a = "NONE",
- altsyncram_component.outdata_aclr_b = "NONE",
- altsyncram_component.outdata_reg_a = "CLOCK0",
- altsyncram_component.outdata_reg_b = "CLOCK0",
- altsyncram_component.power_up_uninitialized = "FALSE",
- altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
- altsyncram_component.widthad_a = 10,
- altsyncram_component.widthad_b = 10,
- altsyncram_component.width_a = 16,
- altsyncram_component.width_b = 16,
- altsyncram_component.width_byteena_a = 1,
- altsyncram_component.width_byteena_b = 1,
- altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
-
-
-endmodule
-
-// ============================================================
-// CNX file retrieval info
-// ============================================================
-// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-// Retrieval info: PRIVATE: CLRq NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-// Retrieval info: PRIVATE: Clock NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-// Retrieval info: PRIVATE: ECC NUMERIC "0"
-// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
-// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
-// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "data/mmu.mif"
-// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-// Retrieval info: PRIVATE: REGdata NUMERIC "1"
-// Retrieval info: PRIVATE: REGq NUMERIC "1"
-// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-// Retrieval info: PRIVATE: REGrren NUMERIC "0"
-// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-// Retrieval info: PRIVATE: REGwren NUMERIC "1"
-// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
-// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-// Retrieval info: PRIVATE: enable NUMERIC "0"
-// Retrieval info: PRIVATE: rden NUMERIC "0"
-// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: INIT_FILE STRING "data/mmu.mif"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
-// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
-// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
-// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]
-// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]
-// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
-// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
-// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
-// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
-// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.bsf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_inst.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_bb.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_waveforms.html TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_wave*.jpg FALSE
-// Retrieval info: LIB_FILE: altera_mf
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: mmuram.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module mmuram (
+ address_a,
+ address_b,
+ clock,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [9:0] address_a;
+ input [9:0] address_b;
+ input clock;
+ input [15:0] data_a;
+ input [15:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [15:0] q_a;
+ output [15:0] q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock;
+ tri0 wren_a;
+ tri0 wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [15:0] sub_wire0;
+ wire [15:0] sub_wire1;
+ wire [15:0] q_a = sub_wire0[15:0];
+ wire [15:0] q_b = sub_wire1[15:0];
+
+ altsyncram altsyncram_component (
+ .clock0 (clock),
+ .wren_a (wren_a),
+ .address_b (address_b),
+ .data_b (data_b),
+ .wren_b (wren_b),
+ .address_a (address_a),
+ .data_a (data_a),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clock1 (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1));
+ defparam
+ altsyncram_component.address_reg_b = "CLOCK0",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_input_b = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.clock_enable_output_b = "BYPASS",
+ altsyncram_component.indata_reg_b = "CLOCK0",
+ altsyncram_component.init_file = "./data/mmu.mif",
+ altsyncram_component.intended_device_family = "Cyclone II",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 1024,
+ altsyncram_component.numwords_b = 1024,
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_aclr_b = "NONE",
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",
+ altsyncram_component.outdata_reg_b = "UNREGISTERED",
+ altsyncram_component.power_up_uninitialized = "FALSE",
+ altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+ altsyncram_component.widthad_a = 10,
+ altsyncram_component.widthad_b = 10,
+ altsyncram_component.width_a = 16,
+ altsyncram_component.width_b = 16,
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.width_byteena_b = 1,
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./data/mmu.mif"
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./data/mmu.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
+// Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
+// Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
+// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
+// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
+// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
+// Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
+// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
+// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL mmuram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/mega/pll1.v b/mega/pll1.v
index a2bc288..a085b15 100644
--- a/mega/pll1.v
+++ b/mega/pll1.v
@@ -107,7 +107,7 @@ module pll1 (
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 2,
+ altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
@@ -194,7 +194,7 @@ endmodule
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -223,14 +223,14 @@ endmodule
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
@@ -287,7 +287,7 @@ endmodule
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"