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authorH. Peter Anvin <hpa@zytor.com>2016-10-14 10:58:46 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-10-14 10:58:46 (GMT)
commitb75d0d464345977847f947f07460345a7d67cee2 (patch)
treedacfc3575ef277d9259294fb47f7517912d38c74
parent2ae02d9256b66756da4b089b65b9f45069baea9d (diff)
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Add color block graphics unit
Add a completely invented color block graphics unit; it should hopefully be fun for kids to play with using the equivalent method to using characters for groups of normal block pixels.
-rw-r--r--abc80.v29
-rwxr-xr-xdata/mmuinit.pl16
-rw-r--r--data/video.txt2
-rw-r--r--display.v245
-rw-r--r--mega/bgram.v240
-rw-r--r--tools/z80asm/Makefile2
6 files changed, 420 insertions, 114 deletions
diff --git a/abc80.v b/abc80.v
index f8a45df..92e5011 100644
--- a/abc80.v
+++ b/abc80.v
@@ -305,9 +305,12 @@ module abc80 (
wire [7:0] video_d;
wire [10:0] chargen_a;
wire [7:0] chargen_d; // Only the low 6 bits are actually used
- wire [2:0] rgb;
+ wire [12:0] bgram_a;
+ wire [5:0] bgram_d;
+ wire [5:0] rgb;
wire [7:0] vram_do;
wire [7:0] cgen_do;
+ wire [7:0] bgram_do;
reg video_width;
videoram video_ram (
@@ -334,6 +337,21 @@ module abc80 (
.clock_b ( fast_clk )
);
+ bgram bg_ram (
+ .wren_a ( 0 ),
+ .address_a ( bgram_a ),
+ .q_a ( bgram_d ),
+ .clock_a ( video_clk ),
+ .data_b ( {cpu_do[6], cpu_do[4:0]} ),
+ .wren_b ( msel[4] & ~cpu_wr_n ),
+ .address_b ( mmu_a[12:0] ),
+ .q_b ( {bgram_do[6], bgram_do[4:0]} ),
+ .clock_b ( fast_clk )
+ );
+ // These bits are fixed
+ assign bgram_do[7] = 1'b0;
+ assign bgram_do[5] = 1'b1;
+
display video (
.clk ( video_clk ),
.width ( video_width ),
@@ -345,6 +363,8 @@ module abc80 (
.d ( video_d ),
.ga ( chargen_a ),
.gd ( chargen_d[5:0] ),
+ .bga ( bgram_a ),
+ .bgd ( bgram_d ),
.rgb ( rgb ),
.vsync ( vga_vs ),
.hsync ( vga_hs ),
@@ -359,9 +379,9 @@ module abc80 (
// SW[4] and SW[3] can be used to emulate a green or amber monitor
// for the normal ABC80 screen, while still allowing colors to be
// shown, just permuted.
- assign vga_r = {4{rgb[2] ^ (sw[4] & rgb[1])}};
- assign vga_g = {4{rgb[1]}};
- assign vga_b = {4{rgb[0] ^ (sw[3] & rgb[1])}};
+ assign vga_r = {2{rgb[5:4] ^ ({2{sw[4]}} & rgb[3:2])}};
+ assign vga_g = {2{rgb[3:2]}};
+ assign vga_b = {2{rgb[1:0] ^ ({2{sw[4]}} & rgb[3:2])}};
// ------------------------------------------------------------------------
// External SRAM
@@ -1074,6 +1094,7 @@ module abc80 (
8'b00000010: cpu_di <= flsh_do;
8'b00000100: cpu_di <= vram_do;
8'b00001000: cpu_di <= cgen_do;
+ 8'b00010000: cpu_di <= bgram_do;
8'b10000000: cpu_di <= mmu_a[15:8];
8'b00000000: cpu_di <= io_do;
default: cpu_di <= 8'bx;
diff --git a/data/mmuinit.pl b/data/mmuinit.pl
index 389c89f..fb04118 100755
--- a/data/mmuinit.pl
+++ b/data/mmuinit.pl
@@ -20,7 +20,7 @@
# 1 - Flash ROM
# 2 - Video RAM
# 3 - Character generator RAM
-# 4 - Reserved
+# 4 - Block graphics RAM
# 5 - Reserved
# 6 - Reserved
# 7 - Hyperspace (reads bits[7:0], writes nowhere)
@@ -29,6 +29,7 @@
#
$testram = 0;
+$with_bgram = 1;
sub do_ram() {
if ( $testram ) {
@@ -60,9 +61,12 @@ $a = 0;
for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC
printf("%03X : %04X;\n", $a++, 0x9000|$i);
}
-for ( $i = 0x40 ; $i < 0x60 ; $i++ ) { # Free for expansion
+for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Free for expansion
printf("%03X : %04X;\n", $a++, 0x70FF);
}
+for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # Free for expansion or bgram
+ printf("%03X : %04X;\n", $a++, $with_bgram ? 0x4000|($i-0x48) : 0x70FF);
+}
for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS, IEC options
printf("%03X : %04X;\n", $a++, 0x1000|$i);
}
@@ -84,7 +88,13 @@ do_ram();
for ( $i = 0x00 ; $i < 0x40 ; $i++ ) { # BASIC (in RAM)
printf("%03X : %04X;\n", $a++, 0x8000|$i);
}
-for ( $i = 0x40 ; $i < 0x74 ; $i++ ) { # Various ROMs (in RAM)
+for ( $i = 0x40 ; $i < 0x48 ; $i++ ) { # Expansion (fill with RAM)
+ printf("%03X : %04X;\n", $a++, 0x0000|$i);
+}
+for ( $i = 0x48 ; $i < 0x60 ; $i++ ) { # RAM or bgram
+ printf("%03X : %04X;\n", $a++, $with_bgram ? 0x4000|($i-0x48) : 0x0000|$i);
+}
+for ( $i = 0x60 ; $i < 0x74 ; $i++ ) { # DOS and IEC (in RAM)
printf("%03X : %04X;\n", $a++, 0x0000|$i);
}
for ( $i = 0x74 ; $i < 0x78 ; $i++ ) { # Video RAM (for 80 col only)
diff --git a/data/video.txt b/data/video.txt
index a5023d7..db3e1ef 100644
--- a/data/video.txt
+++ b/data/video.txt
@@ -1,5 +1,5 @@
Hello, World!
-Suzi is cute!
+Testing HPA's ABC80 FPGA simulation
BLUE blue BLUE blue
GREEN green GREEN green
diff --git a/display.v b/display.v
index 81886b7..68c5be0 100644
--- a/display.v
+++ b/display.v
@@ -1,18 +1,20 @@
module display (
- input clk, // 18.75 MHz
-
+ input clk, // 18.75 MHz
+
input width,
input reverse,
input noblink,
input testpattern,
input reveal,
-
+
output reg [10:0] a,
input [7:0] d,
output [10:0] ga,
input [5:0] gd,
+ output [12:0] bga,
+ input [5:0] bgd,
- output reg [2:0] rgb,
+ output reg [5:0] rgb,
output vsync,
output hsync,
@@ -38,7 +40,7 @@ module display (
// 30 pixels ( 5 char) front porch
// ----------
// 594 pixels (31.68 us)
-//
+//
// Vertical:
// 480 lines graphics (24 rows x 10 pixels x 2 scans/pixel)
// 10 lines back porch/border
@@ -59,101 +61,108 @@ module display (
// especially the desired aspect ratio. Therefore, we want to use -hsync
// and -vsync, - meaning active low, + meaning active high.
- parameter x_blank = 480+6;
- parameter x_sync = x_blank+(12-6);
- parameter x_front = x_sync+72;
- parameter x_max = 594;
-
- parameter y_blank = 480;
- parameter y_sync = y_blank+10;
- parameter y_front = y_sync+2;
- parameter y_max = 525;
-
- parameter hsync_minus = 1'b1; // -hsync
- parameter vsync_minus = 1'b1; // -vsync
-
- reg hsync_q; // Horizontal sync active
- reg vsync_q; // Vertical sync active
-
- reg [9:0] x; // Horizontal pixel count
- reg [9:0] y; // Vertical pixel count
- reg [6:0] xchr; // Character column (0..99)
- reg [2:0] xpxl; // Pixel column in character (0..5)
- reg [4:0] ychr; // Character row (0..26)
- reg [3:0] ypxl; // Pixel row in character (0..9)
- reg [4:0] ylu; // Previous character line
-
- wire xvideo; // Non-blanked in the x direction
- wire yvideo; // Non-blanked in the y direction
- wire [10:0] a80; // Memory address assuming 80 columns
- wire [10:0] a80u; // Memory address assuming 80 columns (-1 line)
- wire [10:0] a40; // Memory address assuming 40 columns
- wire [10:0] a40u; // Memory address assuming 40 columns (-1 line)
- reg [4:0] scan_counter; // Counter of total scans (for flashing et al)
- reg [5:0] pixrow; // One character worth of pixels
- reg prefetch; // True for the prefetch character position
+ parameter x_blank = 480+6;
+ parameter x_sync = x_blank+(12-6);
+ parameter x_front = x_sync+72;
+ parameter x_max = 594;
+
+ parameter y_blank = 480;
+ parameter y_sync = y_blank+10;
+ parameter y_front = y_sync+2;
+ parameter y_max = 525;
+
+ parameter hsync_minus = 1'b1; // -hsync
+ parameter vsync_minus = 1'b1; // -vsync
+
+ reg hsync_q; // Horizontal sync active
+ reg vsync_q; // Vertical sync active
+
+ reg [9:0] x; // Horizontal pixel count
+ reg [9:0] y; // Vertical pixel count
+ reg [6:0] xchr; // Character column (0..99)
+ reg [2:0] xpxl; // Pixel column in character (0..5)
+ reg [4:0] ychr; // Character row (0..26)
+ reg [3:0] ypxl; // Pixel row in character (0..9)
+ wire [3:0] ypxlp = ypxl + 4'd1; // d:o but 1..10
+ reg [4:0] ylu; // Previous character line
+
+ wire xvideo; // Non-blanked in the x direction
+ wire yvideo; // Non-blanked in the y direction
+ wire [10:0] a80; // Memory address assuming 80 columns
+ wire [10:0] a80u; // Memory address assuming 80 columns (-1 line)
+ wire [10:0] a40; // Memory address assuming 40 columns
+ wire [10:0] a40u; // Memory address assuming 40 columns (-1 line)
+ reg [4:0] scan_counter; // Counter of total scans (for flashing et al)
+ reg [5:0] pixrow; // One character worth of pixels
+ reg prefetch; // True for the prefetch character position
// Fine Graphics control
- reg [7:0] fgctl_q; // Latched version of fg_ctl
- reg [7:0] fgpixels; // One byte of fg pixels
-
+ reg [7:0] fgctl_q; // Latched version of fg_ctl
+ reg [7:0] fgpixels; // One byte of fg pixels
+
+ // Block graphics data
+ reg [5:0] block_rgb; // Current block graphics pixel
+ reg [6:0] block_x; // Block graphics pixel X
+ reg [2:0] block_xpxl; // Physical pixel inside block
+ // We leverage ychr and ypxl for the vertical
+
// For the current text line
- reg [2:0] curfg; // Foreground RGB
- reg [2:0] curbg; // Background RGB
- reg inverse; // Inverse video
- reg isgraph; // Graphic mode?
- reg isgsep; // Separated graphics?
- reg isgrel; // Hold graphics?
- reg isdble; // Double height?
- reg isflsh; // Flashing?
- reg ishide; // Hidden
- reg [7:0] thischar; // Character code currently processing
+ reg [2:0] curfg; // Foreground RGB
+ reg [2:0] curbg; // Background RGB
+ reg inverse; // Inverse video
+ reg isgraph; // Graphic mode?
+ reg isgsep; // Separated graphics?
+ reg isgrel; // Hold graphics?
+ reg isdble; // Double height?
+ reg isflsh; // Flashing?
+ reg ishide; // Hidden
+ reg [7:0] thischar; // Character code currently processing
// These refer to the same as above, but for the previous text line
- reg [2:0] oldfg; // Foreground RGB
- reg [2:0] oldbg; // Background RGB
- reg wasgraph; // Graphic mode?
- reg wasgsep; // Separated graphics?
- reg wasgrel; // Hold graphics?
- reg wasdble; // Double height?
- reg wasflsh; // Flashing?
- reg washide; // Hidden
- reg [7:0] thatchar; // Character code currently processing
+ reg [2:0] oldfg; // Foreground RGB
+ reg [2:0] oldbg; // Background RGB
+ reg wasgraph; // Graphic mode?
+ reg wasgsep; // Separated graphics?
+ reg wasgrel; // Hold graphics?
+ reg wasdble; // Double height?
+ reg wasflsh; // Flashing?
+ reg washide; // Hidden
+ reg [7:0] thatchar; // Character code currently processing
// The one we're currently displaying
- wire [2:0] fg = wasdble ? oldfg : curfg;
- wire [2:0] bg = wasdble ? oldbg : curbg;
- wire [7:0] somechar = wasdble ? thatchar : thischar;
+ wire [2:0] fg = wasdble ? oldfg : curfg;
+ wire [2:0] bg = wasdble ? oldbg : curbg;
+ wire [7:0] somechar = wasdble ? thatchar : thischar;
wire gsep = wasdble ? wasgsep : isgsep;
- wire do_flsh = wasdble ? wasflsh : isflsh;
- wire do_hide = wasdble ? washide : ishide;
+ wire do_flsh = wasdble ? wasflsh : isflsh;
+ wire do_hide = wasdble ? washide : ishide;
// Should we advance the character pixel?
// We need to always advance at full speed during prefetch, or
// we would have to start the prefetch earlier in 40-character mode.
- wire advance = width | x[0] | prefetch;
-
+ wire advance = width | x[0] | prefetch;
+
// Address mapping for 40 and 80 characters
- assign a80[3:0] = xchr[3:0];
- wire [3:0] x80middle = { 1'b0, xchr[6:4] };
- wire [3:0] ymiddle = { ychr[4:3] , ychr[4:3] };
- assign a80[7:4] = x80middle+ymiddle;
- assign a80[10:8] = ychr[2:0];
+ assign a80[3:0] = xchr[3:0];
+ wire [3:0] x80middle = { 1'b0, xchr[6:4] };
+ wire [3:0] ymiddle = { ychr[4:3] , ychr[4:3] };
+ assign a80[7:4] = x80middle+ymiddle;
+ assign a80[10:8] = ychr[2:0];
assign a40[2:0] = xchr[2:0];
- wire [3:0] x40middle = { 1'b0, xchr[5:3] };
- assign a40[6:3] = x40middle + ymiddle;
- assign a40[10:7] = { 1'b1, ychr[2:0] };
+ wire [3:0] x40middle = { 1'b0, xchr[5:3] };
+ assign a40[6:3] = x40middle + ymiddle;
+ assign a40[10:7] = { 1'b1, ychr[2:0] };
// Address mapping for 40 and 80 characters minus one line
- assign a80u[3:0] = xchr[3:0];
- wire [3:0] yumiddle = { ylu[4:3] , ylu[4:3] };
- assign a80u[7:4] = x80middle+yumiddle;
- assign a80u[10:8] = ylu[2:0];
+ assign a80u[3:0] = xchr[3:0];
+ wire [3:0] yumiddle = { ylu[4:3] , ylu[4:3] };
+ assign a80u[7:4] = x80middle+yumiddle;
+ assign a80u[10:8] = ylu[2:0];
- assign a40u[2:0] = xchr[2:0];
- assign a40u[6:3] = x40middle+yumiddle;
- assign a40u[10:7] = { 1'b1, ylu[2:0] };
+ assign a40u[2:0] = xchr[2:0];
+ assign a40u[6:3] = x40middle+yumiddle;
+ assign a40u[10:7] = { 1'b1, ylu[2:0] };
// Final address mapping
// Note: We read the current char between pixels 0 and 1,
@@ -170,35 +179,42 @@ module display (
a = a80u;
endcase // case( { width, xchr[1] } )
+ // Block graphics address mapping
+ assign bga[3:0] = block_x[3:0];
+ wire [3:0] bgxmiddle = { 1'b0, block_x[6:4] };
+ wire [3:0] bgymiddle = { ypxlp[3:2], ypxlp[3:2] };
+ assign bga[7:4] = bgxmiddle + bgymiddle;
+ assign bga[12:8] = ychr;
+
// Character generator address mapping
- assign ga[10:4] = somechar[6:0];
- assign ga[3:0] = wasdble ? { 1'b1, ypxl[3:1] } :
+ assign ga[10:4] = somechar[6:0];
+ assign ga[3:0] = wasdble ? { 1'b1, ypxl[3:1] } :
isdble ? { 1'b0, ypxl[3:1] } :
ypxl[3:0];
// Video enable signal
- assign xvideo = ( x < x_blank );
- assign yvideo = ( y < y_blank );
+ assign xvideo = ( x < x_blank );
+ assign yvideo = ( y < y_blank );
+
+ assign hsync = hsync_q ^ hsync_minus;
+ assign vsync = vsync_q ^ vsync_minus;
- assign hsync = hsync_q ^ hsync_minus;
- assign vsync = vsync_q ^ vsync_minus;
-
// Flashing
- wire flash_on = scan_counter[4];
+ wire flash_on = scan_counter[4];
// Inverse video. The normal is a flashing inverse cursor, but
// if "noblink" is asserted the cursor is steady inverted. If
// "reverse" is asserted with invert everything *on top of that*...
- wire invert = (inverse & (flash_on|noblink))^reverse;
+ wire invert = (inverse & (flash_on|noblink))^reverse;
//
// Fine graphics
//
- assign fg_ack = xvideo & yvideo & (x[2:0] == 3'b000);
- assign fg_xrst = yvideo & hsync_q;
- assign fg_yrst = vsync_q;
+ assign fg_ack = xvideo & yvideo & (x[2:0] == 3'b000);
+ assign fg_xrst = yvideo & hsync_q;
+ assign fg_yrst = vsync_q;
- wire [3:0] fg_argb;
+ wire [3:0] fg_argb;
always @(posedge clk)
if ( ~yvideo ) // Only change mode during vertical blank
@@ -215,35 +231,37 @@ module display (
.clock ( clk ),
.q ( fg_argb )
);
-
+
// Synchronous logic
always @(posedge clk)
begin
if ( ~xvideo | ~yvideo | prefetch )
- rgb <= 3'b000; // Blank
+ rgb <= 6'b000000; // Blank
else if ( testpattern )
// Pixel test pattern for LCD monitor calibration
- rgb <= {3{x[0] ^ y[0]}};
+ rgb <= {6{x[0] ^ y[0]}} ^ {6{invert}};
else if ( ~fgctl_q[7] & pixrow[5]
& ~(do_flsh & ~flash_on)
& ~(do_hide & ~reveal) )
- rgb <= fg ^ {3{invert}};
+ rgb <= {fg[2],fg[2],fg[1],fg[1],fg[0],fg[0]} ^ {6{invert}};
else if (fgctl_q[7] | fg_argb[3])
- rgb <= fg_argb[2:0];
+ rgb <= {fg_argb[2],fg_argb[2],fg_argb[1],fg_argb[1],fg_argb[0],fg_argb[0]} ^ {6{invert}};
+ else if (bg == 3'b000)
+ rgb <= block_rgb ^ {6{invert}};
else
- rgb <= bg ^ {3{invert}};
+ rgb <= {bg[2],bg[2],bg[1],bg[1],bg[0],bg[0]} ^ {6{invert}};
// Sync pulses
vsync_q <= ( y >= y_sync && y < y_front );
hsync_q <= ( x >= x_sync && x < x_front );
-
+
// Rotating shift register; may be overridden by the below
// The rotation is so that if we're in GHOL mode we already
// have the previous value
if ( advance )
pixrow <= { pixrow[4:0], pixrow[5] };
-
+
// This code is run 6 times per character; regardless of width
if ( advance )
begin
@@ -259,7 +277,7 @@ module display (
// Load and process previous-line character
thatchar <= (ychr == 0) ? 8'h00 : d;
end
-
+
3'b101:
begin
// Load a new pixel row?
@@ -416,14 +434,22 @@ module display (
end // case: 3'b101
endcase // case( xpxl )
end // if ( advance )
-
+
+ // Block graphics - the block graphics pixels exactly match
+ // 80-column characters
+ if ( block_xpxl == 3'd5 )
+ block_rgb <= bgd;
+
// Counters
if ( x == x_max-1 )
begin
x <= 10'd0;
xchr <= 7'd0;
xpxl <= 3'd0;
+ block_x <= 7'd0;
+ block_xpxl <= 3'd0;
pixrow <= 6'b0; // Read-ahead spot is blank
+ block_rgb <= 6'b0;
prefetch <= 1'b1; // Prefetch character
inverse <= 1'b0; // Not inverse video
curfg <= 3'b111; // Default fg is white
@@ -477,6 +503,15 @@ module display (
else
xpxl <= xpxl + 1;
end
+
+ if ( block_xpxl == 3'd5 )
+ begin
+ block_xpxl <= 0;
+ block_x <= block_x + 1;
+ end
+ else
+ block_xpxl <= block_xpxl + 1;
+
x <= x + 1;
end // else: !if( x == x_max-1 )
end // always @ (posedge clk)
diff --git a/mega/bgram.v b/mega/bgram.v
new file mode 100644
index 0000000..ea741e5
--- /dev/null
+++ b/mega/bgram.v
@@ -0,0 +1,240 @@
+// megafunction wizard: %RAM: 2-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: bgram.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module bgram (
+ address_a,
+ address_b,
+ clock_a,
+ clock_b,
+ data_a,
+ data_b,
+ wren_a,
+ wren_b,
+ q_a,
+ q_b);
+
+ input [12:0] address_a;
+ input [12:0] address_b;
+ input clock_a;
+ input clock_b;
+ input [5:0] data_a;
+ input [5:0] data_b;
+ input wren_a;
+ input wren_b;
+ output [5:0] q_a;
+ output [5:0] q_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock_a;
+ tri0 wren_a;
+ tri0 wren_b;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [5:0] sub_wire0;
+ wire [5:0] sub_wire1;
+ wire [5:0] q_a = sub_wire0[5:0];
+ wire [5:0] q_b = sub_wire1[5:0];
+
+ altsyncram altsyncram_component (
+ .clock0 (clock_a),
+ .wren_a (wren_a),
+ .address_b (address_b),
+ .clock1 (clock_b),
+ .data_b (data_b),
+ .wren_b (wren_b),
+ .address_a (address_a),
+ .data_a (data_a),
+ .q_a (sub_wire0),
+ .q_b (sub_wire1),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .eccstatus (),
+ .rden_a (1'b1),
+ .rden_b (1'b1));
+ defparam
+ altsyncram_component.address_reg_b = "CLOCK1",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_input_b = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.clock_enable_output_b = "BYPASS",
+ altsyncram_component.indata_reg_b = "CLOCK1",
+ altsyncram_component.intended_device_family = "Cyclone II",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 8192,
+ altsyncram_component.numwords_b = 8192,
+ altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_aclr_b = "NONE",
+ altsyncram_component.outdata_reg_a = "UNREGISTERED",
+ altsyncram_component.outdata_reg_b = "UNREGISTERED",
+ altsyncram_component.power_up_uninitialized = "FALSE",
+ altsyncram_component.widthad_a = 13,
+ altsyncram_component.widthad_b = 13,
+ altsyncram_component.width_a = 6,
+ altsyncram_component.width_b = 6,
+ altsyncram_component.width_byteena_a = 1,
+ altsyncram_component.width_byteena_b = 1,
+ altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "1"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+// Retrieval info: PRIVATE: CLRq NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "5"
+// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MEMSIZE NUMERIC "49152"
+// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+// Retrieval info: PRIVATE: REGdata NUMERIC "1"
+// Retrieval info: PRIVATE: REGq NUMERIC "0"
+// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+// Retrieval info: PRIVATE: REGrren NUMERIC "0"
+// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+// Retrieval info: PRIVATE: REGwren NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
+// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
+// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
+// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
+// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+// Retrieval info: PRIVATE: enable NUMERIC "0"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
+// Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+// Retrieval info: USED_PORT: address_a 0 0 13 0 INPUT NODEFVAL "address_a[12..0]"
+// Retrieval info: USED_PORT: address_b 0 0 13 0 INPUT NODEFVAL "address_b[12..0]"
+// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+// Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL "data_a[5..0]"
+// Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL "data_b[5..0]"
+// Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL "q_a[5..0]"
+// Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL "q_b[5..0]"
+// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+// Retrieval info: CONNECT: @address_a 0 0 13 0 address_a 0 0 13 0
+// Retrieval info: CONNECT: @address_b 0 0 13 0 address_b 0 0 13 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+// Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
+// Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
+// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+// Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
+// Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL bgram_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/tools/z80asm/Makefile b/tools/z80asm/Makefile
index 0e01daa..37b2b01 100644
--- a/tools/z80asm/Makefile
+++ b/tools/z80asm/Makefile
@@ -25,7 +25,7 @@ all:z80asm
z80asm: z80asm.o expressions.o Makefile gnulib/getopt.o gnulib/getopt1.o
$(CC) $(LDFLAGS) $(filter %.o,$^) -o $@
- $(MAKE) -C tests || rm $@
+ # $(MAKE) -C tests || rm $@
%.o:%.c z80asm.h gnulib/getopt.h Makefile
$(CC) $(CFLAGS) -c $< -o $@ -DVERSION=\"$(shell cat VERSION)\"