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authorH. Peter Anvin <hpa@zytor.com>2016-10-23 11:19:47 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-10-23 11:19:47 (GMT)
commitb5018bba2d62efa936c96daa2917d5688c1555a1 (patch)
treeaae18b9177e8de0552042821a7dfb107291db5a4
parentc846596ccdc554f72c89fbfae2489670995364dc (diff)
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Add support for using the GPIO 0 header as, well, GPIOs.
It is sometimes useful to be able to control the GPIO header pins as, well, GPIOs. Make it so. No interrupt support or anything like that.
-rw-r--r--abc80.v148
-rw-r--r--ports.txt32
2 files changed, 148 insertions, 32 deletions
diff --git a/abc80.v b/abc80.v
index 92e5011..8629a21 100644
--- a/abc80.v
+++ b/abc80.v
@@ -917,6 +917,29 @@ module abc80 (
// ------------------------------------------------------------------------
+ // GPIO(0) header
+ //
+ // gpio_io: the actual state of the pins
+ // gpio_dat: data for output pin
+ // gpio_ctl: 0 for input/tristate, 1 for output
+ // ------------------------------------------------------------------------
+
+ reg [35:0] gpio_io;
+ reg [35:0] gpio_dat;
+ reg [35:0] gpio_ctl;
+
+ always @(posedge fast_clk)
+ gpio_io <= gpio_0;
+
+ genvar pin;
+ generate
+ for (pin = 0; pin < 36; pin = pin + 1)
+ begin: gpio0_assign
+ assign gpio_0[pin] = gpio_ctl[pin] ? gpio_dat[pin] : 1'bz;
+ end
+ endgenerate
+
+ // ------------------------------------------------------------------------
// Internal non-ABC I/O registers (MMU, turbo, LED)
// ------------------------------------------------------------------------
@@ -926,7 +949,7 @@ module abc80 (
reg turbo_set;
reg nmi_dis;
- assign mmu_wr_e = intio_sel & ~cpu_wr_n & (cpu_a[5:0] == 5'b00011);
+ assign mmu_wr_e = intio_sel & ~cpu_wr_n & (cpu_a[6:0] == 6'b000011);
always @(negedge rst_n or posedge fast_clk)
begin
@@ -950,6 +973,9 @@ module abc80 (
fgctl <= 8'h00;
fgpage <= 5'h04;
+
+ gpio_dat <= 36'b0;
+ gpio_ctl <= 36'b0;
end
else
begin
@@ -958,34 +984,62 @@ module abc80 (
if ( intio_sel & ~cpu_wr_n )
begin
- casex ( cpu_a[5:0] )
- 5'b00000:
+ casex ( cpu_a[6:0] )
+ 7'b0000000:
mmu_mod_addr[7:0] <= cpu_do[7:0];
- 5'b00001:
+ 7'b0000001:
mmu_mod_addr[9:8] <= cpu_do[1:0];
- 5'b00010:
+ 7'b0000010:
mmu_mod_data <= cpu_do[7:0];
- 5'b001xx:
+ 7'b00001xx:
mmu_map_sel <= cpu_do[3:0];
- 5'b100xx:
+ 7'b00100xx:
turbo_set <= 1;
- 5'b10100:
+ 7'b0010100:
prog_led_ctl <= cpu_do[1:0];
- 5'b10101:
+ 7'b0010101:
prog_led <= cpu_do[7:0];
- 5'b10110:
+ 7'b0010110:
prog_s7_0 <= cpu_do[7:0];
- 5'b10111:
+ 7'b0010111:
prog_s7_1 <= cpu_do[7:0];
- 5'b11000:
+ 7'b0011000:
prog_ledr[7:0] <= cpu_do[7:0];
- 5'b11001:
+ 7'b0011001:
prog_ledr[9:8] <= cpu_do[1:0];
- 5'b11110:
+ 7'b0011110:
fgctl <= cpu_do[7:0];
- 5'b11111:
+ 7'b0011111:
fgpage <= cpu_do[4:0];
- endcase // casex cpu_a[5:0] )
+ 7'b0100101:
+ gpio_dat[7:0] <= cpu_do;
+ 7'b0100110:
+ gpio_dat[15:8] <= cpu_do;
+ 7'b0100111:
+ gpio_dat[23:16] <= cpu_do;
+ 7'b0101000:
+ gpio_dat[31:24] <= cpu_do;
+ 7'b0101001:
+ gpio_dat[35:32] <= cpu_do[3:0];
+ 7'b0101010:
+ gpio_ctl[7:0] <= cpu_do;
+ 7'b0101011:
+ gpio_ctl[15:8] <= cpu_do;
+ 7'b0101100:
+ gpio_ctl[23:16] <= cpu_do;
+ 7'b0101101:
+ gpio_ctl[31:24] <= cpu_do;
+ 7'b0101110:
+ gpio_ctl[35:32] <= cpu_do[3:0];
+ 7'b0101111:
+ begin
+ if ( cpu_do[5:0] < 36 )
+ begin
+ gpio_ctl[cpu_do[5:0]] <= cpu_do[6];
+ gpio_dat[cpu_do[5:0]] <= cpu_do[7];
+ end
+ end
+ endcase // casex cpu_a[6:0] )
end // if ( intio_sel & ~cpu_wr_n )
else if ( ~abc_out_n[7] )
begin
@@ -995,38 +1049,68 @@ module abc80 (
end
else if ( intio_sel & ~cpu_rd_n )
begin
- casex ( cpu_a[5:0] )
- 5'b00000:
+ casex ( cpu_a[6:0] )
+ 7'b0000000:
intio_do <= mmu_mod_addr[7:0];
- 5'b00001:
+ 7'b0000001:
intio_do <= { 6'b0, mmu_mod_addr[9:8] };
- 5'b00010:
+ 7'b0000010:
intio_do <= mmu_rd_data[7:0];
- 5'b00011:
+ 7'b0000011:
intio_do <= mmu_rd_data[15:8];
- 5'b001xx:
+ 7'b00001xx:
intio_do <= { 4'b0, mmu_map_sel };
- 5'b100xx:
+ 7'b00100xx:
intio_do <= { 6'b0, cpu_turbo };
- 5'b10100:
+ 7'b0010100:
intio_do <= { 6'b0, prog_led_ctl };
- 5'b10101:
+ 7'b0010101:
intio_do <= prog_led;
- 5'b10110:
+ 7'b0010110:
intio_do <= prog_s7_0;
- 5'b10111:
+ 7'b0010111:
intio_do <= prog_s7_1;
- 5'b11000:
+ 7'b0011000:
intio_do <= prog_ledr[7:0];
- 5'b11001:
+ 7'b0011001:
intio_do <= prog_ledr[9:8];
- 5'b11110:
+ 7'b0011110:
intio_do <= fgctl;
- 5'b11111:
+ 7'b0011111:
intio_do <= { 3'b0, fgpage };
+ 7'b0100000:
+ intio_do <= gpio_io[7:0];
+ 7'b0100001:
+ intio_do <= gpio_io[15:8];
+ 7'b0100010:
+ intio_do <= gpio_io[23:16];
+ 7'b0100011:
+ intio_do <= gpio_io[31:24];
+ 7'b0100100:
+ intio_do <= { 4'b0, gpio_io[35:32] };
+ 7'b0100101:
+ intio_do <= gpio_dat[7:0];
+ 7'b0100110:
+ intio_do <= gpio_dat[15:8];
+ 7'b0100111:
+ intio_do <= gpio_dat[23:16];
+ 7'b0101000:
+ intio_do <= gpio_dat[31:24];
+ 7'b0101001:
+ intio_do <= { 4'b0, gpio_dat[35:32] };
+ 7'b0101010:
+ intio_do <= gpio_ctl[7:0];
+ 7'b0101011:
+ intio_do <= gpio_ctl[15:8];
+ 7'b0101100:
+ intio_do <= gpio_ctl[23:16];
+ 7'b0101101:
+ intio_do <= gpio_ctl[31:24];
+ 7'b0101110:
+ intio_do <= { 4'b0, gpio_ctl[35:32] };
default:
intio_do <= 8'hFF;
- endcase // casex ( cpu_a[5:0] )
+ endcase // casex ( cpu_a[6:0] )
end // if ( intio_sel & ~cpu_rd_n )
end
end
diff --git a/ports.txt b/ports.txt
new file mode 100644
index 0000000..1c3cdac
--- /dev/null
+++ b/ports.txt
@@ -0,0 +1,32 @@
+128 - MMU modify page select
+129 - MMU modify bank select
+130 - MMU data
+132 - MMU active map select
+144 - turbo
+148 - LED control
+149 - Green LEDs
+150 - 7seg right
+151 - 7seg left
+152 - Red LEDs 7:0
+153 - Red LEDs 9:8
+158 - FGCTL
+159 - FG 16K page select
+160 - GPIO pin read 7:0
+161 - GPIO pin read 15:8
+162 - GPIO pin read 23:16
+163 - GPIO pin read 31:24
+164 - GPIO pin read 35:32
+165 - GPIO output data 7:0
+166 - GPIO output data 15:8
+167 - GPIO output data 23:16
+168 - GPIO output data 31:24
+169 - GPIO output data 35:32
+170 - GPIO control (0 = input, 1 = output) 7:0
+171 - GPIO control (0 = input, 1 = output) 15:8
+172 - GPIO control (0 = input, 1 = output) 23:16
+173 - GPIO control (0 = input, 1 = output) 31:24
+174 - GPIO control (0 = input, 1 = output) 35:32
+175 - GPIO set a single bit:
+ bits 5:0 = GPIO number (0-35)
+ bit 6 = GPIO control
+ bit 7 = GPIO output data