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authorH. Peter Anvin <hpa@zytor.com>2016-11-12 19:52:42 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-12 19:56:02 (GMT)
commit96bc9d3b62de6025ad7eff76c7d7277fa4497bb0 (patch)
tree710e1067c8919c7d9a7c7666c2dd9232e730afd0
parentd6d263a84329e201055db188eb814efb6f1fa71f (diff)
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Fix OUT 7 to the memory map: it was blocked by ~intio_selsramshare
Obviously, iotio_sel will be zero for OUT 7. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.v34
1 files changed, 15 insertions, 19 deletions
diff --git a/abc80.v b/abc80.v
index 334f13a..324f118 100644
--- a/abc80.v
+++ b/abc80.v
@@ -1204,8 +1204,7 @@ module abc80 (
wire intio_sel; // Selected for access via I/O ports
reg [7:0] intio_do; // Data out from MMU I/O ports
- reg intio_sel_q;
- reg abc_out_7_q;
+ reg iorq_q;
reg turbo_set;
reg nmi_dis;
@@ -1252,20 +1251,26 @@ module abc80 (
revrom_addr <= 8'h00;
- intio_sel_q <= 1'b0;
- abc_out_7_q <= 1'b0;
+ iorq_q <= 1'b0;
end
else
begin
- intio_sel_q <= intio_sel; // Make it a one-shot only
- abc_out_7_q <= ~abc_out_n[7];
+ iorq_q <= ~cpu_iorq_n;
+
+ if ( ~cpu_wr_n & ~cpu_iorq_n & cpu_m1_n & ~iorq_q &
+ ((cpu_a[7:2] == 6'b100001) |
+ (cpu_a[7] == 1'b0 & cpu_a[4:0] == 4'b0111)) )
+ begin
+ mmu_map <= cpu_do[1:0];
+ nmi_dis <= cpu_do[2];
+ end
if ( ~intio_sel )
begin
intio_do <= ~8'h00;
turbo_set <= 1'b0;
end
- else if ( intio_sel & ~intio_sel_q & ~cpu_wr_n )
+ else if ( intio_sel & ~iorq_q & ~cpu_wr_n )
begin
casez ( cpu_a[6:0] )
7'b0000000:
@@ -1274,11 +1279,8 @@ module abc80 (
mmu_mod_addr[10:8] <= cpu_do[2:0];
7'b0000010:
mmu_mod_data <= cpu_do[7:0];
- 7'b00001zz:
- begin
- mmu_map <= cpu_do[1:0];
- nmi_dis <= cpu_do[2];
- end
+ // 7'b00001zz:
+ // See above - mmu_map/nmi_dis
7'b0001000:
revrom_addr <= cpu_do;
7'b00100zz:
@@ -1333,13 +1335,7 @@ module abc80 (
end
endcase // casez cpu_a[6:0] )
end // if ( intio_sel & ~cpu_wr_n )
- else if ( ~abc_out_n[7] & ~abc_out_7_q )
- begin
- // For compatibility with Mikrodatorn's 64K hack
- mmu_map <= cpu_do[1:0];
- nmi_dis <= cpu_do[2];
- end
- else if ( intio_sel & ~intio_sel_q & ~cpu_rd_n )
+ else if ( intio_sel & ~iorq_q & ~cpu_rd_n )
begin
casez ( cpu_a[6:0] )
7'b0000000: