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authorH. Peter Anvin <hpa@zytor.com>2016-11-11 05:27:46 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-11 05:30:19 (GMT)
commit5a042e65f65e999d9d0df3049a1190d01f24411c (patch)
treef1ed187eb7be5f5f9ed851ec69b470913c20d1e1
parentf82772116d1024cea9a05278394a0550a75e3427 (diff)
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Create a revision ID ROM which can be read from ABC
Create a revision ID ROM readable from ABC (via I/O ports 136 and 137) so we have a hope of not getting ourselves confused about which revision of ABC80-DE1 we are currently running. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.qsf27
-rw-r--r--abc80.v36
-rw-r--r--data/revrom.pl56
-rw-r--r--data/revrom.tcl2
-rw-r--r--mega/revrom.v157
-rw-r--r--ports.txt4
6 files changed, 265 insertions, 17 deletions
diff --git a/abc80.qsf b/abc80.qsf
index 5d25c0f..5b54b42 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -564,6 +564,19 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to ext_clock
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+set_global_assignment -name SLD_FILE "/home/hpa/abc80/abc80-de1/stp2_auto_stripped.stp"
+set_global_assignment -name VERILOG_FILE mega/revrom.v
set_global_assignment -name VERILOG_FILE mega/fgfifo.v
set_global_assignment -name VERILOG_FILE sync.v
set_global_assignment -name VERILOG_FILE mega/bgram.v
@@ -604,18 +617,8 @@ set_global_assignment -name VERILOG_FILE hexled.v
set_global_assignment -name VERILOG_FILE hexascii.v
set_global_assignment -name VERILOG_FILE abc80.v
set_global_assignment -name SDC_FILE abc80.sdc
-
-
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
-set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
-set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
-set_global_assignment -name ECO_OPTIMIZE_TIMING ON
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SOURCE_FILE db/abc80.cmp.rdb
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
-
set_global_assignment -name SIGNALTAP_FILE stp2.stp
-set_global_assignment -name SLD_FILE "/home/hpa/abc80/abc80-de1/stp2_auto_stripped.stp"
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:data/revrom.tcl"
+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/abc80.v b/abc80.v
index b1dfd55..411f2cc 100644
--- a/abc80.v
+++ b/abc80.v
@@ -1149,10 +1149,21 @@ module abc80 (
wire intio_sel; // Selected for access via I/O ports
reg [7:0] intio_do; // Data out from MMU I/O ports
+ reg intio_sel_q;
reg turbo_set;
reg nmi_dis;
+ // Revision ROM
+ reg [7:0] revrom_addr;
+ wire [7:0] revrom_q;
+
+ revrom revrom (
+ .address ( revrom_addr ),
+ .clock ( fast_clk ),
+ .q ( revrom_q )
+ );
+
assign mmu_wr_e = intio_sel & ~cpu_wr_n & (cpu_a[6:0] == 6'b000011);
always @(negedge rst_n or posedge fast_clk)
@@ -1182,13 +1193,21 @@ module abc80 (
gpio_dat <= 36'b0;
gpio_ctl <= 36'b0;
+
+ revrom_addr <= 8'h00;
+
+ intio_sel_q <= 1'b0;
end
else
begin
- intio_do <= ~8'b0;
- turbo_set <= 1'b0;
+ intio_sel_q <= intio_sel; // Make it a one-shot only
- if ( intio_sel & ~cpu_wr_n )
+ if ( ~intio_sel )
+ begin
+ intio_do <= ~8'h00;
+ turbo_set <= 1'b0;
+ end
+ else if ( intio_sel & ~intio_sel_q & ~cpu_wr_n )
begin
casez ( cpu_a[6:0] )
7'b0000000:
@@ -1202,6 +1221,8 @@ module abc80 (
mmu_map <= cpu_do[1:0];
nmi_dis <= cpu_do[2];
end
+ 7'b0001000:
+ revrom_addr <= cpu_do;
7'b00100zz:
turbo_set <= 1'b1;
7'b0010100:
@@ -1260,7 +1281,7 @@ module abc80 (
mmu_map <= cpu_do[1:0];
nmi_dis <= cpu_do[2];
end
- else if ( intio_sel & ~cpu_rd_n )
+ else if ( intio_sel & ~intio_sel_q & ~cpu_rd_n )
begin
casez ( cpu_a[6:0] )
7'b0000000:
@@ -1273,6 +1294,13 @@ module abc80 (
intio_do <= mmu_rd_data[15:8];
7'b00001zz:
intio_do <= { video_width, 4'b0, nmi_dis, mmu_map };
+ 7'b0001000:
+ intio_do <= revrom_addr;
+ 7'b0001001:
+ begin
+ intio_do <= revrom_q;
+ revrom_addr <= revrom_addr + 1'b1;
+ end
7'b00100zz:
intio_do <= { 6'b0, cpu_turbo };
7'b0010100:
diff --git a/data/revrom.pl b/data/revrom.pl
new file mode 100644
index 0000000..cf2e033
--- /dev/null
+++ b/data/revrom.pl
@@ -0,0 +1,56 @@
+#!/usr/bin/perl
+
+use POSIX;
+use bytes;
+
+my $depth = 256;
+
+my @now = localtime(time);
+my $year = $now[5] + 1900;
+my $mon = $now[4] + 1;
+
+my $gitrev;
+if (open(my $gitrevfd, '-|', 'git', 'describe')) {
+ $gitrev = <$gitrevfd>;
+ chomp $gitrev;
+ close($gitrevfd);
+}
+
+my $s = "ABC80-DE1 FPGA emulator\n";
+$s .= "Copyright 2003-$year H. Peter Anvin\n";
+if (defined($gitrev)) {
+ $s .= "Revision: $gitrev\n";
+}
+$s .= POSIX::strftime("Build: %Y-%m-%d %H:%M:%S\n", @now);
+
+my $rs;
+($rs = $s) =~ s/\n/\r\n/g;
+my @sb = (int($year / 100), $year % 100, $mon, $now[3],
+ $now[2], $now[1], $now[0]);
+push(@sb, (0) x (16 - scalar(@sb))); # Reserved
+push(@sb, unpack("C*", $rs));
+push(@sb, (0) x ($depth - scalar(@sb)));
+
+print "%\n";
+my $sq;
+($sq = $s) =~ tr/\%/\$/;
+print $sq;
+print "%\n";
+print "DEPTH = $depth;\n";
+print "WIDTH = 8;\n";
+print "ADDRESS_RADIX = HEX;\n";
+print "DATA_RADIX = HEX;\n";
+print "CONTENT\n";
+print "BEGIN\n";
+
+for (my $i = 0; $i < $depth; $i++) {
+ my $sc;
+ if ($sb[$i] >= 32 && $sb[$i] <= 126) {
+ $sc = sprintf(" '%c'", $sb[$i], $sb[$i]);
+ } else {
+ $sc = '';
+ }
+ printf "%02X : %02X; -- %3u %s\n", $i, $sb[$i], $sb[$i], $sc;
+}
+
+print "END";
diff --git a/data/revrom.tcl b/data/revrom.tcl
new file mode 100644
index 0000000..001be8a
--- /dev/null
+++ b/data/revrom.tcl
@@ -0,0 +1,2 @@
+#!/usr/bin/tclsh
+exec perl data/revrom.pl > data/revrom.mif
diff --git a/mega/revrom.v b/mega/revrom.v
new file mode 100644
index 0000000..a2d5b59
--- /dev/null
+++ b/mega/revrom.v
@@ -0,0 +1,157 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: revrom.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module revrom (
+ address,
+ clock,
+ q);
+
+ input [7:0] address;
+ input clock;
+ output [7:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [7:0] sub_wire0;
+ wire [7:0] q = sub_wire0[7:0];
+
+ altsyncram altsyncram_component (
+ .address_a (address),
+ .clock0 (clock),
+ .q_a (sub_wire0),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .address_b (1'b1),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clock1 (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .data_a ({8{1'b1}}),
+ .data_b (1'b1),
+ .eccstatus (),
+ .q_b (),
+ .rden_a (1'b1),
+ .rden_b (1'b1),
+ .wren_a (1'b0),
+ .wren_b (1'b0));
+ defparam
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.init_file = "./data/revrom.mif",
+ altsyncram_component.intended_device_family = "Cyclone II",
+ altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=REVR",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 256,
+ altsyncram_component.operation_mode = "ROM",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.widthad_a = 8,
+ altsyncram_component.width_a = 8,
+ altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
+// Retrieval info: PRIVATE: JTAG_ID STRING "REVR"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "./data/revrom.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "./data/revrom.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=REVR"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL revrom_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/ports.txt b/ports.txt
index 1c3cdac..c5ef5c6 100644
--- a/ports.txt
+++ b/ports.txt
@@ -1,7 +1,9 @@
128 - MMU modify page select
129 - MMU modify bank select
130 - MMU data
-132 - MMU active map select
+132 - MMU active map select (same as out 7)
+136 - Revision ROM address
+137 - Revision ROM data
144 - turbo
148 - LED control
149 - Green LEDs