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authorH. Peter Anvin <hpa@zytor.com>2016-11-15 08:41:21 (GMT)
committerH. Peter Anvin <hpa@zytor.com>2016-11-15 08:41:21 (GMT)
commit58001a2749e4c18f8167c808c384a5255c0bb125 (patch)
tree563661d579be5f6e2ca47147ee81a8431c58fc6c
parentc82eafb59f3f18021b29d145d5ddc4fa88442cf0 (diff)
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neopixel: latch the data in the right cycle and it works...
We only need one clock cycle before reading the SRAM data, not two. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--abc80.qsf47
-rw-r--r--abc80.sdc2
-rw-r--r--neopixel.v10
3 files changed, 15 insertions, 44 deletions
diff --git a/abc80.qsf b/abc80.qsf
index 2ce9640..f6cc4be 100644
--- a/abc80.qsf
+++ b/abc80.qsf
@@ -433,7 +433,7 @@ set_global_assignment -name GENERATE_JAM_FILE ON
# SignalTap II Assignments
# ========================
-set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
@@ -628,43 +628,12 @@ set_global_assignment -name SDC_FILE abc80.sdc
set_global_assignment -name SOURCE_FILE db/abc80.cmp.rdb
set_global_assignment -name SIGNALTAP_FILE stp2.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
-set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll1:pll1|altpll:altpll_component|_clk2" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to npled_do -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to npled_do -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=4096" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=4096" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to gpio_io[2] -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "neopixel:neopixel|e_data[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "neopixel:neopixel|e_in_rst[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "neopixel:neopixel|pulse[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "neopixel:neopixel|pulse[1]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to np_enable -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to gpio_io[2] -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "neopixel:neopixel|e_data[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "neopixel:neopixel|e_in_rst[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "neopixel:neopixel|pulse[0]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "neopixel:neopixel|pulse[1]" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to np_enable -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=7" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=7" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=47" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=8651" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=56101" -section_id auto_signaltap_0
set_global_assignment -name SLD_FILE "/home/hpa/abc80/abc80-de1/stp1_auto_stripped.stp"
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name DISABLE_OCP_HW_EVAL ON
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
+set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 10000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 10000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 10000
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/abc80.sdc b/abc80.sdc
index cd9197f..cfb373e 100644
--- a/abc80.sdc
+++ b/abc80.sdc
@@ -20,7 +20,9 @@ set_clock_groups -asynchronous \
set_multicycle_path -from [get_keepers {mmuram*q_a[*]}] -to [get_keepers {sram_*_q*}] 4
set_multicycle_path -start -from [get_keepers {msel*[*]}] -to [get_clocks {pll1|*|clk[2]}] 2
set_multicycle_path -from [get_clocks {pll1|*|clk[2]}] -to [get_keepers {sram_*_q*}] 2
+set_multicycle_path -from [get_keepers {neopixel:*}] -to [get_keepers {sram_*_q*}] 6
set_multicycle_path -start -from [get_keepers {sram_q[*]}] -to [get_clocks {pll1|*|clk[1] pll1|*|clk[2]}] 2
+set_multicycle_path -start -from [get_keepers {npled_do}] -to [get_keepers {neopixel:*}] 5
# I/O pin constraints
set_input_delay -clock {pll1|*|clk[0]} -min 0ns [get_ports {sram_dq[*]}]
diff --git a/neopixel.v b/neopixel.v
index 28ebc2c..008abd8 100644
--- a/neopixel.v
+++ b/neopixel.v
@@ -149,21 +149,21 @@ module neopixel (
if ( ~b_ena )
begin
b_stat_d[15:0] = b_conf_addr;
- b_stat_d[32:16] = ~9'b0;
+ b_stat_d[32:24] = ~9'b0;
end
else
begin
- if (&b_ctr[7:5] ) // New byte?
+ if (&b_ctr[7:5]) // New byte?
begin
b_stat_d[15:0] = b_stat_addr + 1'b1;
if ( b_ctr[9] ) // New word?
begin
- if ( b_stat_end | ~&b_stat_pctr )
+ if ( b_stat_end | ~|b_stat_pctr )
b_stat_d[15:0] = b_conf_addr;
b_stat_d[23:16] =
- (( b_stat_end | ~&b_stat_pctr ) ?
+ (( b_stat_end | ~|b_stat_pctr ) ?
b_conf_plen : b_stat_pctr) - 1'b1;
b_stat_d[32:24] =
@@ -180,7 +180,7 @@ module neopixel (
else
b_in_rst <= ~b_ena | b_stat_cctr[8];
- // b_ctr[2:0] is inverted as bit order is bigendian
+ // b_ctr[7:5] is inverted as bit order is bigendian
assign ram_a = { b_stat_addr, ~b_ctr[7:5] };
// D stage, data out from SRAM, parallel out